New fixes for pins

sw/include/blacksasi.h

@@ -6,7 +6,7 @@
 #include "config.h"
 #include "scsi.h"
 // Log File
-#define VERSION "0.xx-SNAPSHOT-BLACKSASI-2022-09-28-F4"
+#define VERSION "0.xx-SNAPSHOT-BLACKSASI-2022-09-28"
 
 #define LOG_FILENAME "LOG.txt"
 
@@ -70,6 +70,11 @@
 #define isHigh(XX) ((XX) == high)
 #define isLow(XX) ((XX) != high)
 
+#define TR_INPUT 0
+#define TR_OUTPUT 1
+#define DB_INPUT 1
+#define DB_OUTPUT 0
+
 // GPIO register port
 #define PAREG GPIOA->regs
 #define PBREG GPIOB->regs
@@ -192,25 +197,6 @@ enum SCSI_DEVICE_TYPE
 #define MAX_SCSI_COMMAND  0xff
 #define SCSI_COMMAND_HANDLER(x) static byte x(SCSI_DEVICE *dev, const byte *cdb)
 
-
-#define ATN       PB14      // SCSI:ATN
-#define BSY       PB6      // SCSI:BSY
-#define ACK       PB7     // SCSI:ACK
-#define RST       PA15     // SCSI:RST
-#define MSG       PE2      // SCSI:MSG
-#define SEL       PE3      // SCSI:SEL
-#define CD        PE4      // SCSI:C/D
-#define REQ       PE5      // SCSI:REQ
-#define IO        PB1      // SCSI:I/O
-
-#define LED1      PA4     // LED
-#define LED2      PA5     // Driven LED
-#define LED3      PA6     // Driven LED
-// Image Set Selector
-#define IMAGE_SELECT1   PC4
-#define IMAGE_SELECT2   PC5
-
-
 #define NOP(x) for(unsigned _nopcount = x; _nopcount; _nopcount--) { asm("NOP"); }
 
 /* SCSI Timing delays */
@@ -271,63 +257,27 @@ static const uint32_t scsiDbInputOutputPullAnd_PEREG  = 0b0000000000000000000101
 #define SCSI_DB_INPUT()  { PDREG->MODER = (PDREG->MODER & scsiDbInputOutputAnd_PDREG); PEREG->MODER = (PEREG->MODER & scsiDbInputOutputAnd_PEREG); SCSI_DATABUS_IN();}
 #define SCSI_SET_PULL()  { PDREG->PUPDR |= scsiDbInputOutputPullAnd_PDREG; PEREG->PUPDR |= scsiDbInputOutputPullAnd_PEREG; }
 
-/*
-static const uint32_t scsiDbOutputRegOr = 0x55150011;
-static const uint32_t scsiDbInputOutputAnd = 0x00C0FFCC;
-// Put DB and DP in output mode
-#define SCSI_DB_OUTPUT() { PBREG->MODER = (PBREG->MODER & scsiDbInputOutputAnd) | scsiDbOutputRegOr; }
-
-// Put DB and DP in input mode
-#define SCSI_DB_INPUT()  { PBREG->MODER = (PBREG->MODER & scsiDbInputOutputAnd); }
-*/
-
-#if XCVR == 1
-
-#define TR_TARGET        PC2   // Target Transceiver Control Pin
-#define TR_DBP           PC0   // Data Pins Transceiver Control Pin
-#define TR_INITIATOR     PC1   // Initiator Transciever Control Pin
-
-#define vTR_TARGET       PC(2) // Target Transceiver Control Pin
-#define vTR_DBP          PC(0) // Data Pins Transceiver Control Pin
-#define vTR_INITIATOR    PC(1) // Initiator Transciever Control Pin
-
-#define TR_INPUT 0
-#define TR_OUTPUT 1
-
 // Transceiver control definitions
 #define TRANSCEIVER_IO_SET(VPIN,TR_INPUT) { GPIOREG(VPIN)->BSRR = BITMASK(VPIN) << ((TR_INPUT) ? 16 : 0); }
 
 
 //                                                      5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 
 static const uint32_t SCSI_TARGET_PORTD_AND        = 0b11111111111111111100111111111111;
-//                                                      5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 
 static const uint32_t SCSI_TARGET_PORTD_OR         = 0b00000000000000000001000000000000;
 
 //                                                      5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 
 static const uint32_t SCSI_TARGET_PORTE_AND        = 0b11111111111111111100000110000011;
-//                                                      5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 
 static const uint32_t SCSI_TARGET_PORTE_OR         = 0b00000000000000000001010100010000;
 
 // Turn on the output only for BSY
 #define SCSI_BSY_ACTIVE()      { PEREG->MODER = (PEREG->MODER & SCSI_TARGET_PORTE_AND) | SCSI_TARGET_PORTE_OR; PDREG->MODER = (PDREG->MODER & SCSI_TARGET_PORTD_AND) | SCSI_TARGET_PORTD_OR; SCSI_OUT(vBSY, active) }
 
 // BSY,REQ,MSG,CD,IO Turn off output, BSY is the last input
-#define SCSI_TARGET_INACTIVE() { PEREG->MODER = (PEREG->MODER & SCSI_TARGET_PORTE_AND); PDREG->MODER = (PDREG->MODER & SCSI_TARGET_PORTD_AND); TRANSCEIVER_IO_SET(vTR_TARGET,TR_INPUT); }
+#define SCSI_TARGET_INACTIVE() { PEREG->MODER = (PEREG->MODER & SCSI_TARGET_PORTE_AND); PDREG->MODER = (PDREG->MODER & SCSI_TARGET_PORTD_AND); TRANSCEIVER_IO_SET(vTAD,TR_INPUT); }
 
 #define SCSI_TARGET_ACTIVE()   { PEREG->MODER = (PEREG->MODER & SCSI_TARGET_PORTE_AND) | SCSI_TARGET_PORTE_OR; PDREG->MODER = (PDREG->MODER & SCSI_TARGET_PORTD_AND) | SCSI_TARGET_PORTD_OR; }
 
-#else
 
-// Turn on the output only for BSY
-#define SCSI_BSY_ACTIVE()      { pinMode(BSY, OUTPUT_OPEN_DRAIN); SCSI_OUT(vBSY,  active) }
-
-// BSY,REQ,MSG,CD,IO Turn off output, BSY is the last input
-#define SCSI_TARGET_INACTIVE() { SCSI_OUT(vREQ,inactive); SCSI_PHASE_CHANGE(SCSI_PHASE_DATAOUT); SCSI_OUT(vBSY,inactive); pinMode(BSY, INPUT); }
-
-// BSY,REQ,MSG,CD,IO Turn on the output (no change required for OD)
-#define SCSI_TARGET_ACTIVE()   { }
-
-#endif
 
 // HDDimage file
 #define HDIMG_ID_POS  2                 // Position to embed ID number
@@ -350,11 +300,11 @@ static uint32_t genBSRR(uint32_t data) {
   // Positions array indicates which bit position each data bit goes in
   // positions[0] is for data bit 0, position[1] for data bit 1, etc
   // DB0, DB1, DB2, DB4, DB5, DB6, DB7 in order
-  uint8_t positions[] = {8UL, 9UL, 10UL, 2UL, 12UL, 13UL, 14UL, 15UL};
+  uint8_t positions[] = {0UL, 1UL, 2UL, 3UL, 4UL, 5UL, 6UL, 7UL};
   uint8_t dbpPosition = 0UL;
   int reqPosition = 6;
   uint8_t bitsAsserted = 0;
-
+ //PM2022 Fix this in better way since we now have the bits correct
   uint32_t output = 0x00000000;
   for (int i = 0; i < 8; i++) {
     if (data & (0x1 << masks[i])) {
@@ -390,8 +340,7 @@ static uint32_t genBSRR(uint32_t data) {
 // Parity bit acquisition
 #define PARITY(DB) (db_bsrr[DB]&1)
 
-// #define GET_CDB6_LBA(x) ((x[2] & 01f) << 16) | (x[3] << 8) | x[4]
-#define READ_DATA_BUS() (byte)((~(uint32_t)GPIOB->regs->IDR)>>8)
+#define READ_DATA_BUS() (byte)((~(uint32_t)GPIOD->regs->IDR)>>8)
 
 
 

sw/platformio.ini

@@ -11,12 +11,14 @@
 [env:blacksasi_f411]
 platform = ststm32
 board = blacksasi_f411m
-board.variants_dir = /home/pm/project/stm32/BlackSASI/sw/variant/blacksasi_f411m
+;board.variants_dir = /home/pm/project/stm32/BlackSASI/sw/variant/blacksasi_f411m
+
+board.variants_dir = C:\Users\martenssonp\projects\BlackSASI\sw\variant\blacksasi_f411m
 framework = arduino
 board_build.core = maple
-;lib_deps =
-;    greiman/SdFat@^2.2.0
- ;   bblanchon/ArduinoJson@^6.19.3
+lib_deps =
+    greiman/SdFat@^2.2.0
+   bblanchon/ArduinoJson@^6.19.3
 upload_protocol = stlink
 debug_tool = stlink
 ; Different gcc versions produce much different binaries in terms of speed.

sw/src/main.cpp

@@ -46,8 +46,7 @@
 #define DEBUG            1      // 0:No debug information output
                                 // 1: Debug information output to USB Serial
                                 // 2: Debug information output to LOG.txt (slow)
-#define XCVR             1      // 0 for standard mode
-                                // 1 for transceiver hardware
+
 
 
 #ifndef MCU_STM32F401CC
@@ -59,11 +58,7 @@
 #define VDS "2022-09-20"
 
 // Log File
-#if XCVR == 1
 #define VERSION "1.1-" VDS "-XCVR-" MCV
-#else
-#define VERSION "1.1-" VDS "-" MCV
-#endif
 #define LOG_FILENAME "LOG.txt"
 
 #include "blacksasi.h"
@@ -139,7 +134,7 @@ inline byte readIO(void)
 {
   // Port input data register
   uint32_t ret = GPIOD->regs->IDR;
-  byte bret = (byte)~(((ret >> 8) & 0b11110111) | ((ret & 0x00000004) << 1));
+  byte bret = (byte)~(((ret >> 8) & 0b11111111));
 #if READ_PARITY_CHECK
   if((db_bsrr[bret]^ret)&1)  // TODO fix parity calculation
     m_sts |= 0x01; // parity error
@@ -299,7 +294,6 @@ void setup()
     db_bsrr[i] = genBSRR(i);
   }
   gpioInit();
-  digitalWrite( BOARD_TRANS_OE ,0);
   // Default all SCSI command handlers to onUnimplemented
   for(unsigned i = 0; i < MAX_SCSI_COMMAND; i++)
   {
@@ -372,81 +366,38 @@ void setup()
 #endif
   delay(3000);
 
-  // PIN initialization
-  pinMode(BOARD_LED1_PIN, OUTPUT);
-  pinMode(BOARD_LED2_PIN, OUTPUT);
-  
-  // Image Set Select Init
-  pinMode(IMAGE_SELECT1, INPUT_PULLUP);
-  pinMode(IMAGE_SELECT2, INPUT_PULLUP);
-  pinMode(IMAGE_SELECT1, INPUT);
-  pinMode(IMAGE_SELECT2, INPUT);
-  int image_file_set = ((digitalRead(IMAGE_SELECT1) == LOW) ? 1 : 0) | ((digitalRead(IMAGE_SELECT2) == LOW) ? 2 : 0);
+
+  int image_file_set = ((digitalRead(BOARD_SWITCH1_PIN) == LOW) ) | ((digitalRead(BOARD_SWITCH2_PIN) == LOW) ) << 1 | ((digitalRead(BOARD_SWITCH3_PIN) == LOW) ) << 2 | ((digitalRead(BOARD_SWITCH4_PIN) == LOW) ) << 3;
   
-#if XCVR == 1
+
   // Transceiver Pin Initialization
-  pinMode(TR_TARGET, OUTPUT);
-  pinMode(TR_INITIATOR, OUTPUT);
-  pinMode(TR_DBP, OUTPUT);
+  pinMode(BOARD_SCSI_TAD, OUTPUT);
+  pinMode(BOARD_SCSI_IND, OUTPUT);
+  pinMode(BOARD_SCSI_DTD, OUTPUT);
   
-  TRANSCEIVER_IO_SET(vTR_INITIATOR,TR_INPUT);
-  TRANSCEIVER_IO_SET(vTR_TARGET,TR_INPUT);
-#else
-  // set up OTYPER for open drain on SCSI pins of PA and PB
-  // PA 0-7, 11-14
-  uint32_t oTypeA_And = 0x000078FF;
-  // PA 8, 9, 10, 15
-  uint32_t oTypeA_Or = 0x00008700;
-#ifndef MCU_STM32F401CC
-  GPIOA->regs->OTYPER = (GPIOA->regs->OTYPER & oTypeA_And) | oTypeA_Or;
-#endif
+  TRANSCEIVER_IO_SET(vIND,TR_INPUT);
+  TRANSCEIVER_IO_SET(vTAD,TR_INPUT);
 
-  // PB 1, 11 are not used
-  uint32_t oTypeB_And = 0x00000802;
-  // PB 0, 2-10, 12-15 are used for SCSI, set open drain
-  uint32_t oTypeB_Or = 0x0000F7FD;
-#ifndef MCU_STM32F401CC
-  GPIOB->regs->OTYPER = (GPIOB->regs->OTYPER & oTypeB_And) | oTypeB_Or;
-#endif
-#endif
 
   SCSI_DB_INPUT()
 
-#if XCVR == 1
-  TRANSCEIVER_IO_SET(vTR_DBP,TR_INPUT);
+  TRANSCEIVER_IO_SET(vDTD,DB_INPUT);
   
   // Initiator port
-  pinMode(ATN, INPUT);
-  pinMode(BSY, INPUT);
-  pinMode(ACK, INPUT);
-  pinMode(RST, INPUT);
-  pinMode(SEL, INPUT);
-  TRANSCEIVER_IO_SET(vTR_INITIATOR,TR_INPUT);
+  pinMode(BOARD_SCSI_ATN, INPUT);
+  pinMode(BOARD_SCSI_BSY, INPUT);
+  pinMode(BOARD_SCSI_ACK, INPUT);
+  pinMode(BOARD_SCSI_RST, INPUT);
+  pinMode(BOARD_SCSI_SEL, INPUT);
+  TRANSCEIVER_IO_SET(vIND,TR_INPUT);
 
   // Target port
-  pinMode(MSG, INPUT);
-  pinMode(CD, INPUT);
-  pinMode(REQ, INPUT);
-  pinMode(IO, INPUT);
-  TRANSCEIVER_IO_SET(vTR_TARGET,TR_INPUT);
+  pinMode(BOARD_SCSI_MSG, INPUT);
+  pinMode(BOARD_SCSI_CD, INPUT);
+  pinMode(BOARD_SCSI_REQ, INPUT);
+  pinMode(BOARD_SCSI_IO, INPUT);
+  TRANSCEIVER_IO_SET(vTAD,TR_INPUT);
   
-#else
-
-  // Input port
-  pinMode(ATN, INPUT_PULLUP);
-  pinMode(BSY, INPUT_PULLUP);
-  pinMode(ACK, INPUT_PULLUP);
-  pinMode(RST, INPUT_PULLUP);
-  pinMode(SEL, INPUT_PULLUP);
-
-  // Output port
-  pinMode(MSG, OUTPUT_OPEN_DRAIN);
-  pinMode(CD, OUTPUT_OPEN_DRAIN);
-  pinMode(REQ, OUTPUT_OPEN_DRAIN);
-  pinMode(IO, OUTPUT_OPEN_DRAIN);
-  
-#endif
-
   // Turn off the output port
   SCSI_TARGET_INACTIVE()
 
@@ -517,7 +468,7 @@ void setup()
   finalizeFileLog();
   LED1_OFF();
   //Occurs when the RST pin state changes from HIGH to LOW
-  attachInterrupt(RST, onBusReset, FALLING);
+  attachInterrupt(BOARD_SCSI_RST, onBusReset, FALLING);
 }
 
 void findDriveImages(FsFile root) {
@@ -738,9 +689,9 @@ void longjmpFromInterrupt(jmp_buf jmpb, int retval) {
  */
 void onBusReset(void)
 {
-  if(isHigh(digitalRead(RST))) {
+  if(isHigh(digitalRead(BOARD_SCSI_RST))) {
     delayMicroseconds(20);
-    if(isHigh(digitalRead(RST))) {
+    if(isHigh(digitalRead(BOARD_SCSI_RST))) {
   // BUS FREE is done in the main process
 //      gpio_mode(MSG, GPIO_OUTPUT_OD);
 //      gpio_mode(CD,  GPIO_OUTPUT_OD);
@@ -794,9 +745,7 @@ inline void writeHandshake(byte d)
 {
   // This has a 400ns bus settle delay built in. Not optimal for multi-byte transfers.
   GPIOB->regs->BSRR = db_bsrr[d]; // setup DB,DBP (160ns)
-#if XCVR == 1
-  TRANSCEIVER_IO_SET(vTR_DBP,TR_OUTPUT)
-#endif
+  TRANSCEIVER_IO_SET(vDTD,DB_OUTPUT)
   SCSI_DB_OUTPUT() // (180ns)
   // ACK.Fall to DB output delay 100ns(MAX)  (DTC-510B)
   SCSI_OUT(vREQ,inactive) // setup wait (30ns)
@@ -811,9 +760,7 @@ inline void writeHandshake(byte d)
   
   // REQ.Raise to DB hold time 0ns
   SCSI_DB_INPUT() // (150ns)
-#if XCVR == 1
-  TRANSCEIVER_IO_SET(vTR_DBP,TR_INPUT)
-#endif
+  TRANSCEIVER_IO_SET(vDTD,DB_INPUT)
   while( SCSI_IN(vACK));
 }
 
@@ -828,9 +775,7 @@ inline void writeHandshake(byte d)
  * Alignment matters. For the 3 instruction wait loops,it looks like crossing
  * an 8 byte prefetch buffer can add 2 cycles of wait every branch taken.
  */
-#if XCVR == 0
-void writeDataLoop(uint32_t blocksize, const byte* srcptr) __attribute__ ((aligned(8)));
-#endif
+
 void writeDataLoop(uint32_t blocksize, const byte* srcptr) {
 #define REQ_ON() (PBREG->BSRR = req_rst_bit);
 #define FETCH_BSRR_DB() (bsrr_val = bsrr_tbl[*srcptr++])
@@ -855,24 +800,14 @@ void writeDataLoop(uint32_t blocksize, const byte* srcptr) {
   WAIT_ACK_ACTIVE();
   REQ_OFF_DB_SET(bsrr_val);
   // Align the starts of the do/while and WAIT loops to an 8 byte prefetch.
-#if XCVR == 0
-  asm("nop.w;nop");
-#endif
+
   do{
     WAIT_ACK_INACTIVE();
     REQ_ON();
     // 4 cycles of work
     FETCH_BSRR_DB();
-    // Extra 1 cycle delay while keeping the loop within an 8 byte prefetch.
-#if XCVR == 0
-    asm("nop");
-#endif
     WAIT_ACK_ACTIVE();
     REQ_OFF_DB_SET(bsrr_val);
-    // Extra 1 cycle delay, plus 4 cycles for the branch taken with prefetch.
-#if XCVR == 0
-    asm("nop");
-#endif
   }while(srcptr < endptr);
   WAIT_ACK_INACTIVE();
   // Finish the last bus cycle, byte is already on DB.
@@ -892,15 +827,11 @@ void writeDataPhase(int len, const byte* p)
   LOG(" DI ");
   SCSI_PHASE_CHANGE(SCSI_PHASE_DATAIN);
   // Bus settle delay 400ns. Following code was measured at 800ns before REQ asserted. STM32F103.
-#if XCVR == 1
-  TRANSCEIVER_IO_SET(vTR_DBP,TR_OUTPUT)
-#endif
+  TRANSCEIVER_IO_SET(vDTD,TR_OUTPUT)
   SCSI_DB_OUTPUT()
   writeDataLoop(len, p);
   SCSI_DB_INPUT()
-#if XCVR == 1
-  TRANSCEIVER_IO_SET(vTR_DBP,TR_INPUT)
-#endif
+  TRANSCEIVER_IO_SET(vDTD,DB_INPUT)
 }
 
 /*
@@ -915,9 +846,7 @@ void writeDataPhaseSD(SCSI_DEVICE *dev, uint32_t adds, uint32_t len)
   uint64_t pos = (uint64_t)adds * dev->m_rawblocksize;
   dev->m_file->seekSet(pos);
 
-#if XCVR == 1
-  TRANSCEIVER_IO_SET(vTR_DBP,TR_OUTPUT)
-#endif
+  TRANSCEIVER_IO_SET(vDTD,DB_OUTPUT)
   SCSI_DB_OUTPUT()
   
   for(uint32_t i = 0; i < len; i++) {
@@ -929,9 +858,7 @@ void writeDataPhaseSD(SCSI_DEVICE *dev, uint32_t adds, uint32_t len)
     writeDataLoop(dev->m_blocksize, &m_buf[dev->m_sector_offset]);
   }
   SCSI_DB_INPUT()
-#if XCVR == 1
-  TRANSCEIVER_IO_SET(vTR_DBP,TR_INPUT)
-#endif
+  TRANSCEIVER_IO_SET(vDTD,DB_INPUT)
 }
 
 #pragma GCC push_options
@@ -1047,20 +974,18 @@ void MsgIn2(int msg)
  */
 void loop() 
 {
-#if XCVR == 1
   // Reset all DB and Target pins, switch transceivers to input
   // Precaution against bugs or jumps which don't clean up properly
   SCSI_DB_INPUT();
-  TRANSCEIVER_IO_SET(vTR_DBP,TR_INPUT)
+  TRANSCEIVER_IO_SET(vDTD,DB_INPUT)
   SCSI_TARGET_INACTIVE();
-  TRANSCEIVER_IO_SET(vTR_TARGET,TR_INPUT)
-
 
   // Reset target state bits (BSY, MSG, CD, REQ, IO)
-  GPIOB->regs->BSRR = 0x000000E8; // MSG, CD, REQ, IO
-  GPIOA->regs->BSRR = 0x00000200; // BSY
-  TRANSCEIVER_IO_SET(vTR_INITIATOR,TR_INPUT)
-#endif
+
+  GPIOE->regs->BSRR = 0x00000074; // MSG, CD, REQ, IO
+  GPIOB->regs->BSRR = 0x00000040; // BOARD_SCSI_BSY
+  TRANSCEIVER_IO_SET(vTAD,TR_INPUT)
+  TRANSCEIVER_IO_SET(vIND,TR_INPUT)
   LED3_ON();
 
   //int msg = 0;
@@ -1088,17 +1013,15 @@ void loop()
   }
   // We've been selected
 
-#if XCVR == 1
-  TRANSCEIVER_IO_SET(vTR_TARGET,TR_OUTPUT);
-  TRANSCEIVER_IO_SET(vTR_INITIATOR,TR_OUTPUT);
-#endif
+  TRANSCEIVER_IO_SET(vTAD,TR_OUTPUT);
+  TRANSCEIVER_IO_SET(vIND,TR_OUTPUT);
   SCSI_TARGET_ACTIVE()  // (BSY), REQ, MSG, CD, IO output turned on
 
   // Set BSY to-when selected
   SCSI_BSY_ACTIVE();     // Turn only BSY output ON, ACTIVE
 
   // Wait until SEL becomes inactive
-  while(isHigh(digitalRead(SEL))) {}
+  while(isHigh(digitalRead(BOARD_SCSI_SEL))) {}
   
   // Ask for a TARGET-ID to respond
   m_id = 31 - __builtin_clz(scsiid);
@@ -1111,7 +1034,7 @@ void loop()
   enableResetJmp();
   
   // In SCSI-2 this is mandatory, but in SCSI-1 it's optional 
-  if(isHigh(digitalRead(ATN))) {
+  if(isHigh(digitalRead(BOARD_SCSI_ATN))) {
     SCSI_PHASE_CHANGE(SCSI_PHASE_MESSAGEOUT);
     // Bus settle delay 400ns. Following code was measured at 350ns before REQ asserted. Added another 50ns. STM32F103.
     SCSI_PHASE_CHANGE(SCSI_PHASE_MESSAGEOUT);// 28ns delay STM32F103
@@ -1120,7 +1043,7 @@ void loop()
     int syncperiod = 50;
     int syncoffset = 0;
     int msc = 0;
-    while(isHigh(digitalRead(ATN)) && msc < 255) {
+    while(isHigh(digitalRead(BOARD_SCSI_ATN)) && msc < 255) {
       m_msb[msc++] = readHandshake();
     }
     for(int i = 0; i < msc; i++) {
@@ -1287,16 +1210,14 @@ BusFree:
   //SCSI_OUT(vIO ,inactive) // gpio_write(IO, low);
   //SCSI_OUT(vBSY,inactive)
   SCSI_TARGET_INACTIVE() // Turn off BSY, REQ, MSG, CD, IO output
-#if XCVR == 1
-  TRANSCEIVER_IO_SET(vTR_TARGET,TR_INPUT);
-  TRANSCEIVER_IO_SET(vTR_INITIATOR,TR_INPUT);
+  TRANSCEIVER_IO_SET(vTAD,TR_INPUT);
+  TRANSCEIVER_IO_SET(vIND,TR_INPUT);
   // Something in code linked after this function is performing better with a +4 alignment.
   // Adding this nop is causing the next function (_GLOBAL__sub_I_SD) to have an address with a last digit of 0x4.
   // Last digit of 0xc also works.
   // This affects both with and without XCVR, currently without XCVR doesn't need any padding.
   // Until the culprit can be tracked down and fixed, it may be necessary to do manual adjustment.
   asm("nop.w");
-#endif
 }
 
 static byte onUnimplemented(SCSI_DEVICE *dev, const byte *cdb)

sw/src/sdcard.cpp

@@ -95,9 +95,9 @@ void switchImage(void){
                   digitalRead(BOARD_SWITCH3_PIN) << 2 |  
                   digitalRead(BOARD_SWITCH4_PIN) << 3)) & 0x0F;
     if ( oldimageSelect!=imageSelect){
-    Serial.print("Image: ");
-    Serial.println(imageSelect);
-    Serial.flush();
+    serial.print("Image: ");
+    serial.println(imageSelect);
+    serial.flush();
     }