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@@ -78,21 +78,30 @@
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#define PEREG GPIOE->regs
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#define PEREG GPIOE->regs
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// Termination control (LOW is active)
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// Termination control (LOW is active)
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-// 12 8 4 0 12 8 4 0
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-#define TERMINATION_HIGH() PBREG->BSRR = 0b0000000100000000 << 16 | 0b0000001000000000;
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-#define TERMINATION_LOW() PBREG->BSRR = 0b0000001000000000 << 16 | 0b0000000100000000;
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-#define TERMINATION_OFF() PBREG->BSRR = 0b0000001100000000;
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+#define TERMINATION_HIGH() GPIOREG(BOARD_SCSI_TERM_HIGH)->BSRR = (1 << BOARD_SCSI_TERM_HIGH % 16) << 16 | (1 << BOARD_SCSI_TERM_LOW % 16);
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+#define TERMINATION_LOW() GPIOREG(BOARD_SCSI_TERM_HIGH)->BSRR = (1 << BOARD_SCSI_TERM_LOW % 16) << 16 | (1 << BOARD_SCSI_TERM_HIGH % 16);
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+#define TERMINATION_OFF() GPIOREG(BOARD_SCSI_TERM_HIGH)->BSRR = (1 << BOARD_SCSI_TERM_HIGH % 16) | (1 << BOARD_SCSI_TERM_LOW % 16);
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// Enable SCSI buffers
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// Enable SCSI buffers
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-// 12 8 4 0
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-#define SCSI_OUTPUT_ENABLE() PBREG->BSRR = 0b0001000000000000 << 16 ;
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-#define SCSI_OUTPUT_DISABLE() PBREG->BSRR = 0b0001000000000000;
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-
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+#define SCSI_OUTPUT_ENABLE() GPIOREG(BOARD_TRANS_OE)->BSRR = (1 << (BOARD_TRANS_OE % 16)) << 16;
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+#define SCSI_OUTPUT_DISABLE() GPIOREG(BOARD_TRANS_OE)->BSRR = (1 << (BOARD_TRANS_OE % 16));
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// SCSI Data Direction
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// SCSI Data Direction
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-// 12 8 4 0
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-#define SCSI_BUFFERS_IN() PCREG->BSRR = 0b0000000000000001 << 16 ;
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-#define SCSI_BUFFERS_OUT() PCREG->BSRR = 0b0000000000000001;
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+#define SCSI_DATABUS_IN() GPIOREG(BOARD_SCSI_DTD)->BSRR = (1 << (BOARD_SCSI_DTD % 16)) << 16;
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+#define SCSI_DATABUS_OUT() GPIOREG(BOARD_SCSI_DTD)->BSRR = (1 << (BOARD_SCSI_DTD % 16))
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+
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+// SCSI IND Direction
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+#define SCSI_IND_IN() GPIOREG(BOARD_SCSI_IND)->BSRR = (1 << (BOARD_SCSI_IND % 16));
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+#define SCSI_IND_OUT() GPIOREG(BOARD_SCSI_IND)->BSRR = (1 << (BOARD_SCSI_IND % 16)) << 16;
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+
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+//SCSI Data and IND Direction
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+#define SCSI_DATABUS_IND_IN() GPIOREG(BOARD_SCSI_DTD)->BSRR = ((1 << (BOARD_SCSI_DTD % 16)) << 16) | (1 << (BOARD_SCSI_IND % 16));
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+#define SCSI_DATABUS_IND_OUT() GPIOREG(BOARD_SCSI_DTD)->BSRR = ((1 << (BOARD_SCSI_IND % 16)) << 16) | (1 << (BOARD_SCSI_DTD % 16));
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+
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+// SCSI TAD Direction
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+
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+#define SCSI_TAD_IN() GPIOREG(BOARD_SCSI_TAD)->BSRR = (1 << (BOARD_SCSI_TAD % 16));
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+#define SCSI_TAD_OUT() GPIOREG(BOARD_SCSI_TAD)->BSRR = (1 << (BOARD_SCSI_TAD % 16)) << 16;
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// Virtual pin (Arduio compatibility is slow, so make it MCU-dependent)
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// Virtual pin (Arduio compatibility is slow, so make it MCU-dependent)
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#define PA(BIT) (BIT)
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#define PA(BIT) (BIT)
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@@ -119,11 +128,10 @@
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#define vIND PC(1) // SCSI:IND
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#define vIND PC(1) // SCSI:IND
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#define vTAD PC(2) // SCSI:TAD
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#define vTAD PC(2) // SCSI:TAD
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#define vTRANS_OE PB(12) // SCSI:TRANS_OE
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#define vTRANS_OE PB(12) // SCSI:TRANS_OE
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-// SCSI output pin control: opendrain active LOW (direct pin drive)
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+// SCSI output pin control: active LOW (direct pin drive)
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#define SCSI_OUT(VPIN,ACTIVE) { GPIOREG(VPIN)->BSRR = BITMASK(VPIN) << ((ACTIVE) ? 16 : 0); }
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#define SCSI_OUT(VPIN,ACTIVE) { GPIOREG(VPIN)->BSRR = BITMASK(VPIN) << ((ACTIVE) ? 16 : 0); }
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// SCSI input pin check (inactive=0,active=1)
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// SCSI input pin check (inactive=0,active=1)
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-//BLACKSASI need to be checked
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#define SCSI_IN(VPIN) ((~GPIOREG(VPIN)->IDR >> ((VPIN % 16) & 15)) & 1)
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#define SCSI_IN(VPIN) ((~GPIOREG(VPIN)->IDR >> ((VPIN % 16) & 15)) & 1)
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// HDDiamge file
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// HDDiamge file
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