first commit

LICENSE

@@ -0,0 +1,339 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Lesser General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
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+
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+
+                    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
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+    Gnomovision version 69, Copyright (C) year name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
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+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
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+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.

Makefile

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+# This Makefile requires GNU Make or equivalent.
+include os.mk
+
+TARGET = abc80diag
+ASMFILES = $(TARGET:%=%.asm)
+CIMFILES = $(TARGET:%=%.cim)
+BDSFILES = $(TARGET:%=%.bds)
+BINFILES = $(TARGET:%=%.bin)
+HEXFILES = $(TARGET:%=%.hex)
+
+all: $(BINFILES)
+trs80m13diag.bin: inc/z80.mac inc/spt.mac inc/spt.asm inc/memtestmarch.asm inc/trs80m13con.asm inc/trs80music.asm Makefile os.mk
+trs80m2diag.bin: inc/z80.mac inc/spt.mac inc/spt.asm inc/memtestmarch.asm inc/trs80m2con.asm inc/trs80m2fdcboot.asm Makefile os.mk 
+trs80m4pdiag.bin: inc/z80.mac inc/spt.mac inc/spt.asm inc/memtestmarch.asm inc/trs80m2con.asm Makefile os.mk 
+
+.PHONY: clean realclean
+clean: 
+	-$(RM) $(wildcard $(BDSFILES) $(TARGET:%=%.txt) $(TARGET:%=%.lst))
+
+realclean: clean
+	-$(RM) $(wildcard $(CIMFILES) $(BINFILES) $(HEXFILES))
+
+
+$(BDSFILES): %.bds: %.bin
+CDDD = truncate
+ASSEMBLE = $(ZMAC) --zmac -m --od . --oo cim,bds,lst,hex
+CDD = $(CDDD) -s 4096 abc80diag.bin
+%.bin: %.asm Makefile
+	@-$(CECHO) $(SGR_COMMAND) $(ASSEMBLE) $< $(SGR_RESET)
+	@-$(CECHON) $(SGR_OUTPUT)
+	@$(ASSEMBLE) $<
+	@-$(CECHON) $(SGR_RESET)
+	@$(REN) $(<:%.asm=%.cim) $@
+	@-$(CECHON) $(SGR_SIZE)
+	@$(STAT) "%N: %z %Xz" $@
+	@-$(CECHON) $(SGR_RESET)
+		@$(CDD) 
+
+.PHONY: emu 
+
+MODEL = -m3
+# MEM = 32
+EMUFLAGS = $(MODEL) $(foreach h,$(HD),-h $(h)) $(foreach m,$(MEM),-mem $(m)) -turbo
+# EMUFLAGS = $(MODEL) $(foreach h,$(HD),-h $(h)) $(foreach m,$(MEM),-mem $(m))
+
+emu emu1 emu1l emu3: trs80m13diag.emu
+emu2 emu12 emu16 emu6k: trs80m2diag.emu
+emu4p: trs80m4pdiag.emu
+
+emu1: MODEL = -m1 -nlc -nld
+emu1l: MODEL = -m1
+
+emu3: MODEL = -m3
+
+emu2: MODEL = -m2
+emu2: HD = ~/w/trs80/trs80-hard-disk-0.hdv
+emu12: MODEL = -m12
+emu16: MODEL = -m16
+emu6k: MODEL = -m6000
+
+# emu4: MODEL = -m4
+emu4p: MODEL = -m4p
+# emu4d: MODEL = -m4d
+
+
+BREAKFLAGS=$(foreach brk,$(B),-b $(brk))
+
+%.emu: %.bds %.bin
+	$(EMU) -ee -vol 20 -rand $(EMUFLAGS) $(BREAKFLAGS) -rom $*.bin -ls $*.bds $(E)
+
+.DEFAULT: all
+.PHONY: all

README.md

@@ -0,0 +1,206 @@
+# TRS-80 Diagnostic ROM
+
+Model I with 4K:
+
+![Normal Operation, M3 48K](documentation/M1_4k_animated.gif)
+
+Model III with 48K:
+
+![Normal Operation, M1 4K](documentation/M3_48k_animated.gif)
+
+Model II with 128K:
+
+![Normal Operation, M2 128K](documentation/M2_128k_animated.gif)
+
+Model 4P with 128K:
+
+![Normal Operation, M4P 128K](documentation/M4p_128k_animated.gif)
+
+#### Main contributors:
+- Dave Giller KI3V - Programmer and designer
+- Frank IZ8DWF - Testing methodology and initial test routines
+- Adrian Black - Testing, initial concept and QA
+
+## Introduction from Adrian
+
+This project was born out of a broken TRS-80 Model III that I was working on. I could not tell if the system was even "executing code," so I used an early version of this ROM to help diagnose the problem.
+
+Please know that the main goal of this ROM is to test the functionality of the video RAM (VRAM) and the dynamic RAM (DRAM, system memory.) It does not test any other component unrelated to those two subsystems. If a TRS-80 has good VRAM and DRAM, it should boot into basic where you can then run further tests. 
+
+You should familiarize yourself with the system schematics and design of the TRS-80 before using this ROM since problems in other areas of the system can sometimes manifest themselves of a RAM problem. 
+
+Videos:
+- Model III Repair [Part 1](https://youtu.be/EGFKjjlvKf4) and [Part 2](https://youtu.be/Hh8dRgtu1Jk)
+- [Model III, Diagnostic ROM Companion Video](https://youtu.be/4fuuyLiSgsE)
+- [Model II, Diagnostic ROM test](https://youtu.be/azsTZ-Cmijs)
+- Model 1 Repair and VRAM upgrade [Part 1](https://youtu.be/rGhkX6O1lRo) and [Part 2](https://youtu.be/LzTM_MTWcGA)
+- Model 4P, Repair video [Part 1](https://youtu.be/-EhhU-mCyp0), [Part 2](https://youtu.be/JgqqT4Ewgzs), Part 3 Coming soon.
+
+In addition, most (all?) RAM tests contained inside the stock boot ROM and even disk/tape based tests use a very rudimentary RAM test that are inadequate to detect subtle RAM problems. While the test in this new diagnostic ROM isn't the end-all, be-all of RAM tests, we feel it is better than the typical simple bit pattern tests used elsewhere. The RAM test implemented here is a "march" test, which we have found to be much more reliable at detecting a variety of different RAM fault modes.
+
+## Feature List
+
+- ***Working DRAM or VRAM is not required.***  The initial release of this ROM could use 8-bit VRAM for its stack, or use the first bank of DRAM as a stack if it tested good.  This ROM now does not require a stack, and can run on a machine with faults in both VRAM and DRAM.  For more information, see [this explanation of the techniques used to operate in the absence of working RAM](spt.md).
+	- Keep in mind however, that other faults, such as address line problems, can keep this (or any) ROM from running properly.
+- One ROM image for **TRS-80 Model I, or III**
+	- Audio feedback via the cassette port, so you can tell what's happening even if you have no video display.
+	- Auto detection of VRAM type (The Model I comes with 7-bit VRAM)
+	- Auto detection of bank size (4k or 16k)
+		- A machine with 4K bank size cannot have RAM at 12K ($7000).  If the ROM tests that region and finds all bits bad, it assumes this is a 4K machine.
+		- Officially, a machine with a 4K bank can only have 4K total, so this ROM does not test beyond the first bank in that case.
+	- Testing up to 48k of DRAM, looping continually.
+- One ROM image for **TRS-80 Model II** with all DRAM sizes.
+	- The same image is expected to work with the Model 12, 16, 16B or 6000, although this is not tested.
+	- Testing full 2K of VRAM
+	- Testing up to 512K of DRAM, looping continually.
+	- Temporarily relocates the test subroutine into previously tested RAM at `$4000` and unmaps the ROM from Z80 address space to test the RAM between `$0000` and `$3FFF`.
+		- The stock BOOT ROM does not test the region of DRAM from `$0000`-`$0FFF` that is hidden while the ROM is mapped. It also does not test any RAM above 32k -- so any faults in the untested parts of RAM will go undetected. This ROM tests 100% of the DRAM.
+	- _This version of the ROM has preliminary support for booting to floppy or hard drive (incluyding FreHD48).  There are known issues with booting at this time, and the symptoms vary between the Model II, 12, 16, 16B, and 6000._
+- One ROM image for **TRS-80 Model 4P** with 64K or 128K.
+	- This is an early version that tests all RAM _**except**_ the lowest 16K.
+		- Testing the lowest 16K will require a relocating test similar to what is done for the Model II tests, but this is not yet implemented.
+	- If the machine has 128K, the upper bank if tested in two halves.
+	- This ROM has only been tested on the model 4P, but is expected to work on the model 4 and 4D as well (all GA and NGA models).
+- All ROM images fit within 2K so the ROM can be used on any machine in the range using a normal 2716 EPROM.
+
+
+### Future improvements
+
+- Testing the ROM on "Big Tandy" systems like the Model 12, 16, and 6000.
+- Testing on the Model 4 and 4D
+- Porting the diagnostic routines to other Z80 systems
+	- Kaypro II'83, 4'83, 10, 2'84, 4'84, 1
+- More comprehensive documentation
+
+## What the ROM does
+
+- Makes sounds to let you know the ROM is running even if the display is not operating properly:
+	- On the Model 1/III:
+		- Makes a beep from the cassette port (so you can know the system is executing the ROM.)
+	- On the Model 4P:
+		- Makes a beep from the internal speaker.
+	- On the Model II:
+		- Accesses the built-in floppy drive three times.  The activity light should activate and the head solenoid should click. (See Model II video above to see this in operation.)
+- Set the system to 64 or 80 column mode depending on the machine.
+	- On the Model 4P, displays a test pattern in 80 column mode for a visual test of the VRAM as well as a test of the 80-column hardware.  Then switches to 64-column mode for the rest of the tests, including the March VRAM test.
+- Tests the video RAM using a March C test.
+	- On the Model I/III:
+		- Tests for 7-bit Model I VRAM (fake bit 6) and identifies it if found.
+	- On the Model I/III/4P:
+		- Beeps a good (rising tones) or bad (tune ending on low note) VRAM sound. 
+		- If the VRAM is bad, it will show a test pattern on the screen, then beep out which bit(s) are bad repeatedly.
+	- On the Model II:
+		- If the VRAM is bad, it will show a test pattern on the screen, then blink the drive light on floppy 0
+			- The bits of VRAM are indicated by long or short blinks, counting from bit 7 down to bit 0.
+				- A long blink means that bit is bad.  A short blink means that bit is good.
+- Clears screen and writes a welcome message.
+- On the Model I/III:
+	- If the first bank of DRAM only has 4K:
+		- Tests that first bank of 4k repeatedly. These systems cannot have more than 4K of RAM, so nothing above 4K is tested.
+	- If the first bank of DRAM is 16k:
+		- Tests all three DRAM banks (48K) repeatedly.  Missing banks (e.g., for a 16K or 32K machine) will be listed with all bits in error (`76543210`).
+- On the Model I/III/4P:
+	- After each test, the diagnostic will play a good bank or bad bank tune. If a bad bank exists, it will beep out which bits are bad and print this to screen.
+	- It is possible to run the diagnostic ROM with NO DRAM installed at all. It will still work properly.
+- The Model II can (theoretically) have up to 512K of DRAM:
+	- The first 32K of DRAM (from `$0000` to `$7FFF`) is always present, but at boot time, the ROM is mapped in and makes the RAM from `$0000` to `$0FFF` inaccessible.
+		- The diagnostic first tests the second physical bank of DRAM located at `$4000-$7FFF`.  
+			- If that bank passes testing, the ROM copies a portion of itself to `$4000`, and passes control to this copy.
+				- The relocated copy unmaps the ROM, exposing all of RAM from `$0000` to `$3FFF`, which it then tests.  Afterwards, it re-maps the ROM to appear at `$0000` again, and hands control back to the ROM.
+			- If the bank at `$4000-$7FFF` fails testing, the ROM skips the test of DRAM from `$0000` to `$3FFF`.
+		- Then the diagnostic tests all possible DRAM pages (`$0-$F`), bank-switching them in turn into the region `$8000-$FFFF`.
+		- It is possible to run the diagnostic with NO DRAM installed at all. It will still work properly. 
+
+
+## Running this diagnostic ROM on a TRS-80 Model I or Model III
+
+The Diagnostic ROM is less than 2K in size, so it will fit completely within a 2716.
+
+To use this diagnostic ROM on a TRS-80 Model III, you must first make or buy an adapter to allow use of an EPROM in the U104 ROM socket. This socket is designed for a 2364 which does not have a compatible pinout with a 2764 EPROM. Adapter PCBs are widely available on the usual sources, or you can make some PCBs at this link:
+
+[PCBway Project Link for EPROM adapter](https://www.pcbway.com/project/shareproject/Adapter_2364___27128__by_Bobbel_.html)
+
+The assembled ROM, ready to be burned to EPROM or EEPROM, is `trs80testrom.bin` or `trs80testrom.hex`.  Both contain the same ROM image, so you can use whichever is more convenient with your EPROM programmer's software.
+
+One you have a programmed 2764 or 28B64C, insert that into the adapter and install it into U104 on the Model III. This is the boot ROM that the CPU starts to execute code from at power-up.  (Address `$0000`)
+  
+On a TRS-80 Model I, you can install the 2716 chip right into the motherboard in left-most socket. This is the same socket the Level II ROM expansion ribbon cable connects to and is the method we recommend you use. 
+
+You can also install the ROM into the Level II ROM upgrade board on the keyboard side, but the layout of these ROM chips can vary depending on revision of the upgrade. You must install the 2364 adapter or possibly a 2732 into the socket containing the primary boot ROM. If using the 2364 to 2764 adapter in this socket, you will need to load the ROM image into `$1000` due to one address line being tied to VCC. 
+  
+- The beep codes for bit errors are as follows:
+	- First a long middle tone is played:
+		- A single tone for the first bank, two for the second, and three for the third
+	- Then after a short pause, the good/bad bits are identified:
+		- If all bits are good, a long high tone is played.
+		- If all bits are **bad**, a long **low** tone is played.
+		- If some bits are good and some bad, the bits are identified starting with bit 7 and counting down to bit 0:
+			- A short high tone indicates this bit is good.
+			- A short **low** tone indicates this bit is bad.
+- For example, if your second 16K bank (locations `$8000-$BFFF`) have bits 5 and 3 bad, the following tones will play:
+	- MID(long) MID(long) (pause) HI HI **low** HI **low** HI HI HI
+- If _only_ bit 6 of VRAM is bad, the diagnostic will further test to see if bit 6 is "faked" as the NOR of bits 5 and 7.  
+	- If it is, you will not hear a beep code because the ROM identifies this as the normal 7-bit VRAM in a stock Model I machine.
+	- If bit 6 of VRAM is not consistently the NOR of bits 5 and 7, the screen will be filled with copies of the character set, and the error will be repeatedly reported as tones (HI **low** HI HI HI HI HI HI, identifying bad bit 6).
+
+## Running this diagnostic ROM on a TRS-80 Model II
+
+***WARNING***: **You use this ROM (or really, do any troubleshooting inside a Model II or its derivatives) at your own risk!** 
+
+The CRT on the Model II (and all of the "Big Tandy" machines that use a 6845 CRT Controller chip) and could be damaged if they are powered on and run without a valid signal from the video controller board.  It is ***very important*** that you are careful to connect all of the video-related cables properly.  Also, while we have tested this ROM to program the CRTC correctly, if your EPROM chip is not programmed successfully or not inserted into the ROM socket correctly such that no ROM code runs, the video board will not output any video signal.  Even if you are sure everything has been prepared correctly, make sure you are ready to cut power if you hear strange sounds from the CRT or anything doesn't seem right.  We've been warned that the technical documentation says you have roughly ***3 seconds*** to cut power before there is risk of damage to the CRT.  We don't know if that's true, but we don't want anyone to damage their machine, so if you proceed, do so with caution.
+
+Do note: this code currently depends on proper operation of the FDC.  Specifically it awaits proper responses from the FDC while it toggles the activity light and head loading solenoid on and off.  In the near future this will be modified to wait appropriate time periods, but not to rely on the data read from the locations where the FDC status registers should be. During testing, even without the FDC installed, the diagnostics ran properly, likely due to the response bit being 0 when read back even with the controller removed. It may not work this way on all systems, as the data bus will be floating during this read operation and results can be erratic. 
+
+The ROM image fits into a 2716, so it is easiest to use one and install that into the single ROM socket on the CPU board. Alternatively, you can use the 2364 to 2764 adapter mentioned above, but as with the TRS-80 Model 1, you must load the ROM into `$1000` when programming. 
+
+As soon as you power on the machine, you should hear the floppy drive clicking, even before the CRT warms up, so you know the diagnostic code is running.
+
+_This version of the ROM has preliminary support for booting to floppy or hard drive (incluyding FreHD48).  There are known issues with booting at this time, and the symptoms vary between the Model II, 12, 16, 16B, and 6000._ **To ensure that this ROM loops the RAM tests indefinitely instead of attempting to boot your system, make sure there is no bootable floppy in drive 0, and make sure any hard drive (or HD emulator) is disconnected or powered off before running this ROM.**
+
+_This section to be completed._
+
+## Running this diagnostic ROM on a TRS-80 Model 4/4P
+
+Note: The ROM has only been tested on a 4P. It should work on the 4/4D, but YMMV.
+
+On the 4P, the stock boot ROM is just a 2332, so you can use a TMS-2532A to replace it, or use a 2732 EPROM but you have to swap around the top address line and also ground the output enable pin. (The 2332 doesn't have this pin, so the motherboard holds that pin at 5V.) 
+
+Flash the test ROM code into the EPROM and install into the motherboard. You should hear a start-up been and then, if the RAM test is running, you will hear beeps indicated the testing of each part of RAM. 
+
+You can actually run the TRS-80 Model 1/III ROM in the Model 4P, and it does work. It will only test 64 column mode and only test 48k of DRAM, but if you have problem with the system running in 80 column mode, this may be a good test to see how well the system is running. 
+
+## Other troubleshooting notes
+
+- On the Model III, you **must** have a working connection between JP2A and JP2B to run this diagnostic. Both the cassette port (for audio output) and the video subsystem is accessed by the CPU via this interconnect. Bits 0 and 1 of this interconnection are needed for the cassette port audio, but all 8 bits are required for video to work. 
+- You do not need the interconnect between JP1A and JP1B. This is used by only the floppy and serial board. The system will operate fine without the interconnect, but you will not be able to use the floppy or serial port. 
+- On the Model III, the cassette port output is the pin closest to the keyboard connector (Connector J3). On the Model I, you can either clip a test lead onto the cassette port, or use the cassette DIN cable to get audio output. 
+- You do not need any DRAM installed in the machine for the diagnostic to run. If you have good working VRAM but no working DRAM, you should see the DRAM tests run, and all banks will come back as bad. 
+- Keep in mind a stuck or bad DRAM bus transceiver can trash the entire bus, causing the VRAM test to also fail.
+- You do not need the keyboard connected for the system to run the diagnostic. The keyboard is not used during the test at all.
+- The diagnostic ROM **must** be installed into U104 on the TRS-80 Model III. You must use a 2364 to 27XXX adapter. The one Adrian used is made for 27128 devices, but it works just fine with 2764 and more conveniently 28B64C (EEPROMs.) 
+- You can also use this same adapter in U105 (for testing replacement of that ROM, **not** for running this diagnostic ROM). You can use a normal 2716 in U106 if you need to test replacing that ROM.
+- You do not need to have any ROM installed in U105 or U106 during the test, as they are not used by the diagnostics. A bad ROM in one of those sockets could cause the computer to not work, so if even this diagnostic ROM does not work, it would be advisable to try pulling those ROMs.
+
+## Knowing what might be wrong
+
+![Motherboard Components](https://github.com/misterblack1/trs80-diagnosticrom/blob/main/documentation/Model%203%20Motherboard%20Layout%20Small%20800.png?raw=true)
+
+The Model III motherboard layout is shown above. I recommend referring to the Radio Shack Technical Service Manual for help in identifying what components might be bad on your system, but the picture should give you a head-start.
+
+![Model I Motherboard](https://github.com/misterblack1/trs80-diagnosticrom/blob/main/documentation/Model%201%20DRAM%20and%20VRAM.png?raw=true)
+
+The Model I motherboard has only 1 bank of DRAM, which can 4k or 16k. If the system has 16k, then an additional 32k can be installed in an attached expansion interface.
+
+For the ROM position in the Level II PCB, you must figure out which ROM is the lower ROM. You may have to look up part numbers of the chips to figure that out. 
+
+![Model 4P Motherboard](https://github.com/misterblack1/trs80-diagnosticrom/blob/main/documentation/Model%204P.png?raw=true)
+
+The Model 4P motherboard has a 2332 bootrom, you need to use an adapter or a TMS2532A in this socker. If you have neither, you can use a 2732 EPROM but you must swap around a couple pins and ground hte /OE pin on the EPROM. (See pin outs of these chips to understand.)
+
+The RAM test on the 4/4P is not complete due to the way the banking works -- but it will FULLY test the upper 64k of RAM, so you can swap the lower bank chips with the upper bank to get a full test.
+
+## Building
+
+This repository will contain the assembled ROM image.  To assemble, you will need to use [George Phillips' `zmac` assembler](http://48k.ca/zmac.html).  
+
+Many thanks to George also for his [excellent `trs80gp` emulator](http://48k.ca/trs80gp.html) which includes integrated debugging facilities which dramatically reduced the time necessary to develop and debug these diagnostics.

abc80diag.asm

@@ -0,0 +1,448 @@
+; code: language=z80-asm tabSize=8
+
+; SIMULATE_ERROR = $80
+; SIMULATE_ERROR = $3C
+
+.include "inc/z80.mac"
+.include "inc/spt.mac"
+
+; Notes on global register allocation:
+;
+; This ROM doesn't work like typical Z80 code, which assumes the presence of a stack.
+; There may in fact be no working memory in the machine for holding the stack.
+;
+; An overall goal for this version of the code is to run in the absence of any working
+; ram at all.  There is no stack and no RAM variables.  The only storage of variables
+; is in registers, so the registers must be carefully preserved.
+;
+; Without a stack, that means either saving them to other registers and restoring before 
+; jumping to other code (remembering there can be no CALLs when there is no stack) 
+; or avoiding their use altogether.  These are extremely confining restrictions.
+;
+; Assembly purists will shudder at the extensive use of macros, but for sanity it
+; cannot be avoided.
+;
+; Globally, the contents of these registers must be preserved
+;	e = bit errors in the region of memory currently being tested
+;	ix = current location in VRAM for printing messages
+;	iy = current table entry for test parameters
+;
+
+VBASE  equ 7c00h
+VSIZE  equ 0400h
+VLINE  equ 40
+
+
+		.org 0000h				; z80 boot code starts at location 0
+reset:
+		di					; mask INT
+		im	1
+
+diagnostics:
+		ld	a,0
+		out	($EC),a				; set 64 char mode	
+		; ld	a,0				; byte to be written goes in A
+		out	($F8),a				; blank printer port for now
+
+test_vram:
+		SPTHREAD_BEGIN				; set up to begin running threaded code
+
+		dw spt_playmusic, tones_welcome
+
+		dw spt_select_test, tp_vram
+		dw memtestmarch				; test the VRAM
+		dw spt_check_7bit_vram
+		; dw spt_sim_error, $40
+		dw spt_jp_nc, .vram_ok
+
+		; we have bad vram
+		dw spt_chartest
+	.vram_bad_loop:
+		dw spt_play_testresult			; play the tones for bit errors
+		dw spt_pause, $0000
+		dw spt_jp,.vram_bad_loop
+
+	.vram_7bit:
+		dw spt_con_print, msg_ok7bit
+		; dw spt_play_testresult			; play the tones for bit errors
+		dw spt_jp,.vram_goodtones
+
+	.vram_ok:
+		dw spt_prepare_display
+		MAC_SPT_CON_GOTO 1,0
+		dw spt_announcetest 			; print results of VRAM tst
+		; dw print_biterrs
+		dw spt_jp_e_7bit_vram, .vram_7bit
+		dw spt_con_print, msg_ok8bit
+
+	.vram_goodtones:
+		dw spt_playmusic, tones_vramgood	; play the VRAM good tones
+
+	.vram_continue:
+		MAC_SPT_CON_GOTO 3,0
+
+		dw spt_select_test, tp_16k			; load the first test
+		dw spt_jp, .start
+
+SPT_SKIP_NMIVEC
+
+	.start	dw spt_con_goto
+			MAC_SPT_CON_OFFSET 3,0
+
+	.loop:	dw spt_announcetest 			; announce what test we are about to run
+		dw memtestmarch				; test the current bank
+		dw spt_jp_nc, .ok
+		
+		dw spt_con_print, msg_biterrs		; we have errors: print the bit string
+		dw print_biterrs
+		dw spt_play_testresult			; play the tones for bit errors
+		dw spt_jp, .cont
+	
+	.ok:	dw spt_con_print, msg_testok		; bank is good: print the OK message
+		dw spt_play_testresult			; play the tones
+
+	.cont:
+		dw spt_tp_next, .start
+		dw spt_jp, .loop
+
+
+;; -------------------------------------------------------------------------------------------------
+;; end of main program.
+
+spt_prepare_display:
+		SPTHREAD_ENTER
+		dw con_clear
+		dw spt_con_print, msg_banner		; print the banner
+		dw spt_print_charset
+		dw spt_exit
+
+spt_check_vram_contents:
+		pop	bc
+		ld	a,b
+		ld	d,c
+; confirm that all of VRAM contains the value in register A
+check_vram_contents:
+		ld	hl,VBASE
+		ld	bc,VSIZE
+	.fillloop:
+		ld	(HL),a
+		cpi
+		jp	pe,.fillloop
+
+		ld	hl,VBASE
+		ld	bc,VSIZE
+		ld	a,d
+	.readloop:
+		cpi
+		jr	nz,.bad
+		jp	pe,.readloop
+
+		or	a	; clear carry flag
+		ret
+	.bad:	scf
+		ret
+
+spt_check_7bit_vram:
+		ret	nc				; if carry flag is not set, do nothing
+		ld	a,01000000b
+		cp	e
+		jr	z,.scantests
+		scf					; something other than bit 6 is bad, so this is not 7bit VRAM
+		ret
+	.scantests:
+		SPTHREAD_ENTER
+		dw spt_check_vram_contents, $0040
+		dw spt_jp_c, .exit
+		dw spt_check_vram_contents, $FFBF
+		dw spt_jp_c, .exit
+		dw spt_check_vram_contents, $AAAA
+		dw spt_jp_c, .exit
+		dw spt_check_vram_contents, $5555
+		dw spt_jp_c, .exit
+	.exit:	dw spt_exit				; if carry flag is set, this is not good 7-bit VRAM
+
+
+spt_sim_error:
+		pop	de
+		scf
+		ret
+
+
+; test if the error is $FF (all bits bad)
+spt_jp_all_bits_bad:
+		pop	hl				; get the address for jumping if match
+		ld	a,$FF				; check for all bits bad
+		cp	e
+		ret	nz				; return without jump if there is NOT a match
+		ld	sp,hl				; else jump to the requested location
+		ret
+
+; test if the e register matches 7-bit vram and jump to spt address if match
+spt_jp_e_7bit_vram:
+		pop	hl				; get the address for jumping if match
+		ld	a,01000000b			; ignore bit 6
+		cp	e				; see if there are other errors
+		ret	nz				; return without jump if there is NOT a match
+		ld	sp,hl				; else jump to the requested location
+		ret
+
+; test if the e register matches 7-bit vram and jump to spt address if match
+spt_jp_e_zero:
+		pop	hl				; get the address for jumping if match
+		ld	a,0				; test clean
+		cp	e				; see if there are other errors
+		ret	nz				; return without jump if there is NOT a match
+		ld	sp,hl				; else jump to the requested location
+		ret
+
+
+; load the label string address from the current test parameter table entry into hl
+spt_ld_hl_tp_label:
+		ld	l,(iy+4)
+		ld	h,(iy+5)
+		ret
+
+; load the label string address from the current test parameter table entry into hl
+spt_ld_hl_tp_tones:
+		ld	l,(iy+6)
+		ld	h,(iy+7)
+		ret
+
+spt_ld_new_line:
+		ld	a,(iy+9)
+		ld ixh,a
+		ld	a,(iy+8)
+		ld ixl,a
+		ret
+; move to the next test parameter table entry
+spt_tp_next:	pop	hl				; get the address to jump to if we are starting over
+		ld 	bc,tp_size			; find the next entry
+		add 	iy,bc
+		ld	a,(iy+0)			; is the length zero?
+		add	a,(iy+1)
+		ret	nz				; no, use it
+		ld	c,(iy+2)			; yes, get the address of the first entry
+		ld	b,(iy+3)
+		ld	iy,0
+		add	iy,bc
+		; sub	a				; clear zero flag when restarting
+		ld	sp,hl				; jump to the next location
+		ret
+
+spt_announcetest:
+		; pop	hl				; get the message to be printed
+		SPTHREAD_ENTER
+		dw spt_ld_new_line
+		dw spt_ld_hl_tp_label
+		dw con_print				; picks up message from hl
+		dw spt_con_print, msg_testing
+		dw spt_con_index, -9
+		dw spt_exit
+
+
+spt_play_testresult:
+		SPTHREAD_SAVE				; save the stack pointer
+
+		SPTHREAD_BEGIN
+		dw spt_ld_hl_tp_tones			; play the ID tune for current bank
+		dw playmusic
+		dw spt_pause, $2000
+		SPTHREAD_END
+
+		ld	a,$FF
+		cp	e
+		jr	z,.allbad			; if all bits bad, play shorter tune
+
+		cpl
+		cp	e
+		jr	z,.allgood			; if all bits good, play shorter tune
+
+		ld	d,8				; play bit tune for each bit, high to low
+	.showbit:
+		rlc	e
+		jr	nc,.zero
+		ld	hl,tones_bitbad
+		jr	.msbe_cont
+	.zero:
+		ld	hl,tones_bitgood
+	.msbe_cont:
+		SPTHREAD_BEGIN
+		dw playmusic
+		dw spt_pause, $2000
+		SPTHREAD_END
+
+		; pause $4000
+		dec	d
+		jr	nz,.showbit
+		jr	.done
+	.allbad:
+		SPTHREAD_BEGIN
+		dw spt_playmusic, tones_bytebad
+		dw spt_pause, $8000
+		SPTHREAD_END
+		jr	.done
+	.allgood:
+		SPTHREAD_BEGIN
+		dw spt_playmusic, tones_bytegood
+		dw spt_pause, $8000
+		SPTHREAD_END
+	.done:
+		SPTHREAD_RESTORE			; restore the stack pointer
+		ret
+
+
+spt_pause:
+		pop	bc
+; pause by an amount specified in BC
+pause_bc:
+	.loop:
+		dec	bc
+		ld	a,b
+		or	c
+		jr	nz,.loop
+		ret
+
+
+
+print_biterrs:
+		ld	a,'7'
+		ld	b,8
+	.showbit:
+		rlc	e
+		jr	nc,.zero
+		ld	(ix+0),a
+		jr	.cont
+	.zero:
+		ld	(ix+0),'.'
+	.cont:
+		inc	ix
+		dec	a
+		djnz	.showbit
+
+		ret
+
+spt_ld_bc:	pop 	bc
+		ret
+
+spt_ld_line1_pos:
+		ld	ix,(pos_line1_text)
+		ret
+spt_ld_line2_pos:
+		ld	ix,(pos_line2_text)
+		ret
+spt_ld_line3_pos:
+		ld	ix,(pos_line3_text)
+		ret
+spt_print_charset:
+		ld	a,ixh
+		ld	h,a
+		ld	a,ixl
+		ld	l,a
+		xor a
+		ld	ix,(pos_char_text)
+		SPTHREAD_ENTER
+
+		;MAC_SPT_CON_GOTO 9,24
+
+		dw spt_con_print, msg_charset		; show a copy of the character set
+		dw spt_ld_line1_pos
+		dw spt_ld_bc, $e0
+		dw do_charset_ix
+		dw spt_exit
+
+spt_chartest:
+		ld	ix,VBASE
+		ld	bc,VSIZE
+		
+do_charset_ix:
+	ld	a,32
+	.charloop:
+
+		ld	(ix+0),a	; copy A to byte pointed by HL
+		inc	a		; increments A
+		inc	ix
+		cp 048h
+		jp nz,.cont2
+		ld	ix,(pos_line2_text)	
+	.cont2:
+		cp 070h
+		jp nz,.cont3
+		ld	ix,(pos_line3_text)
+	.cont3:
+		cp 098h
+		jp nz,.cont4
+		ld	ix,(pos_line4_text)
+	.cont4:
+		cp 0c0h
+		jp nz,.cont5
+		ld	ix,(pos_line5_text)
+	.cont5:
+		cp 0e8h
+		jp nz,.cont6
+		ld	ix,(pos_line6_text)
+	.cont6:
+		cpi			; increments HL, decrements BC (and does a CP)
+		jp	pe, .charloop
+		ret
+
+
+label_vram:	dbz " 1K VRAM 7C00-7FFF "
+label_dram16k1:	dbz "16K DRAM C000-FFFF "
+label_dram16k2:	dbz " 8K DRAM 8000-9FFF "
+label_dram16k3:	dbz " 8K DRAM A000-BFFF "
+label_sram2k1:	dbz " 2K SRAM 5000-57FF "
+label_sram2k2:	dbz " 2K VRAM 5800-58FF "
+msg_banner:	dbz "ABC80-TEST ROM -- FRANK / DAVE / ADRIAN"
+msg_charset:	dbz "-CHARACTER SET-"
+; msg_testing:	db " ", " "+$80, "t"+$80, "e"+$80, "s"+$80, "t"+$80, " "+$80, "  ", 0
+msg_testing:	dbz "..TEST.. "
+msg_testok:	dbz "---OK--- "
+msg_biterrs:	dbz "BIT ERRS "
+msg_ok7bit:	dbz "OK! (7-BIT MODEL 1)"
+msg_ok8bit:	dbz "OK! (8-BIT)"
+msg_banktest:	dbz "TESTING BANK SIZE  "
+
+
+; test parameter table. 2-byte entries:
+; 1. size of test in bytes
+; 2. starting address
+; 3. address of string for announcing test
+; 4. address of tones for identifying the test audibly
+tp_size		equ	10
+
+memtest_ld_bc_size .macro
+		ld	c,(iy+0)
+		ld	b,(iy+1)
+.endm
+
+memtest_ld_hl_base .macro
+		ld	l,(iy+2)
+		ld	h,(iy+3)
+.endm
+
+memtest_loadregs .macro
+		memtest_ld_bc_size
+		memtest_ld_hl_base
+.endm
+
+
+tp_vram:	dw	VSIZE, VBASE, label_vram, tones_vram,$7d00
+
+
+tp_16k:		dw	$4000, $C000, label_dram16k1, tones_id1,$7d80
+			dw	$2000, $8000, label_dram16k2, tones_id1,$7e00
+			dw	$2000, $A000, label_dram16k3, tones_id1,$7e80
+			dw	$0800, $5000, label_sram2k1 , tones_id1,$7f00
+			dw	$0800, $5800, label_sram2k2 , tones_id1,$7f80
+			dw	$0000, tp_16k
+pos_char_text: dw $7c5c
+pos_line1_text: dw $7cd0
+pos_line2_text: dw $7d50
+pos_line3_text: dw $7dd0
+pos_line4_text: dw $7e50
+pos_line5_text: dw $7ed0
+pos_line6_text: dw $7f50
+include "inc/spt.asm"
+include "inc/memtestmarch.asm"
+include "inc/abc80con.asm"
+include "inc/trs80music.asm"

abc80diag.hex

@@ -0,0 +1,89 @@
+:10000000F3ED563E00D3ECD3F8310D00C9D9041EF0
+:1000100005AF036103CE03C600BA0331001D0266BB
+:1000200001C8010000B7031F00A0042D03B703415E
+:10003000008E00B304287C490107012900A0044177
+:1000400003D9043405B304787CAF036B03B70368AA
+:1000500000B7036800FFFFFFFFFFFFFFFFFFFFFF89
+:10006000FFFFFFFFFFFFED45B304787C4901CE039E
+:10007000BA038000A0042303CF016601B703860002
+:10008000A004190366012E016800B7036C00D908AB
+:10009000EB2100003908D9319B00C9C304A004D763
+:1000A00002F701B203C1785121007C01000477ED11
+:1000B000A1EAAE0021007C0100047AEDA12005EA4E
+:1000C000BB00B7C937C9D03E40BB280237C9D908E1
+:1000D000EB2100003908D931DB00C9A5004000BE82
+:1000E00003FB00A500BFFFBE03FB00A500AAAABE3C
+:1000F00003FB00A5005555BE03FB00B203D137C971
+:10010000E13EFFBBC0F9C9E13E40BBC0F9C9E13ED9
+:1001100000BBC0F9C9FD6E04FD6605C9FD6E06FD94
+:100120006607C9FD7E09DD67FD7E08DD6FC9E10157
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+:1001400003FD210000FD09F9C9D908EB21000039A0
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+:10016000D504F7FFB203D908EB2100003908D931D3
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+:1001900003214605319801C9DA04C8010020A001F5
+:1001A0001520E5181E31A901C9D9045605C801005A
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+:10020000A103D908EB2100003908D9310F02C9A098
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+:1002E0005420524F4D202D2D204652414E4B202F51
+:1002F0002044415645202F2041445249414E002D73
+:10030000434841524143544552205345542D002EF9
+:100310002E544553542E2E20002D2D2D4F4B2D2D78
+:100320002D2000424954204552525320004F4B216A
+:100330002028372D424954204D4F44454C20312927
+:10034000004F4B212028382D424954290054455351
+:1003500054494E472042414E4B2053495A45202094
+:10036000000004007C5F022205007D004000C07395
+:10037000025C05807D0020008087025C05007E0015
+:100380002000A09B025C05807E00080050AF025C4C
+:1003900005007F00080058C3025C05807F00006BE9
+:1003A000035C7CD07C507DD07D507ED07E507FFD24
+:1003B000E1C9D9F9EBD9C9E1F9C9E1D8F9C9E1D065
+:1003C000F9C9E1D908EB2100003908D9F9C9AF5FB3
+:1003D00057FD6E02FD6603440E012F772F02BE28E3
+:1003E00006FE0028F618041EFF184DFD4E00FD46BF
+:1003F00001FD6E02FD660372230B79B020F9FD4EFC
+:1004000000FD4601FD6E02FD66037EBA2804AAB314
+:100410005F7A2F77230B79B020F0FD4E00FD460167
+:10042000FD6E02FD66037E2FBA2804AAB35F7A72BE
+:10043000230B79B020F01804186118AFFD4E00FDB1
+:100440004601FD6E02FD6603092B7EBA2804AAB39D
+:100450005F7A2F772B0B79B020F0FD4E00FD46011F
+:10046000FD6E02FD6603092B7E2FBA2804AAB35F36
+:100470007A722B0B79B020F0FD4E00FD4601FD6E27
+:1004800002FD6603092B7EBA2804AAB35F7A2B0B00
+:1004900079B020F27AFE001655289F97B3C837C965
+:1004A000E17EB72808DD7700DD232318F4C9DD21BC
+:1004B000007CC9DDE1C9DD7DE6C0C640DD6F3002EC
+:1004C000DD24C921007C0100043620EDA1EAC90425
+:1004D000DD21007CC9C1DD09C9E14E79B7283A2385
+:1004E0007EB728263E0246D3FF180010FCEE0346D6
+:1004F000D3FF180010FCEE0346D3FF180010FCEEEB
+:1005000003CB4F20E10D20DE180B06001800180069
+:1005100010FA0D20F57E2318C13E00D3FFC96040BC
+:10052000000010501090105010901050109010506B
+:1005300060C0000003C003B004A0049004800570F4
+:1005400005604050000040302000000010C0200036
+:100550000000FF30000044C08000000040606000E8
+:10056000000040601000406060000000406010002B
+:0A05700040601000406060000000D1
+:00000001FF

inc/abc80con.asm

@@ -0,0 +1,45 @@
+spt_con_print:	pop hl
+con_print:
+	.loop:
+		ld a,(HL)       ; get message char
+		or a            ; test for null
+		jr z, .done     ; return if done
+		ld (ix+0),A     ; store char
+		inc ix          ; advance screen pointer
+		inc hl          ; advance message pointer
+		jr .loop        ; continue
+
+	.done:
+		ret
+
+con_home:	ld ix,VBASE
+		ret
+
+spt_con_goto:	pop ix
+		ret
+
+con_NL:
+		ld a,ixl		; go to beginning of line
+		and $c0			; then go to the next line
+		add a,$40
+		ld ixl,a		; store the low byte back
+		jr nc,.skip
+		inc ixh			; fix up high byte if there was a carry
+	.skip:
+		ret
+
+con_clear:
+		ld hl,VBASE
+		ld bc,VSIZE
+	.loop:
+		ld (hl),20h
+		cpi
+		jp pe,.loop
+
+		ld ix,VBASE
+		ret
+
+spt_con_index:	pop bc
+con_index:
+		add ix,bc
+		ret

inc/memtestmarch.asm

@@ -0,0 +1,174 @@
+; code: language=asm-collection tabSize=8
+; Requirements:
+; This function must be RELOCATABLE (only relative jumps), and use NO RAM or STACK.
+; These restrictions lead to somewhat long-winded, repetative code.
+
+;; March C- algorithm:
+;;  1: (up w0) write each location bottom to top with test value
+;;  2: (up r0,w1) read each location bottom to top, compare to test value, then write complement
+;;  3: (up r1,w0) read each location bottom to top, compare to complement, then write test value
+;;  4: (dn r0,w1) read each location top to bottom, compare to test value, then write complement
+;;  5: (dn r1,w0) read each location top to bottom, compare to complement, then write test value
+;;  6: (dn r0) read each location top to bottom, compare to test value
+
+; Arguments:
+;	hl = current memory position under test
+;	bc = bytes remaining to test
+;	iy = test data structure
+; returns:
+;	e = all errored bits found in this block/bank/range of memory
+; destroys: a,bc,d,hl
+; preserves: ix
+
+memtestmarch:
+		xor	a
+		ld	e,a			; reset error accumulator
+		ld	d,a			; set the first testing value to 0
+
+	checkabsent:					; quick test for completely missing bank
+		memtest_ld_hl_base
+		ld	b,h
+		ld	c,1
+		cpl				; A := FF
+	.redo	ld	(hl),a			; write FF to base
+		cpl				; A := 0
+		ld	(bc),a			; write 00 to base+1
+		cp	(hl)			; compare to base (should be FF, should not match)
+		jr	z,.allbad		; if they match, all bits are bad, but double-check
+		cp	0			; are we on the first round?
+		jr	z,.redo			; yes, redo with reversed bits
+		jr	mtm1
+	.allbad:
+		ld	e,$FF			; report all bits bad
+		jr	mtm_done_bounce
+
+	mtm1:
+		memtest_loadregs
+	mtm1loop:				; fill initial value upwards
+		ld	(hl),d
+		inc	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,mtm1loop
+	mtm2:					; read value, write complement upwards
+		memtest_loadregs
+	mtm2loop:
+		ld	a,(hl)
+		cp	d			; compare to value
+		jr	z, mtm2cont		; memory changed, report
+		xor	d			; calculate errored bits
+		or	e				
+		ld	e,a			; save error bits to e
+		ld	a,d			; reload a with correct value
+	mtm2cont:
+		cpl				; take the complement
+		ld	(hl),a			; write the complement
+		inc	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,mtm2loop
+		
+	mtm3:					; read complement, write original value upwards
+		memtest_loadregs
+	mtm3loop:
+		ld	a,(hl)
+		cpl
+		cp	d			; compare to the complement
+		jr	z, mtm3cont		; memory changed, report
+		xor	d			; calculate errored bits
+		or	e				
+		ld	e,a			; save error bits to e
+		ld	a,d			; reload a with correct value
+	mtm3cont:
+		ld	(hl),d			; fill with test value
+		inc	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,mtm3loop
+		jr	mtm4
+	
+	mtm_done_bounce:
+		jr	mtm_done
+	mtm1_bounce:
+		jr	mtm1
+
+	mtm4:					; read test value, write complement downwards
+		memtest_loadregs
+		add	hl,bc			; move to end of the test area
+		dec	hl
+	mtm4loop:
+		ld	a,(hl)
+		cp	d			; compare to value
+		jr	z, mtm4cont
+		xor	d			; calculate errored bits
+		or	e				
+		ld	e,a			; save error bits to e
+		ld	a,d			; reload a with correct value
+	mtm4cont:
+		cpl				; take the complement
+		ld	(hl),a			; write complement
+		dec	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,mtm4loop
+
+	mtm5:					; read complement, write value downwards
+		memtest_loadregs
+		add	hl,bc			; move to end of the test area
+		dec	hl
+	mtm5loop:
+		ld	a,(hl)
+		cpl
+		cp	d
+		jr	z, mtm5cont
+		xor	d			; calculate errored bits
+		or	e				
+		ld	e,a			; save error bits to e
+		ld	a,d			; reload a with correct value
+	mtm5cont:
+		ld	(hl),d
+		dec	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,mtm5loop
+	
+	mtm6:					; final check that all are zero
+		memtest_loadregs
+		add	hl,bc			; move to end of the test area
+		dec	hl
+	mtm6loop:
+		ld	a,(hl)
+		cp	d
+		jr	z,mtm6cont
+		xor	d			; calculate errored bits
+		or	e				
+		ld	e,a			; save error bits to e
+		ld	a,d			; reload a with correct value
+	mtm6cont:
+		dec	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,mtm6loop
+
+	mtmredo:
+		ld	a,d	
+		cp	0			; if our test value is 0
+		ld	d,$55
+		jr	z,mtm1_bounce		; then rerun the tests with value $55
+
+	mtm_done:
+		sub	a			; set carry flag if e is nonzero
+		or	e
+	mtm_return:
+		ret	z
+		scf
+		ret
+
+memtestmarch_end equ $
+;-----------------------------------------------------------------------------

inc/memtestsplit.asm

@@ -0,0 +1,144 @@
+; code: language=asm-collection tabSize=8
+; Requirements:
+; This function must be RELOCATABLE (only relative jumps), and use NO RAM or STACK.
+; These restrictions lead to somewhat long-winded, repetative code.
+
+;; March C- algorithm:
+;;  1: (up w0) write each location bottom to top with test value
+;;  2: (up r0,w1) read each location bottom to top, compare to test value, then write complement
+;;  3: (up r1,w0) read each location bottom to top, compare to complement, then write test value
+;;  4: (dn r0,w1) read each location top to bottom, compare to test value, then write complement
+;;  5: (dn r1,w0) read each location top to bottom, compare to complement, then write test value
+;;  6: (dn r0) read each location top to bottom, compare to test value
+
+; Arguments:
+;	hl = current memory position under test
+;	bc = bytes remaining to test
+;	iy = test data structure
+; returns:
+;	e = all errored bits found in this block/bank/range of memory
+; destroys: a,bc,d,hl
+; preserves: ix
+
+
+memtest_init:
+		xor	a
+		ld	e,a			; reset error accumulator
+		ret
+
+memtest_absent:
+		ld	b,h
+		ld	c,1
+		cpl				; A := FF
+	.redo	ld	(hl),a			; write FF to base
+		cpl				; A := 0
+		ld	(bc),a			; write 00 to base+1
+		cp	(hl)			; compare to base (should be FF, should not match)
+		jr	z,.allbad		; if they match, all bits are bad, but double-check
+		cp	0			; are we on the first round?
+		jr	z,.redo			; yes, redo with reversed bits
+		ret				; didn't find missing ram, exit without error
+	.allbad:
+		ld	e,$FF			; report all bits bad
+		ret
+
+memtest_march_w_up:
+	.loop:					; fill upwards
+		ld	(hl),d
+		inc	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,.loop
+		ret
+
+memtest_march_rw_up:
+	.loop:
+		ld	a,(hl)
+		cp	d			; compare to value
+		jr	z, .cont		; memory changed, report
+		xor	d			; calculate errored bits
+		or	e				
+		ld	e,a			; save error bits to e
+		ld	a,d			; reload a with correct value
+	.cont:
+		cpl				; take the complement
+		ld	(hl),a			; write the complement
+		inc	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,.loop
+		ret
+		
+memtest_march_rw_dn:
+		add	hl,bc			; move to end of the test area
+		dec	hl
+	.loop:
+		ld	a,(hl)
+		cp	d			; compare to value
+		jr	z, .cont
+		xor	d			; calculate errored bits
+		or	e				
+		ld	e,a			; save error bits to e
+		ld	a,d			; reload a with correct value
+	.cont:
+		cpl				; take the complement
+		ld	(hl),a			; write complement
+		dec	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,.loop
+		ret
+
+memtest_march_r_dn:
+		add	hl,bc			; move to end of the test area
+		dec	hl
+	.loop:
+		ld	a,(hl)
+		cp	d
+		jr	z,.cont
+		xor	d			; calculate errored bits
+		or	e				
+		ld	e,a			; save error bits to e
+		ld	a,d			; reload a with correct value
+	.cont:
+		dec	hl
+		dec	bc
+		ld	a,c
+		or	b
+		jr	nz,.loop
+		ret
+
+
+	mtmredo:
+		ld	a,d	
+		cp	0			; if our test value is 0
+		ld	d,$55
+		jr	z,mtm1_bounce		; then rerun the tests with value $55
+
+	mtm_done:
+		sub	a			; set carry flag if e is nonzero
+		or	e
+	mtm_return:
+		ret	z
+		scf
+		ret
+
+memtest_march:
+		xor	a
+		ld	e,a			; reset error accumulator
+
+		push	hl			; save the test regs
+		push	bc
+
+		call	memtest_absent
+		
+
+		ld	d,0
+
+	.redo:	
+
+memtest_split_end equ $
+;-----------------------------------------------------------------------------

inc/spt.asm

@@ -0,0 +1,67 @@
+; code: lang=asm-collection tabSize=8
+; spt_ld_bc:	pop 	bc
+; 		ret
+
+; spt_ld_hl:	pop 	hl
+; 		ret
+
+spt_select_test:
+		pop	iy
+		ret
+
+; spt_ld_bchl:	pop 	bc
+; 		pop 	hl
+; 		ret
+
+; spt_clr_e:	ld	e,0		; just clear reg e
+; 		ret
+
+
+spt_exit:	
+		SPTHREAD_RESTORE
+		ret
+
+
+spt_jp:		pop	hl
+		ld	sp,hl
+		ret
+
+spt_jp_nc:	pop	hl
+		ret	c
+		ld	sp,hl
+		ret
+
+spt_jp_c:	pop	hl
+		ret	nc
+		ld	sp,hl
+		ret
+
+; spt_jp_z:	pop	hl
+; 		ret	nz
+; 		ld	sp,hl
+; 		ret
+
+
+
+; ; attempt to create subroutine to replace SPTHREAD_ENTER macro
+; ; the downside of these is that they destroy HL, which is a hard pill to swallow in
+; ; ramless code
+; ; notes:
+; ; if a subroutine immediately JP's here, we know that:
+; ;	(sp-2) contains the address of the routine that called us (because we got there by RET)
+; ;	(sp-2)+3 contains the address we can jp back to in order to continue
+; spt_enter:
+; 		dec	sp
+; 		dec	sp
+; 		pop	hl
+; 		SPTHREAD_ENTER
+; 		jp	(hl)
+
+
+; call an all-threaded subroutine
+;	the parameter (pointed by SP) is where we are jumping
+spt_call:
+		pop	hl
+		SPTHREAD_SAVE
+		ld	sp,hl
+		ret

inc/spt.mac

@@ -0,0 +1,82 @@
+; code: lang=asm-collection tabSize=8
+; macros for placing interrupt vectors in the middle of a block of threaded code
+SPT_SKIP_INTVEC .macro
+		dw spt_jp, .intvec_continue			; continue after the NMI vector
+		PLACE_INTVEC
+		; ld	sp,0
+		reti
+	.intvec_continue:
+.endm
+
+SPT_SKIP_NMIVEC .macro
+		dw spt_jp, .nmivec_continue			; continue after the NMI vector
+		; PLACE_NMIVEC
+		PLACE_VEC $66
+		; ld	sp,0					; on model 1, NMI is connected to reset button
+		retn
+	.nmivec_continue:
+.endm
+
+; Start a threaded-code section by pointing to it with SP and issuing RET
+; immediately following this macro should be the addresses (and optionally,
+; parameters) for the threaded code
+SPTHREAD_BEGIN .macro
+	.local threadstart
+		ld	sp,.`threadstart
+		ret
+	.`threadstart:
+.endm
+
+; At the end of the threaded code section, place an address just beyond
+; the list of addresses, to jump back to conventional code
+SPTHREAD_END .macro
+		dw	$+2
+.endm
+
+; Save the stack pointer into the stack registers.  This is analogous
+; to pushing SP onto the (simulated) stack.  The shadow registers hold
+; two copies of SP, and effectively become a 2-element stack.  This means
+; that there can be up to two threaded code stack frames saved.  The
+; innermost threaded stack frame can call a third-level machine-code
+; subroutine, but that subroutine can't make any further calls or run
+; threaded code itself.
+SPTHREAD_SAVE .macro
+		exx
+		ex	af,af'		; save flags because of the add hl,sp instruction
+		ex	de,hl
+		ld	hl,0		; copy old sp to iy
+		add	hl,sp
+		ex	af,af'
+		exx
+.endm
+
+; The opposite of SPTHREAD_SAVE.  Pops SP off the simulated stack in
+; preparation for returning to the enclosing threaded stack frame.
+SPTHREAD_RESTORE .macro
+		exx
+		ld	sp,hl		; resume from the thread location saved in hl'
+		ex	de,hl
+		exx
+.endm
+
+; The prologue for a subroutine that contains threaded code.
+SPTHREAD_ENTER .macro
+		SPTHREAD_SAVE
+		SPTHREAD_BEGIN
+.endm
+
+; The epilogue for a subroutine that contains threaded code.  To be followed by RET
+SPTHREAD_LEAVE .macro
+		SPTHREAD_END
+		SPTHREAD_RESTORE
+.endm
+
+
+
+MAC_SPT_CON_GOTO .macro row,col
+		dw spt_con_goto, VBASE+(row*VLINE)+col
+.endm
+
+MAC_SPT_CON_OFFSET .macro row,col
+		dw VBASE+(row*VLINE)+col
+.endm

inc/trs80music.asm

@@ -0,0 +1,162 @@
+; playmusic
+; parameters:
+;	hl = list of notes to play
+; destroys: a,bc,hl
+; preserves: de,ix
+
+spt_playmusic:	
+		pop	hl
+		; fall through to playmusic
+
+playmusic:	;music routine
+	.getnote:
+		ld	c,(hl)
+		ld	a,c
+		or	a
+		jr	z,.end			; zero duration: we are done
+
+		inc	hl
+		ld	a,(hl)
+		or	a
+		jr	z,.rest			; zero frequency: rest
+
+
+		ld	a,2
+	.cycle:					; tone cycle.  First low part of square wave
+		ld	b,(hl)
+		out	($FF),a
+	.loophalf:
+		nop12
+		djnz	.loophalf
+		xor	3			; invert the cassette bits
+
+		ld	b,(hl)
+		out	($FF),a
+	.loophalf2:
+		nop12
+		djnz	.loophalf2
+		xor	3			; invert the cassette bits
+
+		ld	b,(hl)
+		out	($FF),a
+	.loophalf3:
+		nop12
+		djnz	.loophalf3
+		xor	3			; invert the cassette bits
+
+		bit	1,a
+		jr	nz,.cycle
+
+		dec	c
+		jr	nz,.cycle
+
+	; 	ld	b,80
+	; .between_inner:				; delay between notes
+	; 	nop12
+	; 	djnz	.between_inner
+
+		jr	.nextnote
+
+	.rest:
+		ld	b,0
+	.restloop:
+		nop12
+		nop12
+		djnz	.restloop
+
+		dec	c
+		jr	nz,.rest
+
+
+	.nextnote:
+		ld	a,(hl)
+		inc	hl
+
+		jr	.getnote
+
+	.end:
+		ld	a,0
+		out	($FF),a
+		ret
+
+tones_welcome:
+		db	$60,$40
+		db	$00,$00 ;end
+
+tones_vram:	db	$10,$50 ;each note is first byte duration
+		db	$10,$90 ;then next byte frequency -- the higher the second byte, the lower the frequency
+		db	$10,$50
+		db	$10,$90
+		db	$10,$50
+		db	$10,$90 
+		db	$10,$50
+		db	$60,$c0
+		; db	$40,$00 ;rest
+		db	$00,$00 ;end
+
+; tones_vram:	db	$30,$60
+; 		db	$10,$90 ;each note is first byte duration
+; 		db	$20,$40 ;then next byte frequency -- the higher the second byte, the lower the frequency
+; 		db	$10,$90
+; 		db	$20,$40
+; 		db	$30,$60
+; 		;	db $30,$50
+; 		;	db $f0,$c0
+; 		db	$60,$00 ;rest
+; 		db	$00,$00 ;end
+
+
+; tones_sad:	db	$30,$50 ;each note is first byte duration
+; 		db	$30,$60 ;then next byte frequency -- the higher the second byte, the lower the frequency
+; 		db	$30,$70
+; 		db	$30,$80
+; 		db	$30,$90
+; 		db	$30,$a0 
+; 		db	$30,$b0
+; 		db	$f0,$c0
+; 		db	$00,$00 ;end
+
+tones_vramgood:	db	$03,$c0 ;each note is first byte duration
+		db	$03,$b0 ;then next byte frequency -- the higher the second byte, the lower the frequency
+		db	$04,$a0 
+		db	$04,$90 
+		db	$04,$80
+		db	$05,$70
+		db	$05,$60
+		db	$40,$50 
+		;	db $40,$00 ;rest
+		db	$00,$00 ;end
+
+
+tones_bitgood:	db	$40,$30
+		db	$20,$00 ;rest
+		db	$00,$00 ;end
+
+tones_bitbad:	db	$10,$C0
+		db	$20,$00 ;rest
+		db	$00,$00 ;end
+
+tones_bytegood:	db	$FF,$30
+		db	$00,$00 ;end
+
+tones_bytebad:	db	$44,$C0
+		db	$80,$00 ;rest
+		db	$00,$00 ;end
+
+tones_id1:	db	$40,$60
+		db	$60,$00 ;rest
+		db	$00,$00 ;end
+
+tones_id2:	db	$40,$60
+		db	$10,$00 ;rest
+		db	$40,$60
+		db	$60,$00 ;rest
+		db	$00,$00 ;end
+
+tones_id3:	db	$40,$60
+		db	$10,$00 ;rest
+		db	$40,$60
+		db	$10,$00 ;rest
+		db	$40,$60
+		db	$60,$00 ;rest
+		db	$00,$00 ;end

inc/z80.mac

@@ -0,0 +1,73 @@
+; code: lang=asm-collection tabSize=8
+
+JP_ERROR defl 0
+JR_PROMOTE defl 0
+
+	.jperror JP_ERROR
+	.jrpromote JR_PROMOTE
+
+dbi .macro string
+	irpc char,<string>
+		db	'`char`'|$80
+	.endm
+.endm
+
+dbz .macro string
+		db "`string`", 0
+.endm
+
+dbiz .macro string
+		dbi "`string`"
+		db 0
+.endm
+
+nop12 .macro
+		jr	$+2
+.endm
+
+
+; interrupt vectors: these need to be located at 38h and 66h, so there is little
+; code space before them.  They should probably be present so that any incoming interrupts
+; won't kill the test routines.  The INT vector is probably unnecessary but the NMI should
+; be present.
+
+; to maximize space, 
+
+PLACE_VEC .macro loc
+		.assert $ <= loc
+		.if $ < loc
+		dc	loc-$,$FF
+		.endif
+		org	loc
+.endm
+
+; PLACE_INTVEC .macro
+; 		.assert $ <= $38
+; 		.if $ < $38
+; 		dc 	$38-$,$FF				; fill empty space
+; 		.endif
+; 		org 	$38					; NMI vector
+; .endm
+
+; PLACE_NMIVEC .macro
+; 		.assert $ <= $66
+; 		.if $ < $66
+; 		dc 	$66-$,$FF				; fill empty space
+; 		.endif
+; 		org 	$66					; NMI vector
+; .endm
+
+SKIP_INTVEC .macro
+		jr	.intvec_continue			; continue after the NMI vector
+		PLACE_INTVEC
+		reti
+	.intvec_continue:
+.endm
+
+SKIP_NMIVEC .macro
+		jr	.nmivec_continue			; continue after the NMI vector
+		; PLACE_NMIVEC
+		PLACE_VEC $66
+		retn
+	.nmivec_continue:
+.endm

make.bat

@@ -0,0 +1,14 @@
+@echo off
+echo Building the TRS-80 Diagnostic ROM...
+echo Deleting intermediate files...
+del *.cim
+del *.bin
+del *.hex
+del *.lst
+del *.bds
+echo Assembling...
+"C:\Program Files (x86)\zmac\zmac" --zmac -m --od . --oo cim,bds,lst,hex trs80m13diag.asm
+ren trs80m13diag.cim trs80m13diag.bin
+"C:\Program Files (x86)\zmac\zmac" --zmac -m --od . --oo cim,bds,lst,hex trs80m2diag.asm
+ren trs80m2diag.cim trs80m2diag.bin
+echo Done!

os.mk

@@ -0,0 +1,37 @@
+# this file attempts to give basic OS independence to the make process.
+# It depends on GNU Make (or compatible)
+
+
+ifeq ($(OS),Windows_NT)
+# buiding on Windows currently untested
+    RM = cmd //C del //Q //F
+    RRM = cmd //C rmdir //Q //S
+	REN = ren
+	ZMAC = "C:\Program Files (x86)\zmac\zmac"
+	SGR_COMMAND = 
+	SGR_OUTPUT =
+	SGR_SIZE =
+	SGR_RESET =
+	STAT = cmd //C rem
+	CECHO =
+else
+    RRM = $(RM) -r
+	REN = mv
+	ZMAC = zmac
+	SGR_COMMAND := `tput sgr0 ; tput setaf 7 ; tput setab 4 ; tput bold`
+	SGR_OUTPUT := `tput sgr0 ; tput setaf 3 ; tput bold`
+	SGR_SIZE := `tput setaf 2; tput bold`
+	SGR_RESET := `tput sgr0`
+	EMU = trs80gp
+	CECHO = echo
+	CECHON = printf "%s"
+
+    UNAME_S := $(shell uname -s)
+    ifeq ($(UNAME_S),Darwin)
+		STAT = stat -f
+	else
+		STAT = stat -c
+    endif
+    ifeq ($(UNAME_S),Linux)
+    endif
+endif

spt.md

@@ -0,0 +1,204 @@
+## Notes on the techniques used in this ROM
+
+_David Giller, KI3V_
+
+Writing any non-trivial program on a Z80 to operate without using RAM is an extremely tight constraint.  A few of the restrictions implied by lack of RAM are:
+- You cannot use the `CALL` or `RET` instructions in any conventional sense
+- You cannot store variables to the stack using `PUSH`, or move data between registers with `PUSH` and `POP`
+- You can only keep track of as much variable information as will fit in the registers
+	- ... and some of those registers, especially `A`, will be consumed by just about any operation or computation at all
+- Moving data between registers is hampered by the fact that some pathways generally use RAM as an intermediate location
+
+I by no means an expert at Z80 assembly language; this project is my first Z80 program.  I did not invent the techniques used in this program, although I have not seen them combined in exactly this form elsewhere.  This was a learning experience for me, and this document aims to help others who are starting from a similar level of experience to mine learn some of the lessons I did.
+
+## Subroutines without a RAM stack
+
+The initial inspiration for the techniques used in this project was taken [from this article by Jens Madsen on the z80.info web site](http://www.z80.info/jmnomem.htm).  Jens describes how a 'stack' of sorts can be assembled by hand into ROM, and the addresses and parameters that form operations made out of machine-language primitives (subroutines that don't call any other subroutines) can be listed in a very space-efficient form and thus composed into larger, more complex programs without using the `CALL` instruction, RAM, or the stack for return addresses.
+
+(For brevity I'll call this _Jens' method_, though I don't believe he claims to have invented it.  If anyone knows who did, I would be very interested to hear the story.)
+
+## Threaded code
+
+These days, the word _threading_ almost always means concurrent multiprocessing.  But traditionally, the term "threaded code" had a different meaning, one more familiar to Forth language programmers.  
+
+Threaded code in this sense is a technique of stringing subroutines together using sequences of codes representing operations; these operations have been likened to user-definable opcodes in an abstract virtual machine.  The extremely simple interpreter that ran this virtual machine is called an _address interpreter_.
+
+In _Direct Threaded Code_, the opcodes are just the address of the machine-language subroutines that implement each operation.  This is like a string of `CALL mysubroutine` operations, without the `CALL` opcode on the front.  Interspersed with the opcodes, as necessary, are any parameters required by the machine-language opcode subroutines.
+
+The technique described above by Jens is basically a form of direct threading code.  However, this method still only allowed for one level of subroutines, and the order needs to be determined at compile time.  More importantly, subroutines can start the CPU on a new 'stack' or stream of instructions, but can't perform a `CALL` to other code that returns where the current code left off.
+
+Threaded code is not generally a technique to avoid using RAM or a stack; quite the contrary, the Forth language makes extensive use of at least _two_ stacks for fundamental operation.  I needed to find a way to extend this mechanism to allow subroutine calls, even if only in a very limited form, without using RAM for variables of for a CPU stack.
+
+## SPT: Stack Pointer Threading
+
+I implemented a very simple address interpreter based on Jens' method.
+
+To start defining a thread of code, I created the `spthread_begin` macro.  All this does is define a ROM-based 'stack' with its "top" beginning immediately after the macro is invoked.  _Z80 stacks grow from high addresses to low ones, so the "top" of the stack is the lowest address._
+
+At the end of a string of threaded code, the `spthread_end` macro wraps it up.
+
+Defining threaded code, then, just looks like this:
+
+```
+	spthread_begin
+	dw proc1
+	dw proc1arg1
+	dw proc2
+	dw proc2arg1
+	dw proc2arg2
+	dw proc3
+	spthread_end
+```
+
+This can be written more succinctly, which conveniently also looks more like a high level language:
+
+```
+	spthread_begin
+	dw proc1, proc1arg1
+	dw proc2, proc2arg1, proc2arg2
+	dw proc3
+	spthread_end
+```
+
+These macros expand to generate code that looks like this:
+
+```
+	ld sp,.threadstart
+	ret
+.threadstart:
+	dw proc1, proc1arg1
+	dw proc2, proc2arg1, proc2arg2
+	dw proc3
+	dw .threadend
+.threadend:
+
+```
+Conbine the above with subroutines such as the following:
+
+```
+proc1:	pop hl
+	; do some processing
+	; ...
+	ret
+
+proc2:	pop hl
+	pop bc
+	; do some useful work
+	; ...
+	ret
+
+proc3:	; do something without arguments
+	; ...
+	; ...
+	ret
+
+```
+
+For lack of a more creative term, I call this "Stack Pointer Threading", or SPT.  This is not an invention of mine, just an implementation of the method Jens described.  The trick is to remember that the `SP` register serves the purpose of the instruction pointer, for the threaded code addresses.
+
+(For attempted clarity, I will use the term "instruction pointer" to refer to threaded code, to distinguish between that and the Z80's `PC` register.)
+
+The "interpreter" consists of just two instructions: `RET` calls the next threaded operation, and `POP` fetches a parameter from the instruction stream.  It's just two Z80 instructions.  There is no need for an interpreter subroutine.
+
+Now we have code that 'calls' subroutines — limited to one level deep, and with only fixed arguments passed on the stack.  Still, they feel almost like regular subroutines, save for the fact that `POP` instructions are not balanced with `PUSH` instructions anywhere else.
+
+The final piece, however, is how to make more than one level of subroutine call.  I came to the solution for this after pondering on the advice by [Jim Westfall](https://github.com/jwestfall69) to remember the `EX` and `EXX` instructions.  These instructions are not really designed for general use; they are really intended to reduce context switching time in interrupt service routines by shortening the time required to save a single set of registers (instead of saving them to the stack).  This ROM does not use interrupts, but the magic idea there is _"instead of saving them to the stack"_.
+
+## Simulating the stack using the Z80 alternate register set
+
+The alternate resister set that is swapped in and out by the `EX AF,AF'` and `EXX` instructions don't include the stack pointer `SP`.  They do, however, include `HL`, which happens to be the only register to and from which the `SP` register can be transferred without using RAM.
+
+The SPT address interpreter can make one level of subroutine calls, but those calls cannot make deeper calls because we need a place to save the `SP` register (just like the Z80 must store a copy of the `PC` register on the stack before jumping to a subroutine using the `CALL` instruction).
+
+Using this knowlege, I created a set of macros to form the function prologue and epilogue for subroutines that want to make deeper threaded subroutine calls.  The sequence for a threaded subroutine call expands to look like this:
+
+```
+ .prologue
+ 	exx			; prologue: push SP, (threaded IP),
+				; onto the emulated stack
+ 	ex	de,hl		; copy hl' to de'
+ 	ld	hl,0		; copy sp to hl'
+ 	add	hl,sp
+ 	exx
+ 	ld sp,.threadstart
+	ret			; begin address interpreter
+.threadstart
+	db	func1, func1arg1
+	db	func2,
+	; ...
+	db	.threadend
+.threadend
+ 	exx			; epilogue: pop the previous SP off the emulated stack
+ 	ld	sp,hl		; resume from the thread location saved in hl'
+ 	ex	de,hl		; copy de' to hl'
+ 	exx
+	ret
+```
+
+This gives a two-level threaded-code stack, which gives up to three levels of subroutine nesting:
+
+- top level program, with a `spthread_begin` and `spthread_end` threaded code section (threaded IP saved in `DE'`)
+	- First subroutine call, using prologue above (IP saved in `HL'`)
+		- Second subroutine call, using prologue above (IP saved in `SP`)
+			- Third subroutine call — can't make further subroutine calls
+
+If necessary, it would be possible to extend this method by one more register by also using `BC'`.  However, this seems excessive.  Operating without RAM is for special situations such as this RAM testing firmware, and it seems likely that such programs can be structured to live with three levels of nesting or less.
+
+It's worth saying this here: this is extremely slow compared to native Z80 `CALL` and `RET`.  This technique is for when you don't have RAM and can't use `CALL`!
+
+There are a handful of refinements such as the ability to jump to a copy of the epliogue (not the prologue), and even returning to the previous threaded 'stack' frame from within a primitive operation, but the useful portions of the method are described here.
+
+I doubt that I am the first to use this method, and I doubt that I have implemented it in the optimal way.  I would be very interested to hear suggestions for improving this technique.  Please submit a "Issue" or start a "Discussion" on the main Github page for this project with any suggestions or thoughts you may have.
+
+## _Virtual Machine_ revisited
+
+If it seems like a stretch to call the threaded code a "virtual machine", consider that the technique described above already permits code like the following, which I think you'll agree starts to look like assembly language for a fictitious virtual processor:
+
+```
+main_program:
+	spthread_begin
+.loop:	dw sendbyte, $FFFF
+	dw readbyte $FF
+	dw jump_nonzero, .loop
+	spthread_end
+	; ... other code here
+	halt
+
+sendbyte:
+	pop	bc
+	out	(c),b
+	ret
+
+readbyte:
+	pop	bc
+	in	b,(c)
+	ret
+
+jump_nonzero:
+	pop	hl
+	sub	a
+	cp	b
+	ret	z
+	ld	sp,hl		; SP now points to .loop and...
+	ret			; this will continue execution at sendbyte
+```
+
+By changing `SP` from a machine-level threaded-code "instruction", your code can move around inside the threaded instruction stream.
+
+## But... why?
+
+Some might be wondering why not simply use the `IX` and `IY` registers to store return addresses.  After all, it is very easy to make a macro to do this:
+
+```
+	ld	iy,$+3		; save the return address
+	jp	musub		; 
+	; ...
+
+mysub:	; do something useful
+	; ...
+	jp	(iy)		; return from whence we came
+```
+
+We have three registers available with similar powers, `IX`, `IY`, and even `HL`.  And this is _much_ faster and simpler than the whole SPT mess.
+
+The reason is simple.  In this diagnostics ROM, where the goal was to operate with no RAM whatsoever, giving up `IX` and `IY` was too high a price to pay when they are needed for global variables.