stm32f7xx_hal_pwr_ex.c 19 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f7xx_hal_pwr_ex.c
  4. * @author MCD Application Team
  5. * @brief Extended PWR HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of PWR extension peripheral:
  8. * + Peripheral Extended features functions
  9. *
  10. ******************************************************************************
  11. * @attention
  12. *
  13. * Copyright (c) 2017 STMicroelectronics.
  14. * All rights reserved.
  15. *
  16. * This software is licensed under terms that can be found in the LICENSE file
  17. * in the root directory of this software component.
  18. * If no LICENSE file comes with this software, it is provided AS-IS.
  19. *
  20. ******************************************************************************
  21. */
  22. /* Includes ------------------------------------------------------------------*/
  23. #include "stm32f7xx_hal.h"
  24. /** @addtogroup STM32F7xx_HAL_Driver
  25. * @{
  26. */
  27. /** @defgroup PWREx PWREx
  28. * @brief PWR HAL module driver
  29. * @{
  30. */
  31. #ifdef HAL_PWR_MODULE_ENABLED
  32. /* Private typedef -----------------------------------------------------------*/
  33. /* Private define ------------------------------------------------------------*/
  34. /** @addtogroup PWREx_Private_Constants
  35. * @{
  36. */
  37. #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
  38. #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
  39. #define PWR_BKPREG_TIMEOUT_VALUE 1000
  40. #define PWR_VOSRDY_TIMEOUT_VALUE 1000
  41. /**
  42. * @}
  43. */
  44. /* Private macro -------------------------------------------------------------*/
  45. /* Private variables ---------------------------------------------------------*/
  46. /* Private function prototypes -----------------------------------------------*/
  47. /* Private functions ---------------------------------------------------------*/
  48. /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
  49. * @{
  50. */
  51. /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
  52. * @brief Peripheral Extended features functions
  53. *
  54. @verbatim
  55. ===============================================================================
  56. ##### Peripheral extended features functions #####
  57. ===============================================================================
  58. *** Main and Backup Regulators configuration ***
  59. ================================================
  60. [..]
  61. (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
  62. the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
  63. retained even in Standby or VBAT mode when the low power backup regulator
  64. is enabled. It can be considered as an internal EEPROM when VBAT is
  65. always present. You can use the HAL_PWREx_EnableBkUpReg() function to
  66. enable the low power backup regulator.
  67. (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
  68. the backup SRAM is powered from VDD which replaces the VBAT power supply to
  69. save battery life.
  70. (+) The backup SRAM is not mass erased by a tamper event. It is read
  71. protected to prevent confidential data, such as cryptographic private
  72. key, from being accessed. The backup SRAM can be erased only through
  73. the Flash interface when a protection level change from level 1 to
  74. level 0 is requested.
  75. -@- Refer to the description of Read protection (RDP) in the Flash
  76. programming manual.
  77. (+) The main internal regulator can be configured to have a tradeoff between
  78. performance and power consumption when the device does not operate at
  79. the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
  80. macro which configure VOS bit in PWR_CR register
  81. Refer to the product datasheets for more details.
  82. *** FLASH Power Down configuration ****
  83. =======================================
  84. [..]
  85. (+) By setting the FPDS bit in the PWR_CR register by using the
  86. HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
  87. down mode when the device enters Stop mode. When the Flash memory
  88. is in power down mode, an additional startup delay is incurred when
  89. waking up from Stop mode.
  90. *** Over-Drive and Under-Drive configuration ****
  91. =================================================
  92. [..]
  93. (+) In Run mode: the main regulator has 2 operating modes available:
  94. (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
  95. voltage scaling (scale 1, scale 2 or scale 3)
  96. (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
  97. higher frequency than the normal mode for a given voltage scaling (scale 1,
  98. scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
  99. disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
  100. the sequence described in Reference manual.
  101. (+) In Stop mode: the main regulator or low power regulator supplies a low power
  102. voltage to the 1.2V domain, thus preserving the content of registers
  103. and internal SRAM. 2 operating modes are available:
  104. (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
  105. available when the main regulator or the low power regulator is used in Scale 3 or
  106. low voltage mode.
  107. (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
  108. available when the main regulator or the low power regulator is in low voltage mode.
  109. @endverbatim
  110. * @{
  111. */
  112. /**
  113. * @brief Enables the Backup Regulator.
  114. * @retval HAL status
  115. */
  116. HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
  117. {
  118. uint32_t tickstart = 0;
  119. /* Enable Backup regulator */
  120. PWR->CSR1 |= PWR_CSR1_BRE;
  121. /* Workaround for the following hardware bug: */
  122. /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
  123. PWR->CSR1 |= PWR_CSR1_EIWUP;
  124. /* Get tick */
  125. tickstart = HAL_GetTick();
  126. /* Wait till Backup regulator ready flag is set */
  127. while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
  128. {
  129. if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
  130. {
  131. return HAL_TIMEOUT;
  132. }
  133. }
  134. return HAL_OK;
  135. }
  136. /**
  137. * @brief Disables the Backup Regulator.
  138. * @retval HAL status
  139. */
  140. HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
  141. {
  142. uint32_t tickstart = 0;
  143. /* Disable Backup regulator */
  144. PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
  145. /* Workaround for the following hardware bug: */
  146. /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
  147. PWR->CSR1 |= PWR_CSR1_EIWUP;
  148. /* Get tick */
  149. tickstart = HAL_GetTick();
  150. /* Wait till Backup regulator ready flag is set */
  151. while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
  152. {
  153. if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
  154. {
  155. return HAL_TIMEOUT;
  156. }
  157. }
  158. return HAL_OK;
  159. }
  160. /**
  161. * @brief Enables the Flash Power Down in Stop mode.
  162. * @retval None
  163. */
  164. void HAL_PWREx_EnableFlashPowerDown(void)
  165. {
  166. /* Enable the Flash Power Down */
  167. PWR->CR1 |= PWR_CR1_FPDS;
  168. }
  169. /**
  170. * @brief Disables the Flash Power Down in Stop mode.
  171. * @retval None
  172. */
  173. void HAL_PWREx_DisableFlashPowerDown(void)
  174. {
  175. /* Disable the Flash Power Down */
  176. PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
  177. }
  178. /**
  179. * @brief Enables Main Regulator low voltage mode.
  180. * @retval None
  181. */
  182. void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
  183. {
  184. /* Enable Main regulator low voltage */
  185. PWR->CR1 |= PWR_CR1_MRUDS;
  186. }
  187. /**
  188. * @brief Disables Main Regulator low voltage mode.
  189. * @retval None
  190. */
  191. void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
  192. {
  193. /* Disable Main regulator low voltage */
  194. PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
  195. }
  196. /**
  197. * @brief Enables Low Power Regulator low voltage mode.
  198. * @retval None
  199. */
  200. void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
  201. {
  202. /* Enable low power regulator */
  203. PWR->CR1 |= PWR_CR1_LPUDS;
  204. }
  205. /**
  206. * @brief Disables Low Power Regulator low voltage mode.
  207. * @retval None
  208. */
  209. void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
  210. {
  211. /* Disable low power regulator */
  212. PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
  213. }
  214. /**
  215. * @brief Activates the Over-Drive mode.
  216. * @note This mode allows the CPU and the core logic to operate at a higher frequency
  217. * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
  218. * @note It is recommended to enter or exit Over-drive mode when the application is not running
  219. * critical tasks and when the system clock source is either HSI or HSE.
  220. * During the Over-drive switch activation, no peripheral clocks should be enabled.
  221. * The peripheral clocks must be enabled once the Over-drive mode is activated.
  222. * @retval HAL status
  223. */
  224. HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
  225. {
  226. uint32_t tickstart = 0;
  227. __HAL_RCC_PWR_CLK_ENABLE();
  228. /* Enable the Over-drive to extend the clock frequency to 216 MHz */
  229. __HAL_PWR_OVERDRIVE_ENABLE();
  230. /* Get tick */
  231. tickstart = HAL_GetTick();
  232. while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
  233. {
  234. if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
  235. {
  236. return HAL_TIMEOUT;
  237. }
  238. }
  239. /* Enable the Over-drive switch */
  240. __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
  241. /* Get tick */
  242. tickstart = HAL_GetTick();
  243. while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
  244. {
  245. if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
  246. {
  247. return HAL_TIMEOUT;
  248. }
  249. }
  250. return HAL_OK;
  251. }
  252. /**
  253. * @brief Deactivates the Over-Drive mode.
  254. * @note This mode allows the CPU and the core logic to operate at a higher frequency
  255. * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
  256. * @note It is recommended to enter or exit Over-drive mode when the application is not running
  257. * critical tasks and when the system clock source is either HSI or HSE.
  258. * During the Over-drive switch activation, no peripheral clocks should be enabled.
  259. * The peripheral clocks must be enabled once the Over-drive mode is activated.
  260. * @retval HAL status
  261. */
  262. HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
  263. {
  264. uint32_t tickstart = 0;
  265. __HAL_RCC_PWR_CLK_ENABLE();
  266. /* Disable the Over-drive switch */
  267. __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
  268. /* Get tick */
  269. tickstart = HAL_GetTick();
  270. while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
  271. {
  272. if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
  273. {
  274. return HAL_TIMEOUT;
  275. }
  276. }
  277. /* Disable the Over-drive */
  278. __HAL_PWR_OVERDRIVE_DISABLE();
  279. /* Get tick */
  280. tickstart = HAL_GetTick();
  281. while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
  282. {
  283. if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
  284. {
  285. return HAL_TIMEOUT;
  286. }
  287. }
  288. return HAL_OK;
  289. }
  290. /**
  291. * @brief Enters in Under-Drive STOP mode.
  292. *
  293. * @note This mode can be selected only when the Under-Drive is already active
  294. *
  295. * @note This mode is enabled only with STOP low power mode.
  296. * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
  297. * mode is only available when the main regulator or the low power regulator
  298. * is in low voltage mode
  299. *
  300. * @note If the Under-drive mode was enabled, it is automatically disabled after
  301. * exiting Stop mode.
  302. * When the voltage regulator operates in Under-drive mode, an additional
  303. * startup delay is induced when waking up from Stop mode.
  304. *
  305. * @note In Stop mode, all I/O pins keep the same state as in Run mode.
  306. *
  307. * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
  308. * the HSI RC oscillator is selected as system clock.
  309. *
  310. * @note When the voltage regulator operates in low power mode, an additional
  311. * startup delay is incurred when waking up from Stop mode.
  312. * By keeping the internal regulator ON during Stop mode, the consumption
  313. * is higher although the startup time is reduced.
  314. *
  315. * @param Regulator specifies the regulator state in STOP mode.
  316. * This parameter can be one of the following values:
  317. * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
  318. * and Flash memory in power-down when the device is in Stop under-drive mode
  319. * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
  320. * and Flash memory in power-down when the device is in Stop under-drive mode
  321. * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
  322. * This parameter can be one of the following values:
  323. * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
  324. * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
  325. * @retval None
  326. */
  327. HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
  328. {
  329. uint32_t tempreg = 0;
  330. uint32_t tickstart = 0;
  331. /* Check the parameters */
  332. assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
  333. assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
  334. /* Enable Power ctrl clock */
  335. __HAL_RCC_PWR_CLK_ENABLE();
  336. /* Enable the Under-drive Mode ---------------------------------------------*/
  337. /* Clear Under-drive flag */
  338. __HAL_PWR_CLEAR_ODRUDR_FLAG();
  339. /* Enable the Under-drive */
  340. __HAL_PWR_UNDERDRIVE_ENABLE();
  341. /* Get tick */
  342. tickstart = HAL_GetTick();
  343. /* Wait for UnderDrive mode is ready */
  344. while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
  345. {
  346. if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
  347. {
  348. return HAL_TIMEOUT;
  349. }
  350. }
  351. /* Select the regulator state in STOP mode ---------------------------------*/
  352. tempreg = PWR->CR1;
  353. /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
  354. tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
  355. /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
  356. tempreg |= Regulator;
  357. /* Store the new value */
  358. PWR->CR1 = tempreg;
  359. /* Set SLEEPDEEP bit of Cortex System Control Register */
  360. SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
  361. /* Select STOP mode entry --------------------------------------------------*/
  362. if(STOPEntry == PWR_SLEEPENTRY_WFI)
  363. {
  364. /* Request Wait For Interrupt */
  365. __WFI();
  366. }
  367. else
  368. {
  369. /* Request Wait For Event */
  370. __WFE();
  371. }
  372. /* Reset SLEEPDEEP bit of Cortex System Control Register */
  373. SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  374. return HAL_OK;
  375. }
  376. /**
  377. * @brief Returns Voltage Scaling Range.
  378. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
  379. * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
  380. */
  381. uint32_t HAL_PWREx_GetVoltageRange(void)
  382. {
  383. return (PWR->CR1 & PWR_CR1_VOS);
  384. }
  385. /**
  386. * @brief Configures the main internal regulator output voltage.
  387. * @param VoltageScaling specifies the regulator output voltage to achieve
  388. * a tradeoff between performance and power consumption.
  389. * This parameter can be one of the following values:
  390. * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
  391. * typical output voltage at 1.4 V,
  392. * system frequency up to 216 MHz.
  393. * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
  394. * typical output voltage at 1.2 V,
  395. * system frequency up to 180 MHz.
  396. * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
  397. * typical output voltage at 1.00 V,
  398. * system frequency up to 151 MHz.
  399. * @note To update the system clock frequency(SYSCLK):
  400. * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
  401. * - Call the HAL_RCC_OscConfig() to configure the PLL.
  402. * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
  403. * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
  404. * @note The scale can be modified only when the HSI or HSE clock source is selected
  405. * as system clock source, otherwise the API returns HAL_ERROR.
  406. * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
  407. * value in the PWR_CR1 register are not taken in account.
  408. * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
  409. * @note The new voltage scale is active only when the PLL is ON.
  410. * @retval HAL Status
  411. */
  412. HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
  413. {
  414. uint32_t tickstart = 0;
  415. assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
  416. /* Enable Power ctrl clock */
  417. __HAL_RCC_PWR_CLK_ENABLE();
  418. /* Check if the PLL is used as system clock or not */
  419. if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
  420. {
  421. /* Disable the main PLL */
  422. __HAL_RCC_PLL_DISABLE();
  423. /* Get Start Tick */
  424. tickstart = HAL_GetTick();
  425. /* Wait till PLL is disabled */
  426. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
  427. {
  428. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  429. {
  430. return HAL_TIMEOUT;
  431. }
  432. }
  433. /* Set Range */
  434. __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
  435. /* Enable the main PLL */
  436. __HAL_RCC_PLL_ENABLE();
  437. /* Get Start Tick */
  438. tickstart = HAL_GetTick();
  439. /* Wait till PLL is ready */
  440. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
  441. {
  442. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  443. {
  444. return HAL_TIMEOUT;
  445. }
  446. }
  447. /* Get Start Tick */
  448. tickstart = HAL_GetTick();
  449. while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
  450. {
  451. if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
  452. {
  453. return HAL_TIMEOUT;
  454. }
  455. }
  456. }
  457. else
  458. {
  459. return HAL_ERROR;
  460. }
  461. return HAL_OK;
  462. }
  463. /**
  464. * @}
  465. */
  466. /**
  467. * @}
  468. */
  469. #endif /* HAL_PWR_MODULE_ENABLED */
  470. /**
  471. * @}
  472. */
  473. /**
  474. * @}
  475. */