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@@ -111,8 +111,6 @@ Text GLabel 9250 2350 1 50 Input ~ 0
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GND
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Text GLabel 9350 2350 1 50 Input ~ 0
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VCC_ONE
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-Text GLabel 9650 2350 1 50 Input ~ 0
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-GND
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Text GLabel 8900 9300 1 50 Input ~ 0
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FPGA_TCK
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Text GLabel 8900 9900 3 50 Input ~ 0
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@@ -2460,4 +2458,6 @@ Wire Bus Line
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13800 2900 13800 5700
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Wire Bus Line
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11650 2950 11650 8200
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+Text GLabel 9650 2350 1 50 Input ~ 0
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+Y0#
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$EndSCHEMATC
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Per Mårtensson