Browse Source

Moved pin for ABC_CLK and FGPA_SDA

Per Mårtensson 3 years ago
parent
commit
043f613d86
2 changed files with 15753 additions and 19993 deletions
  1. 15732 19972
      max80.kicad_pcb
  2. 21 21
      max80.sch

File diff suppressed because it is too large
+ 15732 - 19972
max80.kicad_pcb


+ 21 - 21
max80.sch

@@ -348,7 +348,7 @@ Wire Wire Line
 	1100 10450 1150 10450
 	1100 10450 1150 10450
 Text Label 6450 3950 2    39   ~ 0
 Text Label 6450 3950 2    39   ~ 0
 FPGA_SCL
 FPGA_SCL
-Text Label 6500 2450 2    39   ~ 0
+Text Label 6450 4150 2    39   ~ 0
 FPGA_SDA
 FPGA_SDA
 Text Label 6500 2550 2    39   ~ 0
 Text Label 6500 2550 2    39   ~ 0
 32KHZ
 32KHZ
@@ -981,17 +981,6 @@ F1 "power_fpga.sch" 50
 $EndSheet
 $EndSheet
 $Comp
 $Comp
 L max80:EP4CE15F17C8N U13
 L max80:EP4CE15F17C8N U13
-U 6 1 6054E41F
-P 7350 3200
-F 0 "U13" H 6650 5100 50  0000 L CNN
-F 1 "EP4CE15F17C8N" H 7350 5100 50  0000 L CNN
-F 2 "" H 6000 3550 50  0001 L CNN
-F 3 "" H 6000 3550 50  0001 L CNN
-	6    7350 3200
-	1    0    0    -1  
-$EndComp
-$Comp
-L max80:EP4CE15F17C8N U13
 U 2 1 6055A8B6
 U 2 1 6055A8B6
 P 2450 7200
 P 2450 7200
 F 0 "U13" H 2850 9050 50  0000 L CNN
 F 0 "U13" H 2850 9050 50  0000 L CNN
@@ -1674,8 +1663,6 @@ Wire Wire Line
 	4150 2450 4200 2450
 	4150 2450 4200 2450
 Text GLabel 4150 2450 0    39   Input ~ 0
 Text GLabel 4150 2450 0    39   Input ~ 0
 FPGA_RESIN
 FPGA_RESIN
-Text Label 3550 2350 0    39   ~ 0
-FREEIO1
 Entry Wire Line
 Entry Wire Line
 	3250 2150 3350 2250
 	3250 2150 3350 2250
 Text Label 3550 2250 0    39   ~ 0
 Text Label 3550 2250 0    39   ~ 0
@@ -1714,7 +1701,7 @@ Entry Wire Line
 	3250 3550 3350 3650
 	3250 3550 3350 3650
 Wire Wire Line
 Wire Wire Line
 	4150 3450 4200 3450
 	4150 3450 4200 3450
-Text GLabel 4150 3450 0    39   Input ~ 0
+Text GLabel 4100 2350 0    39   Input ~ 0
 ABC_CLK_3V3
 ABC_CLK_3V3
 Wire Wire Line
 Wire Wire Line
 	4150 3550 4200 3550
 	4150 3550 4200 3550
@@ -2227,8 +2214,6 @@ F 3 "" H 8850 3500 50  0001 L CNN
 $EndComp
 $EndComp
 Text Label 8700 1750 1    50   ~ 0
 Text Label 8700 1750 1    50   ~ 0
 Memorybus
 Memorybus
-Wire Wire Line
-	6500 2450 6550 2450
 Text Label 14150 1800 2    50   ~ 0
 Text Label 14150 1800 2    50   ~ 0
 Memorybus
 Memorybus
 Wire Wire Line
 Wire Wire Line
@@ -2518,11 +2503,8 @@ Wire Wire Line
 	8800 2350 9400 2350
 	8800 2350 9400 2350
 Wire Wire Line
 Wire Wire Line
 	8800 2150 9400 2150
 	8800 2150 9400 2150
-Wire Wire Line
-	3550 2350 4200 2350
 Wire Wire Line
 Wire Wire Line
 	1050 2500 1650 2500
 	1050 2500 1650 2500
-NoConn ~ 6550 4150
 Wire Wire Line
 Wire Wire Line
 	6450 7100 6550 7100
 	6450 7100 6550 7100
 Wire Wire Line
 Wire Wire Line
@@ -2531,10 +2513,28 @@ Text Label 4600 10550 2    39   ~ 0
 FPGA_USB_PU
 FPGA_USB_PU
 Wire Wire Line
 Wire Wire Line
 	4600 10550 4650 10550
 	4600 10550 4650 10550
-Text Label 6450 4050 2    50   ~ 0
+Text Label 6450 4050 2    39   ~ 0
 FPGA_USB_PU
 FPGA_USB_PU
 Wire Wire Line
 Wire Wire Line
 	6450 4050 6550 4050
 	6450 4050 6550 4050
+Text Label 6100 1500 0    39   ~ 0
+FREEIO1
+Wire Wire Line
+	4100 2350 4200 2350
+Wire Wire Line
+	6450 4150 6550 4150
+$Comp
+L max80:EP4CE15F17C8N U13
+U 6 1 6054E41F
+P 7350 3200
+F 0 "U13" H 6650 5100 50  0000 L CNN
+F 1 "EP4CE15F17C8N" H 7350 5100 50  0000 L CNN
+F 2 "" H 6000 3550 50  0001 L CNN
+F 3 "" H 6000 3550 50  0001 L CNN
+	6    7350 3200
+	1    0    0    -1  
+$EndComp
+NoConn ~ 6550 2450
 Wire Bus Line
 Wire Bus Line
 	5700 1850 5700 3650
 	5700 1850 5700 3650
 Wire Bus Line
 Wire Bus Line

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