Added JTAGen to pin 7 on header

adapter_conn.sch

@@ -45,7 +45,6 @@ F 3 "" H 7100 3900 50  0001 C CNN
 $EndComp
 NoConn ~ 6350 3700
 NoConn ~ 6350 3600
-NoConn ~ 5850 3700
 Wire Wire Line
 	5800 3800 5850 3800
 Wire Wire Line
@@ -176,4 +175,8 @@ Wire Wire Line
 	6350 3500 6450 3500
 Wire Wire Line
 	6450 3500 6450 3250
+Text GLabel 5800 3700 0    50   Input ~ 0
+FPGA_JTAGEN
+Wire Wire Line
+	5800 3700 5850 3700
 $EndSCHEMATC

max80.sch

@@ -32,7 +32,7 @@ FPGA_SPI_MOSI
 Text GLabel 5850 5350 0    50   Input ~ 0
 FPGA_SPI_CLK
 Text GLabel 5850 4350 0    50   Input ~ 0
-JTAGEN
+FPGA_JTAGEN
 Text GLabel 5850 5950 0    50   Input ~ 0
 VCC_ONE
 Text GLabel 5850 6250 0    50   Input ~ 0
@@ -114,18 +114,6 @@ VCC_ONE
 Text GLabel 9650 2350 1    50   Input ~ 0
 GND
 $Comp
-L Device:R_Small R1
-U 1 1 57BABB34
-P 8700 9600
-F 0 "R1" H 8600 9650 50  0000 C CNN
-F 1 "1k" H 8600 9550 50  0000 C CNN
-F 2 "Resistor_SMD:R_0402_1005Metric" V 8630 9600 50  0001 C CNN
-F 3 "" H 8700 9600 50  0000 C CNN
-F 4 "C11702" H 8700 9600 50  0001 C CNN "LCSC"
-	1    8700 9600
-	1    0    0    -1  
-$EndComp
-$Comp
 L Device:R_Small R2
 U 1 1 57BABC0A
 P 8900 9600
@@ -137,12 +125,8 @@ F 4 "C11702" H 8900 9600 50  0001 C CNN "LCSC"
 	1    8900 9600
 	1    0    0    -1  
 $EndComp
-Text GLabel 8700 9300 1    50   Input ~ 0
-JTAGEN
 Text GLabel 8900 9300 1    50   Input ~ 0
 FPGA_TCK
-Text GLabel 8700 9900 3    50   Input ~ 0
-GND
 Text GLabel 8900 9900 3    50   Input ~ 0
 GND
 $Comp
@@ -677,12 +661,8 @@ U 6013B380
 F0 "abc80bus" 50
 F1 "abc80bus.sch" 50
 $EndSheet
-Wire Wire Line
-	8700 9900 8700 9700
 Wire Wire Line
 	8900 9900 8900 9700
-Wire Wire Line
-	8700 9500 8700 9300
 Wire Wire Line
 	8900 9500 8900 9300
 $Sheet
@@ -1954,6 +1934,7 @@ F 0 "U6" H 14200 6200 50  0000 C CNN
 F 1 "MT48LC16M16A2P-6A" H 15550 6250 50  0000 C CNN
 F 2 "Package_SO:TSOP-II-54_22.2x10.16mm_P0.8mm" H 14000 5050 50  0001 C CNN
 F 3 "" H 14000 5050 50  0001 C CNN
+F 4 "C41881" H 14750 4900 50  0001 C CNN "LCSC"
 	1    14750 4900
 	1    0    0    -1  
 $EndComp