Browse Source

Switch pin 27 and 29 on FPGA

Per Mårtensson 4 years ago
parent
commit
7e5ffe48c7
2 changed files with 423 additions and 371 deletions
  1. 419 367
      max80.kicad_pcb
  2. 4 4
      max80.sch

File diff suppressed because it is too large
+ 419 - 367
max80.kicad_pcb


+ 4 - 4
max80.sch

@@ -1134,7 +1134,7 @@ Text Label 8850 7650 3    50   ~ 0
 FPGA_SCL
 FPGA_SCL
 Text Label 8950 7650 3    50   ~ 0
 Text Label 8950 7650 3    50   ~ 0
 FPGA_SDA
 FPGA_SDA
-Text Label 5050 5750 2    50   ~ 0
+Text Label 5050 5550 2    50   ~ 0
 32KHZ
 32KHZ
 Text GLabel 10550 5450 2    50   Input ~ 0
 Text GLabel 10550 5450 2    50   Input ~ 0
 GND
 GND
@@ -1356,7 +1356,7 @@ F 3 "" H 5850 2950 60  0000 C CNN
 	1    5850 2950
 	1    5850 2950
 	1    0    0    -1  
 	1    0    0    -1  
 $EndComp
 $EndComp
-Text GLabel 5850 5550 0    50   Input ~ 0
+Text GLabel 5850 5750 0    50   Input ~ 0
 FGPA_SPI_CS_ESP32
 FGPA_SPI_CS_ESP32
 Text Label 4150 10100 2    50   ~ 0
 Text Label 4150 10100 2    50   ~ 0
 32KHZ
 32KHZ
@@ -1705,8 +1705,6 @@ Wire Wire Line
 	5100 4550 5850 4550
 	5100 4550 5850 4550
 Wire Wire Line
 Wire Wire Line
 	5100 4250 5850 4250
 	5100 4250 5850 4250
-Wire Wire Line
-	5050 5750 5850 5750
 Wire Wire Line
 Wire Wire Line
 	5050 5850 5850 5850
 	5050 5850 5850 5850
 Wire Wire Line
 Wire Wire Line
@@ -2448,6 +2446,8 @@ Text GLabel 6950 7050 3    50   Input ~ 0
 GND
 GND
 Wire Wire Line
 Wire Wire Line
 	10550 4950 10600 4950
 	10550 4950 10600 4950
+Wire Wire Line
+	5050 5550 5850 5550
 Wire Bus Line
 Wire Bus Line
 	4900 6200 4900 8200
 	4900 6200 4900 8200
 Wire Bus Line
 Wire Bus Line

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