Added RTS,CTS,DTR for FPGA

max80.sch

@@ -150,7 +150,7 @@ L Oscillator:ASE-xxxMHz OSC1
 U 1 1 57BABF34
 P 14900 7350
 F 0 "OSC1" H 14700 7600 50  0000 C CNN
-F 1 "EPSON Q33310" H 15250 7600 50  0000 C CNN
+F 1 "EPSON Q33310 48 MHz" H 15250 7600 50  0000 C CNN
 F 2 "max80:Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm" V 14830 7350 50  0001 C CNN
 F 3 "" H 14900 7350 50  0000 C CNN
 F 4 "C32533" V 14900 7350 50  0001 C CNN "LCSC"
@@ -692,12 +692,15 @@ F0 "POWER" 50
 F1 "power.sch" 50
 $EndSheet
 $Sheet
-S 2400 10050 500  400 
+S 2400 10050 550  650 
 U 601569F0
 F0 "USB" 50
 F1 "usb.sch" 50
 F2 "TX0" I L 2400 10200 50 
 F3 "RX0" I L 2400 10300 50 
+F4 "CTS" I L 2400 10400 50 
+F5 "RTS" I L 2400 10500 50 
+F6 "DTR" I L 2400 10600 50 
 $EndSheet
 Text GLabel 5400 1100 3    50   Input ~ 0
 VCC_ONE
@@ -1395,8 +1398,6 @@ Text GLabel 5850 5450 0    50   Input ~ 0
 CLK0n
 Text Label 2400 10200 2    50   ~ 0
 FPGA_USB_TXD
-Text Label 2400 10300 2    50   ~ 0
-FPGA_USB_RXD
 Text Label 8250 8100 1    50   ~ 0
 FPGA_USB_TXD
 Text Label 5050 6050 2    50   ~ 0
@@ -1744,8 +1745,6 @@ Wire Wire Line
 	5050 5750 5850 5750
 Wire Wire Line
 	5050 5850 5850 5850
-NoConn ~ 6850 2350
-NoConn ~ 7250 2350
 Wire Wire Line
 	8450 1450 8450 2350
 Wire Wire Line
@@ -1872,17 +1871,14 @@ Wire Wire Line
 	10550 6250 11550 6250
 Wire Wire Line
 	10550 6350 11550 6350
-NoConn ~ 7050 2350
 Text GLabel 5850 3650 0    50   Input ~ 0
 FPGA_GPIO4
 Text GLabel 5850 3550 0    50   Input ~ 0
 FPGA_GPIO5
 Text GLabel 5850 3450 0    50   Input ~ 0
 INT_ESP32
-Text Label 6750 2100 1    50   ~ 0
+Text Label 6750 1950 1    50   ~ 0
 RTC_INT
-Wire Wire Line
-	6750 2100 6750 2350
 Wire Wire Line
 	5100 1050 5100 1200
 Wire Wire Line
@@ -2264,6 +2260,20 @@ Entry Wire Line
 	4900 6250 5000 6150
 Wire Wire Line
 	5000 6150 5850 6150
+Text Label 7250 1950 1    50   ~ 0
+FPGA_USB_RTS
+Text Label 7050 1950 1    50   ~ 0
+FPGA_USB_CTS
+Wire Wire Line
+	6750 1950 6750 2350
+Wire Wire Line
+	6850 1950 6850 2350
+Wire Wire Line
+	7050 1950 7050 2350
+Text Label 6850 1950 1    50   ~ 0
+FPGA_USB_DTR
+Wire Wire Line
+	7250 1950 7250 2350
 Wire Bus Line
 	4900 6200 4900 8200
 Wire Bus Line
@@ -2278,4 +2288,12 @@ Wire Bus Line
 	13800 2900 13800 5700
 Wire Bus Line
 	11650 2950 11650 8200
+Text Label 2400 10300 2    50   ~ 0
+FPGA_USB_RXD
+Text Label 2400 10400 2    50   ~ 0
+FPGA_USB_CTS
+Text Label 2400 10500 2    50   ~ 0
+FPGA_USB_RTS
+Text Label 2400 10600 2    50   ~ 0
+FPGA_USB_DTR
 $EndSCHEMATC

usb.sch

@@ -142,8 +142,6 @@ Wire Wire Line
 Connection ~ 5350 3100
 Wire Wire Line
 	5350 3100 5450 3100
-NoConn ~ 6450 2800
-NoConn ~ 6450 3200
 NoConn ~ 6450 3400
 NoConn ~ 6450 3500
 NoConn ~ 6450 3700
@@ -251,8 +249,6 @@ Wire Wire Line
 	4400 4300 4400 4200
 Wire Wire Line
 	4700 3800 4800 3800
-NoConn ~ 6450 2900
-NoConn ~ 6450 3300
 $Comp
 L Device:R R7
 U 1 1 6114851D
@@ -397,4 +393,17 @@ Wire Wire Line
 	5150 2750 5200 2750
 Wire Wire Line
 	3800 2800 4650 2800
+NoConn ~ 6450 3200
+Text HLabel 6550 2800 2    50   Input ~ 0
+CTS
+Text HLabel 6550 2900 2    50   Input ~ 0
+RTS
+Wire Wire Line
+	6450 2800 6550 2800
+Wire Wire Line
+	6450 2900 6550 2900
+Text HLabel 6550 3300 2    50   Input ~ 0
+DTR
+Wire Wire Line
+	6450 3300 6550 3300
 $EndSCHEMATC