Added Y0# to FPGA

abc80bus.sch

@@ -1346,8 +1346,6 @@ Wire Wire Line
 	4650 2100 4850 2100
 Wire Wire Line
 	4650 2200 4850 2200
-Wire Wire Line
-	4650 2500 4850 2500
 Wire Wire Line
 	4650 2600 4850 2600
 Entry Wire Line
@@ -1509,10 +1507,6 @@ F 4 "C25741" H 4100 2500 50  0001 C CNN "LCSC"
 $EndComp
 Wire Wire Line
 	4100 2400 4100 2300
-Text Label 4450 5200 0    50   ~ 0
-~Y0
-Text Label 4650 2500 0    50   ~ 0
-~Y0
 $Comp
 L Transistor_FET:AO3400A Q1
 U 1 1 6137C379
@@ -1536,8 +1530,6 @@ F 3 "" H 5650 7400 50  0001 C CNN
 	1    5650 7400
 	1    0    0    -1  
 $EndComp
-Text Label 5250 7200 2    50   ~ 0
-~Y0
 Wire Wire Line
 	5250 7200 5350 7200
 $Comp
@@ -1886,6 +1878,18 @@ Wire Wire Line
 	3500 4300 3500 4400
 Wire Wire Line
 	3500 4050 3500 4100
+Text GLabel 4800 2450 0    50   Input ~ 0
+Y0#
+Wire Wire Line
+	4800 2450 4850 2450
+Wire Wire Line
+	4850 2450 4850 2500
+Text GLabel 5250 7200 0    50   Input ~ 0
+Y0#
+Text GLabel 4700 5200 2    50   Input ~ 0
+Y0#
+Wire Wire Line
+	4450 5200 4700 5200
 Wire Wire Line
 	4400 1600 4750 1600
 Wire Wire Line

max80.sch

@@ -2446,6 +2446,8 @@ Text GLabel 1750 8100 0    50   Input ~ 0
 FLASH_CS#
 Wire Wire Line
 	1750 8100 1850 8100
+Wire Wire Line
+	7250 1800 7250 2350
 Wire Bus Line
 	4900 6200 4900 8200
 Wire Bus Line
@@ -2458,6 +2460,6 @@ Wire Bus Line
 	13800 2900 13800 5700
 Wire Bus Line
 	11650 2950 11650 8200
-Wire Wire Line
-	7250 1800 7250 2350
+Text GLabel 11150 4950 2    50   Input ~ 0
+Y0#
 $EndSCHEMATC