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@@ -1693,8 +1693,6 @@ Wire Wire Line
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4550 1300 4700 1300
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Wire Wire Line
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4700 1100 4550 1100
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-Wire Wire Line
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- 11150 4050 11150 4950
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Text Label 4150 10300 2 50 ~ 0
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FPGA_SCL
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Text Label 4150 10200 2 50 ~ 0
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@@ -1801,8 +1799,6 @@ Wire Wire Line
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10550 3850 11550 3850
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Wire Wire Line
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10550 3950 11550 3950
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-Wire Wire Line
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- 10550 4050 11150 4050
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Wire Wire Line
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10550 4150 11550 4150
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Wire Wire Line
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@@ -2444,17 +2440,8 @@ Wire Wire Line
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2850 8000 2950 8000
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Wire Wire Line
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7250 1550 7250 1600
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-Wire Wire Line
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- 7250 1800 7250 1900
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-Text GLabel 7150 1600 1 50 Input ~ 0
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+Text GLabel 10550 4050 2 50 Input ~ 0
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FLASH_CS#
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-Wire Wire Line
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- 7150 1600 7150 1900
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-Wire Wire Line
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- 7150 1900 7250 1900
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-Connection ~ 7250 1900
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-Wire Wire Line
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- 7250 1900 7250 2350
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Text GLabel 1750 8100 0 50 Input ~ 0
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FLASH_CS#
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Wire Wire Line
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@@ -2471,4 +2458,6 @@ Wire Bus Line
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13800 2900 13800 5700
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Wire Bus Line
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11650 2950 11650 8200
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+Wire Wire Line
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+ 7250 1800 7250 2350
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$EndSCHEMATC
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Per Mårtensson