max80/adapter_conn.sch

EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 7 9
Title "MAX80"
Date "2021-02-22"
Rev "0.01"
Comp "Peter o Per"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_02x20_Odd_Even J4
U 1 1 60B95FED
P 6050 4300
F 0 "J4" H 6050 5350 50  0000 R CNN
F 1 "Conn_02x20_Odd_Even" H 7350 5300 50  0000 R CNN
F 2 "Connector_IDC:IDC-Header_2x20_P2.54mm_Horizontal" H 6050 4300 50  0001 C CNN
F 3 "~" H 6050 4300 50  0001 C CNN
	1    6050 4300
	1    0    0    -1  
$EndComp
Text GLabel 5800 3400 0    50   Input ~ 0
FPGA_TCK
Text GLabel 5800 3500 0    50   Input ~ 0
FPGA_TDO
Text GLabel 5800 3600 0    50   Input ~ 0
FPGA_TMS
Text GLabel 5800 3800 0    50   Input ~ 0
FPGA_TDI
$Comp
L power:GND #PWR0129
U 1 1 60BAB928
P 7100 3900
F 0 "#PWR0129" H 7100 3650 50  0001 C CNN
F 1 "GND" H 7105 3727 50  0000 C CNN
F 2 "" H 7100 3900 50  0001 C CNN
F 3 "" H 7100 3900 50  0001 C CNN
	1    7100 3900
	1    0    0    -1  
$EndComp
NoConn ~ 6350 3700
NoConn ~ 6350 3600
Wire Wire Line
	5800 3800 5850 3800
Wire Wire Line
	5800 3600 5850 3600
Wire Wire Line
	5800 3500 5850 3500
Wire Wire Line
	5800 3400 5850 3400
$Comp
L power:+3V3 #PWR0130
U 1 1 60BBF195
P 6450 3250
F 0 "#PWR0130" H 6450 3100 50  0001 C CNN
F 1 "+3V3" H 6465 3423 50  0000 C CNN
F 2 "" H 6450 3250 50  0001 C CNN
F 3 "" H 6450 3250 50  0001 C CNN
	1    6450 3250
	1    0    0    -1  
$EndComp
Text GLabel 6350 4900 2    50   Input ~ 0
ESP32_TMS
$Comp
L power:+3V3 #PWR0146
U 1 1 61136360
P 5200 4850
F 0 "#PWR0146" H 5200 4700 50  0001 C CNN
F 1 "+3V3" H 5215 5023 50  0000 C CNN
F 2 "" H 5200 4850 50  0001 C CNN
F 3 "" H 5200 4850 50  0001 C CNN
	1    5200 4850
	1    0    0    -1  
$EndComp
$Comp
L power:GND #PWR0147
U 1 1 61136E2E
P 5750 5400
F 0 "#PWR0147" H 5750 5150 50  0001 C CNN
F 1 "GND" H 5755 5227 50  0000 C CNN
F 2 "" H 5750 5400 50  0001 C CNN
F 3 "" H 5750 5400 50  0001 C CNN
	1    5750 5400
	1    0    0    -1  
$EndComp
Wire Wire Line
	5850 5000 5750 5000
Wire Wire Line
	5750 5000 5750 5100
Wire Wire Line
	5750 5100 5850 5100
Connection ~ 5750 5100
Wire Wire Line
	5750 5100 5750 5200
Wire Wire Line
	5750 5200 5850 5200
Connection ~ 5750 5200
Wire Wire Line
	5750 5200 5750 5300
Wire Wire Line
	5750 5300 5850 5300
Connection ~ 5750 5300
Wire Wire Line
	5750 5300 5750 5400
Text GLabel 6350 5000 2    50   Input ~ 0
ESP32_TCK
Text GLabel 6350 5100 2    50   Input ~ 0
ESP32_TDO
Text GLabel 6350 5200 2    50   Input ~ 0
ESP32_TDI
NoConn ~ 6350 5300
Text GLabel 6350 4700 2    50   Input ~ 0
ESP32_EN
Wire Wire Line
	5200 4850 5200 4900
Wire Wire Line
	5200 4900 5850 4900
Text GLabel 6350 4800 2    50   Input ~ 0
ESP32_IO0
Text GLabel 5850 4700 0    50   Input ~ 0
ESP32_TXD
Text HLabel 6400 3900 2    50   Input ~ 0
FPGA_SDA
Wire Wire Line
	5800 3900 5850 3900
Text HLabel 5800 3900 0    50   Input ~ 0
FPGA_SCL
Wire Wire Line
	6350 3900 6400 3900
Text GLabel 6350 4400 2    50   Input ~ 0
ESP32_MOSI
Text GLabel 6350 4600 2    50   Input ~ 0
ESP32_MISO
Text GLabel 6350 4500 2    50   Input ~ 0
ESP32_SCK
Text GLabel 5850 4600 0    50   Input ~ 0
ESP32_CS0
Text GLabel 5850 4500 0    50   Input ~ 0
ESP32_CS1
Text GLabel 5850 4300 0    50   Input ~ 0
ESP32_CS2
Text GLabel 5850 4400 0    50   Input ~ 0
ESP32_SCL
Text GLabel 6350 4300 2    50   Input ~ 0
ESP32_SDA
Text GLabel 5850 4000 0    50   Input ~ 0
FPGA_GPIO0
Text GLabel 6350 4000 2    50   Input ~ 0
FPGA_GPIO1
Text GLabel 5850 4100 0    50   Input ~ 0
FPGA_GPIO2
Text GLabel 6350 4100 2    50   Input ~ 0
FPGA_GPIO3
Text GLabel 5850 4200 0    50   Input ~ 0
FPGA_GPIO4
Text GLabel 6350 4200 2    50   Input ~ 0
FPGA_GPIO5
Text GLabel 5850 4800 0    50   Input ~ 0
ESP32_RXD
Wire Wire Line
	7100 3800 7100 3900
Wire Wire Line
	6350 3800 7100 3800
Wire Wire Line
	7100 3400 7100 3800
Wire Wire Line
	6350 3400 7100 3400
Connection ~ 7100 3800
Wire Wire Line
	6350 3500 6450 3500
Wire Wire Line
	6450 3500 6450 3250
Text GLabel 5800 3700 0    50   Input ~ 0
FPGA_JTAGEN
Wire Wire Line
	5800 3700 5850 3700
$EndSCHEMATC