/*
 * Move test image to SRAM and jump to it
 */
#include "sys.h"

	.section ".dram.text","ax"
	.globl __start_test
__start_test:
	la	a0,__dram_test_start
	li	a1,SRAM_SIZE
	li	a2,0
	li	a3,32

	.balign 4
.L_loop:
	lw	a5,0(a0)
	sw	a5,0(a2)
	lw	a5,4(a0)
	sw	a5,4(a2)
	lw	a5,8(a0)
	sw	a5,8(a2)
	lw	a5,12(a0)
	sw	a5,12(a2)
	lw	a5,16(a0)
	sw	a5,16(a2)
	lw	a5,20(a0)
	sw	a5,20(a2)
	lw	a5,24(a0)
	sw	a5,24(a2)
	lw	a5,28(a0)
	sw	a5,28(a2)
	add	a0,a0,a3
	add	a2,a2,a3
	bltu	a2,a1,.L_loop

	/* For future compatibility... */
	li	sp,SRAM_SIZE
	li	tp,0
	li	a0,0
	li	a1,0
	li	a2,0
	li	a3,0
	li	a4,0
	li	a5,0

	li	ra,_PC_RESET
	jr	ra
