//altremote_update CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" check_app_pof="true" config_device_addr_width=24 DEVICE_FAMILY="Cyclone IV E" in_data_width=24 is_epcq="true" operation_mode="remote" out_data_width=29 asmi_addr asmi_busy asmi_data_valid asmi_dataout asmi_rden asmi_read busy clock ctl_nupdt data_in data_out param pof_error read_param read_source reconfig reset reset_timer write_param
//VERSION_BEGIN 21.1 cbx_altremote_update 2021:10:21:11:02:24:SJ cbx_cycloneii 2021:10:21:11:02:24:SJ cbx_lpm_add_sub 2021:10:21:11:02:24:SJ cbx_lpm_compare 2021:10:21:11:02:24:SJ cbx_lpm_counter 2021:10:21:11:02:24:SJ cbx_lpm_decode 2021:10:21:11:02:24:SJ cbx_lpm_shiftreg 2021:10:21:11:02:24:SJ cbx_mgl 2021:10:21:11:11:47:SJ cbx_nadder 2021:10:21:11:02:24:SJ cbx_nightfury 2021:10:21:11:02:24:SJ cbx_stratix 2021:10:21:11:02:24:SJ cbx_stratixii 2021:10:21:11:02:24:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



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//  and other software and tools, and any partner logic 
//  functions, and any output files from any of the foregoing 
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//  the Intel FPGA IP License Agreement, or other applicable license
//  agreement, including, without limitation, that your use is for
//  the sole purpose of programming logic devices manufactured by
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//  refer to the applicable agreement for further details, at
//  https://fpgasoftware.intel.com/eula.



//synthesis_resources = cycloneive_rublock 1 lpm_add_sub 1 lpm_counter 8 lpm_shiftreg 1 reg 167 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104;suppress_da_rule_internal=C101;suppress_da_rule_internal=C103"} *)
module  altera_remote_update_core
	( 
	asmi_addr,
	asmi_busy,
	asmi_data_valid,
	asmi_dataout,
	asmi_rden,
	asmi_read,
	busy,
	clock,
	ctl_nupdt,
	data_in,
	data_out,
	param,
	pof_error,
	read_param,
	read_source,
	reconfig,
	reset,
	reset_timer,
	write_param) /* synthesis synthesis_clearbox=1 */;
	output   [23:0]  asmi_addr;
	input   asmi_busy;
	input   asmi_data_valid;
	input   [7:0]  asmi_dataout;
	output   asmi_rden;
	output   asmi_read;
	output   busy;
	input   clock;
	input   ctl_nupdt;
	input   [23:0]  data_in;
	output   [28:0]  data_out;
	input   [2:0]  param;
	output   pof_error;
	input   read_param;
	input   [1:0]  read_source;
	input   reconfig;
	input   reset;
	input   reset_timer;
	input   write_param;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri0   asmi_busy;
	tri0   asmi_data_valid;
	tri0   [7:0]  asmi_dataout;
	tri0   ctl_nupdt;
	tri0   [23:0]  data_in;
	tri0   [2:0]  param;
	tri0   read_param;
	tri0   [1:0]  read_source;
	tri0   reconfig;
	tri0   reset_timer;
	tri0   write_param;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

	reg	[7:0]	asim_data_reg;
	wire	[23:0]	wire_asmi_addr_st_d;
	reg	[23:0]	asmi_addr_st;
	wire	[23:0]	wire_asmi_addr_st_ena;
	reg	[0:0]	asmi_read_reg;
	reg	[0:0]	cal_addr_reg;
	reg	[0:0]	check_busy_dffe;
	reg	[0:0]	crc_cal_reg;
	reg	[0:0]	crc_check_end_reg;
	reg	[0:0]	crc_chk_st_dffe;
	reg	[0:0]	crc_done_reg;
	wire	wire_crc_done_reg_ena;
	reg	[7:0]	crc_high;
	reg	[7:0]	crc_low;
	reg	[15:0]	crc_reg;
	wire	[23:0]	wire_dataa_switch_d;
	reg	[23:0]	dataa_switch;
	wire	[23:0]	wire_dataa_switch_ena;
	reg	[6:0]	dffe10a;
	wire	[6:0]	wire_dffe10a_ena;
	reg	[0:0]	dffe1a0;
	reg	[0:0]	dffe1a1;
	wire	[1:0]	wire_dffe1a_ena;
	reg	[0:0]	dffe2a0;
	reg	[0:0]	dffe2a1;
	reg	[0:0]	dffe2a2;
	wire	[2:0]	wire_dffe2a_ena;
	reg	[0:0]	dffe3a0;
	reg	[0:0]	dffe3a1;
	reg	[0:0]	dffe3a2;
	wire	[2:0]	wire_dffe3a_ena;
	reg	[28:0]	dffe7a;
	wire	[28:0]	wire_dffe7a_ena;
	reg	dffe9;
	reg	[0:0]	get_addr_reg;
	reg	idle_state;
	reg	idle_write_wait;
	reg	[0:0]	load_crc_high_reg;
	reg	[0:0]	load_crc_low_reg;
	reg	[0:0]	load_data_reg;
	reg	[0:0]	pof_counter_l42;
	reg	[0:0]	pof_error_reg;
	wire	wire_pof_error_reg_ena;
	reg	re_config_reg;
	reg	read_address_state;
	wire	wire_read_address_state_ena;
	reg	[0:0]	read_control_reg_dffe;
	reg	read_data_state;
	reg	read_init_counter_state;
	reg	read_init_state;
	reg	read_post_state;
	reg	read_pre_data_state;
	reg	read_source_update_state;
	reg	[0:0]	reconfig_width_reg;
	reg	[0:0]	ru_reconfig_pof_reg;
	reg	write_data_state;
	reg	write_init_counter_state;
	reg	write_init_state;
	reg	write_load_state;
	reg	write_post_data_state;
	reg	write_pre_data_state;
	reg	write_source_update_state;
	reg	write_wait_state;
	wire  [23:0]   wire_add_sub16_result;
	wire  [2:0]   wire_cntr11_q;
	wire  [2:0]   wire_cntr12_q;
	wire  [2:0]   wire_cntr13_q;
	wire  wire_cntr14_cout;
	wire  [5:0]   wire_cntr14_q;
	wire  wire_cntr15_cout;
	wire  [2:0]   wire_cntr15_q;
	wire  [5:0]   wire_cntr5_q;
	wire  [4:0]   wire_cntr6_q;
	wire  [2:0]   wire_cntr8_q;
	wire  wire_shift_reg17_shiftout;
	wire  wire_sd4_regout;
	wire  asmi_read_out;
	wire  asmi_read_wire;
	wire  bit_counter_all_done;
	wire  bit_counter_clear;
	wire  bit_counter_enable;
	wire  [5:0]  bit_counter_param_start;
	wire  bit_counter_param_start_match;
	wire  cal_addr;
	wire  chk_crc_counter_enable;
	wire  chk_pof_counter_enable;
	wire  chk_pof_counter_start;
	wire  [6:0]  combine_port;
	wire  [15:0]  crc;
	wire  crc_cal;
	wire  crc_check_end;
	wire  crc_check_st;
	wire  crc_check_st_wire;
	wire  crc_enable_wire;
	wire  [15:0]  crc_reg_wire;
	wire  crc_shift_done;
	wire  get_addr;
	wire  global_gnd;
	wire  global_vcc;
	wire  halt_cal;
	wire  idle;
	wire  invert_bits;
	wire  load_crc_high;
	wire  load_crc_low;
	wire  load_data;
	wire  [2:0]  param_c3;
	wire  [6:0]  param_decoder_param_latch;
	wire  [22:0]  param_decoder_select;
	wire  pof_counter_40;
	wire  pof_error_wire;
	wire  power_up;
	wire  read_address;
	wire  read_control_reg;
	wire  read_data;
	wire  read_init;
	wire  read_init_counter;
	wire  read_param_c3;
	wire  read_post;
	wire  read_pre_data;
	wire  [1:0]  read_source_c3;
	wire  read_source_update;
	wire  reconfig_c3;
	wire  rsource_load;
	wire  [1:0]  rsource_parallel_in;
	wire  rsource_serial_out;
	wire  rsource_shift_enable;
	wire  [2:0]  rsource_state_par_ini;
	wire  rsource_update_done;
	wire  ru_reconfig_pof;
	wire  rublock_captnupdt;
	wire  rublock_clock;
	wire  rublock_reconfig;
	wire  rublock_regin;
	wire  rublock_regout;
	wire  rublock_regout_reg;
	wire  rublock_shiftnld;
	wire  select_shift_nloop;
	wire  shift_reg_clear;
	wire  shift_reg_load_enable;
	wire  [28:0]  shift_reg_q;
	wire  shift_reg_serial_in;
	wire  shift_reg_serial_out;
	wire  shift_reg_shift_enable;
	wire  st_counter_enable;
	wire  st_v0;
	wire  st_v1;
	wire  st_v2;
	wire  st_v3;
	wire  st_v4;
	wire  st_v5;
	wire  st_v6;
	wire  st_v7;
	wire  [5:0]  start_bit_decoder_out;
	wire  [22:0]  start_bit_decoder_param_select;
	wire  [1:0]  w4w;
	wire  [5:0]  w53w;
	wire  [4:0]  w83w;
	wire  width_counter_all_done;
	wire  width_counter_clear;
	wire  width_counter_enable;
	wire  [4:0]  width_counter_param_width;
	wire  width_counter_param_width_match;
	wire  [4:0]  width_decoder_out;
	wire  [22:0]  width_decoder_param_select;
	wire  write_data;
	wire  write_init;
	wire  write_init_counter;
	wire  write_load;
	wire  write_param_c3;
	wire  write_post_data;
	wire  write_pre_data;
	wire  write_source_update;
	wire  write_wait;
	wire  [2:0]  wsource_state_par_ini;
	wire  wsource_update_done;

	// synopsys translate_off
	initial
		asim_data_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asim_data_reg <= 8'b0;
		else if  (asmi_data_valid == 1'b1)   asim_data_reg <= {asmi_dataout[0], asmi_dataout[1], asmi_dataout[2], asmi_dataout[3], asmi_dataout[4], asmi_dataout[5], asmi_dataout[6], asmi_dataout[7]};
	// synopsys translate_off
	initial
		asmi_addr_st[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[0:0] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[0:0] == 1'b1)   asmi_addr_st[0:0] <= wire_asmi_addr_st_d[0:0];
	// synopsys translate_off
	initial
		asmi_addr_st[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[1:1] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[1:1] == 1'b1)   asmi_addr_st[1:1] <= wire_asmi_addr_st_d[1:1];
	// synopsys translate_off
	initial
		asmi_addr_st[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[2:2] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[2:2] == 1'b1)   asmi_addr_st[2:2] <= wire_asmi_addr_st_d[2:2];
	// synopsys translate_off
	initial
		asmi_addr_st[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[3:3] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[3:3] == 1'b1)   asmi_addr_st[3:3] <= wire_asmi_addr_st_d[3:3];
	// synopsys translate_off
	initial
		asmi_addr_st[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[4:4] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[4:4] == 1'b1)   asmi_addr_st[4:4] <= wire_asmi_addr_st_d[4:4];
	// synopsys translate_off
	initial
		asmi_addr_st[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[5:5] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[5:5] == 1'b1)   asmi_addr_st[5:5] <= wire_asmi_addr_st_d[5:5];
	// synopsys translate_off
	initial
		asmi_addr_st[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[6:6] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[6:6] == 1'b1)   asmi_addr_st[6:6] <= wire_asmi_addr_st_d[6:6];
	// synopsys translate_off
	initial
		asmi_addr_st[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[7:7] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[7:7] == 1'b1)   asmi_addr_st[7:7] <= wire_asmi_addr_st_d[7:7];
	// synopsys translate_off
	initial
		asmi_addr_st[8:8] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[8:8] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[8:8] == 1'b1)   asmi_addr_st[8:8] <= wire_asmi_addr_st_d[8:8];
	// synopsys translate_off
	initial
		asmi_addr_st[9:9] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[9:9] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[9:9] == 1'b1)   asmi_addr_st[9:9] <= wire_asmi_addr_st_d[9:9];
	// synopsys translate_off
	initial
		asmi_addr_st[10:10] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[10:10] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[10:10] == 1'b1)   asmi_addr_st[10:10] <= wire_asmi_addr_st_d[10:10];
	// synopsys translate_off
	initial
		asmi_addr_st[11:11] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[11:11] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[11:11] == 1'b1)   asmi_addr_st[11:11] <= wire_asmi_addr_st_d[11:11];
	// synopsys translate_off
	initial
		asmi_addr_st[12:12] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[12:12] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[12:12] == 1'b1)   asmi_addr_st[12:12] <= wire_asmi_addr_st_d[12:12];
	// synopsys translate_off
	initial
		asmi_addr_st[13:13] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[13:13] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[13:13] == 1'b1)   asmi_addr_st[13:13] <= wire_asmi_addr_st_d[13:13];
	// synopsys translate_off
	initial
		asmi_addr_st[14:14] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[14:14] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[14:14] == 1'b1)   asmi_addr_st[14:14] <= wire_asmi_addr_st_d[14:14];
	// synopsys translate_off
	initial
		asmi_addr_st[15:15] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[15:15] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[15:15] == 1'b1)   asmi_addr_st[15:15] <= wire_asmi_addr_st_d[15:15];
	// synopsys translate_off
	initial
		asmi_addr_st[16:16] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[16:16] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[16:16] == 1'b1)   asmi_addr_st[16:16] <= wire_asmi_addr_st_d[16:16];
	// synopsys translate_off
	initial
		asmi_addr_st[17:17] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[17:17] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[17:17] == 1'b1)   asmi_addr_st[17:17] <= wire_asmi_addr_st_d[17:17];
	// synopsys translate_off
	initial
		asmi_addr_st[18:18] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[18:18] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[18:18] == 1'b1)   asmi_addr_st[18:18] <= wire_asmi_addr_st_d[18:18];
	// synopsys translate_off
	initial
		asmi_addr_st[19:19] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[19:19] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[19:19] == 1'b1)   asmi_addr_st[19:19] <= wire_asmi_addr_st_d[19:19];
	// synopsys translate_off
	initial
		asmi_addr_st[20:20] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[20:20] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[20:20] == 1'b1)   asmi_addr_st[20:20] <= wire_asmi_addr_st_d[20:20];
	// synopsys translate_off
	initial
		asmi_addr_st[21:21] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[21:21] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[21:21] == 1'b1)   asmi_addr_st[21:21] <= wire_asmi_addr_st_d[21:21];
	// synopsys translate_off
	initial
		asmi_addr_st[22:22] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[22:22] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[22:22] == 1'b1)   asmi_addr_st[22:22] <= wire_asmi_addr_st_d[22:22];
	// synopsys translate_off
	initial
		asmi_addr_st[23:23] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_addr_st[23:23] <= 1'b0;
		else if  (wire_asmi_addr_st_ena[23:23] == 1'b1)   asmi_addr_st[23:23] <= wire_asmi_addr_st_d[23:23];
	assign
		wire_asmi_addr_st_d = {((shift_reg_q[21] & get_addr) | (wire_add_sub16_result[23] & asmi_read_wire)), ((shift_reg_q[20] & get_addr) | (wire_add_sub16_result[22] & asmi_read_wire)), ((shift_reg_q[19] & get_addr) | (wire_add_sub16_result[21] & asmi_read_wire)), ((shift_reg_q[18] & get_addr) | (wire_add_sub16_result[20] & asmi_read_wire)), ((shift_reg_q[17] & get_addr) | (wire_add_sub16_result[19] & asmi_read_wire)), ((shift_reg_q[16] & get_addr) | (wire_add_sub16_result[18] & asmi_read_wire)), ((shift_reg_q[15] & get_addr) | (wire_add_sub16_result[17] & asmi_read_wire)), ((shift_reg_q[14] & get_addr) | (wire_add_sub16_result[16] & asmi_read_wire)), ((shift_reg_q[13] & get_addr) | (wire_add_sub16_result[15] & asmi_read_wire)), ((shift_reg_q[12] & get_addr) | (wire_add_sub16_result[14] & asmi_read_wire)), ((shift_reg_q[11] & get_addr) | (wire_add_sub16_result[13] & asmi_read_wire)), ((shift_reg_q[10] & get_addr) | (wire_add_sub16_result[12] & asmi_read_wire)), ((shift_reg_q[9] & get_addr) | (wire_add_sub16_result[11] & asmi_read_wire)), ((shift_reg_q[8] & get_addr) | (wire_add_sub16_result[10] & asmi_read_wire)), ((shift_reg_q[7] & get_addr) | (wire_add_sub16_result[9] & asmi_read_wire)), ((shift_reg_q[6] & get_addr) | (wire_add_sub16_result[8] & asmi_read_wire)), ((shift_reg_q[5] & get_addr) | (wire_add_sub16_result[7] & asmi_read_wire)), ((shift_reg_q[4] & get_addr) | (wire_add_sub16_result[6] & asmi_read_wire)), ((shift_reg_q[3] & get_addr) | (wire_add_sub16_result[5] & asmi_read_wire)), ((shift_reg_q[2] & get_addr) | (wire_add_sub16_result[4] & asmi_read_wire)), ((shift_reg_q[1] & get_addr) | (wire_add_sub16_result[3] & asmi_read_wire)), ((shift_reg_q[0] & get_addr) | (wire_add_sub16_result[2] & asmi_read_wire)), (wire_add_sub16_result[1] & asmi_read_wire), (wire_add_sub16_result[0] & asmi_read_wire)};
	assign
		wire_asmi_addr_st_ena = {24{(get_addr | asmi_read_wire)}};
	// synopsys translate_off
	initial
		asmi_read_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) asmi_read_reg <= 1'b0;
		else if  (check_busy_dffe == 1'b1)   asmi_read_reg <= ((wire_cntr12_q[2] & (~ wire_cntr12_q[1])) & wire_cntr12_q[0]);
	// synopsys translate_off
	initial
		cal_addr_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) cal_addr_reg <= 1'b0;
		else if  (check_busy_dffe == 1'b1)   cal_addr_reg <= (get_addr_reg | ((wire_cntr12_q[2] & (~ wire_cntr12_q[1])) & (~ wire_cntr12_q[0])));
	// synopsys translate_off
	initial
		check_busy_dffe = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) check_busy_dffe <= 1'b0;
		else  check_busy_dffe <= ((wire_cntr11_q[2] | wire_cntr11_q[1]) | wire_cntr11_q[0]);
	// synopsys translate_off
	initial
		crc_cal_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) crc_cal_reg <= 1'b0;
		else  crc_cal_reg <= (((~ wire_cntr12_q[2]) & wire_cntr12_q[1]) & wire_cntr12_q[0]);
	// synopsys translate_off
	initial
		crc_check_end_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) crc_check_end_reg <= 1'b0;
		else  crc_check_end_reg <= (((wire_cntr11_q[2] & wire_cntr11_q[1]) & (~ wire_cntr11_q[0])) & wire_cntr14_cout);
	// synopsys translate_off
	initial
		crc_chk_st_dffe = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) crc_chk_st_dffe <= 1'b0;
		else  crc_chk_st_dffe <= crc_check_st_wire;
	// synopsys translate_off
	initial
		crc_done_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) crc_done_reg <= 1'b0;
		else if  (wire_crc_done_reg_ena == 1'b1) 
			if (chk_pof_counter_start == 1'b1) crc_done_reg <= 1'b0;
			else  crc_done_reg <= pof_counter_40;
	assign
		wire_crc_done_reg_ena = (pof_counter_40 | chk_pof_counter_start);
	// synopsys translate_off
	initial
		crc_high = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) crc_high <= 8'b0;
		else if  (load_crc_high == 1'b1)   crc_high <= asim_data_reg;
	// synopsys translate_off
	initial
		crc_low = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) crc_low <= 8'b0;
		else if  (load_crc_low == 1'b1)   crc_low <= asim_data_reg;
	// synopsys translate_off
	initial
		crc_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) crc_reg <= {16{1'b1}};
		else if  (crc_enable_wire == 1'b1) 
			if (crc_check_st_wire == 1'b1) crc_reg <= {{1{1'b1}}, {15{1'b1}}};
			else  crc_reg <= crc_reg_wire;
	// synopsys translate_off
	initial
		dataa_switch[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[0:0] <= 1'b0;
		else if  (wire_dataa_switch_ena[0:0] == 1'b1)   dataa_switch[0:0] <= wire_dataa_switch_d[0:0];
	// synopsys translate_off
	initial
		dataa_switch[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[1:1] <= 1'b0;
		else if  (wire_dataa_switch_ena[1:1] == 1'b1)   dataa_switch[1:1] <= wire_dataa_switch_d[1:1];
	// synopsys translate_off
	initial
		dataa_switch[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[2:2] <= 1'b0;
		else if  (wire_dataa_switch_ena[2:2] == 1'b1)   dataa_switch[2:2] <= wire_dataa_switch_d[2:2];
	// synopsys translate_off
	initial
		dataa_switch[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[3:3] <= 1'b0;
		else if  (wire_dataa_switch_ena[3:3] == 1'b1)   dataa_switch[3:3] <= wire_dataa_switch_d[3:3];
	// synopsys translate_off
	initial
		dataa_switch[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[4:4] <= 1'b0;
		else if  (wire_dataa_switch_ena[4:4] == 1'b1)   dataa_switch[4:4] <= wire_dataa_switch_d[4:4];
	// synopsys translate_off
	initial
		dataa_switch[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[5:5] <= 1'b0;
		else if  (wire_dataa_switch_ena[5:5] == 1'b1)   dataa_switch[5:5] <= wire_dataa_switch_d[5:5];
	// synopsys translate_off
	initial
		dataa_switch[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[6:6] <= 1'b0;
		else if  (wire_dataa_switch_ena[6:6] == 1'b1)   dataa_switch[6:6] <= wire_dataa_switch_d[6:6];
	// synopsys translate_off
	initial
		dataa_switch[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[7:7] <= 1'b0;
		else if  (wire_dataa_switch_ena[7:7] == 1'b1)   dataa_switch[7:7] <= wire_dataa_switch_d[7:7];
	// synopsys translate_off
	initial
		dataa_switch[8:8] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[8:8] <= 1'b0;
		else if  (wire_dataa_switch_ena[8:8] == 1'b1)   dataa_switch[8:8] <= wire_dataa_switch_d[8:8];
	// synopsys translate_off
	initial
		dataa_switch[9:9] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[9:9] <= 1'b0;
		else if  (wire_dataa_switch_ena[9:9] == 1'b1)   dataa_switch[9:9] <= wire_dataa_switch_d[9:9];
	// synopsys translate_off
	initial
		dataa_switch[10:10] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[10:10] <= 1'b0;
		else if  (wire_dataa_switch_ena[10:10] == 1'b1)   dataa_switch[10:10] <= wire_dataa_switch_d[10:10];
	// synopsys translate_off
	initial
		dataa_switch[11:11] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[11:11] <= 1'b0;
		else if  (wire_dataa_switch_ena[11:11] == 1'b1)   dataa_switch[11:11] <= wire_dataa_switch_d[11:11];
	// synopsys translate_off
	initial
		dataa_switch[12:12] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[12:12] <= 1'b0;
		else if  (wire_dataa_switch_ena[12:12] == 1'b1)   dataa_switch[12:12] <= wire_dataa_switch_d[12:12];
	// synopsys translate_off
	initial
		dataa_switch[13:13] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[13:13] <= 1'b0;
		else if  (wire_dataa_switch_ena[13:13] == 1'b1)   dataa_switch[13:13] <= wire_dataa_switch_d[13:13];
	// synopsys translate_off
	initial
		dataa_switch[14:14] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[14:14] <= 1'b0;
		else if  (wire_dataa_switch_ena[14:14] == 1'b1)   dataa_switch[14:14] <= wire_dataa_switch_d[14:14];
	// synopsys translate_off
	initial
		dataa_switch[15:15] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[15:15] <= 1'b0;
		else if  (wire_dataa_switch_ena[15:15] == 1'b1)   dataa_switch[15:15] <= wire_dataa_switch_d[15:15];
	// synopsys translate_off
	initial
		dataa_switch[16:16] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[16:16] <= 1'b0;
		else if  (wire_dataa_switch_ena[16:16] == 1'b1)   dataa_switch[16:16] <= wire_dataa_switch_d[16:16];
	// synopsys translate_off
	initial
		dataa_switch[17:17] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[17:17] <= 1'b0;
		else if  (wire_dataa_switch_ena[17:17] == 1'b1)   dataa_switch[17:17] <= wire_dataa_switch_d[17:17];
	// synopsys translate_off
	initial
		dataa_switch[18:18] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[18:18] <= 1'b0;
		else if  (wire_dataa_switch_ena[18:18] == 1'b1)   dataa_switch[18:18] <= wire_dataa_switch_d[18:18];
	// synopsys translate_off
	initial
		dataa_switch[19:19] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[19:19] <= 1'b0;
		else if  (wire_dataa_switch_ena[19:19] == 1'b1)   dataa_switch[19:19] <= wire_dataa_switch_d[19:19];
	// synopsys translate_off
	initial
		dataa_switch[20:20] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[20:20] <= 1'b0;
		else if  (wire_dataa_switch_ena[20:20] == 1'b1)   dataa_switch[20:20] <= wire_dataa_switch_d[20:20];
	// synopsys translate_off
	initial
		dataa_switch[21:21] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[21:21] <= 1'b0;
		else if  (wire_dataa_switch_ena[21:21] == 1'b1)   dataa_switch[21:21] <= wire_dataa_switch_d[21:21];
	// synopsys translate_off
	initial
		dataa_switch[22:22] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[22:22] <= 1'b0;
		else if  (wire_dataa_switch_ena[22:22] == 1'b1)   dataa_switch[22:22] <= wire_dataa_switch_d[22:22];
	// synopsys translate_off
	initial
		dataa_switch[23:23] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dataa_switch[23:23] <= 1'b0;
		else if  (wire_dataa_switch_ena[23:23] == 1'b1)   dataa_switch[23:23] <= wire_dataa_switch_d[23:23];
	assign
		wire_dataa_switch_d = {{18{1'b0}}, (get_addr & (~ crc_check_st)), {4{1'b0}}, (get_addr | crc_check_st)};
	assign
		wire_dataa_switch_ena = {24{(get_addr | crc_check_st)}};
	// synopsys translate_off
	initial
		dffe10a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe10a[0:0] <= 1'b0;
		else if  (wire_dffe10a_ena[0:0] == 1'b1)   dffe10a[0:0] <= combine_port[0:0];
	// synopsys translate_off
	initial
		dffe10a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe10a[1:1] <= 1'b0;
		else if  (wire_dffe10a_ena[1:1] == 1'b1)   dffe10a[1:1] <= combine_port[1:1];
	// synopsys translate_off
	initial
		dffe10a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe10a[2:2] <= 1'b0;
		else if  (wire_dffe10a_ena[2:2] == 1'b1)   dffe10a[2:2] <= combine_port[2:2];
	// synopsys translate_off
	initial
		dffe10a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe10a[3:3] <= 1'b0;
		else if  (wire_dffe10a_ena[3:3] == 1'b1)   dffe10a[3:3] <= combine_port[3:3];
	// synopsys translate_off
	initial
		dffe10a[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe10a[4:4] <= 1'b0;
		else if  (wire_dffe10a_ena[4:4] == 1'b1)   dffe10a[4:4] <= combine_port[4:4];
	// synopsys translate_off
	initial
		dffe10a[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe10a[5:5] <= 1'b0;
		else if  (wire_dffe10a_ena[5:5] == 1'b1)   dffe10a[5:5] <= combine_port[5:5];
	// synopsys translate_off
	initial
		dffe10a[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe10a[6:6] <= 1'b0;
		else if  (wire_dffe10a_ena[6:6] == 1'b1)   dffe10a[6:6] <= combine_port[6:6];
	assign
		wire_dffe10a_ena = {7{(idle & ((write_param_c3 | read_param_c3) | read_control_reg))}};
	// synopsys translate_off
	initial
		dffe1a0 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe1a0 <= 1'b0;
		else if  (wire_dffe1a_ena[0:0] == 1'b1)   dffe1a0 <= ((rsource_load & rsource_parallel_in[0]) | ((~ rsource_load) & dffe1a1[0:0]));
	// synopsys translate_off
	initial
		dffe1a1 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe1a1 <= 1'b0;
		else if  (wire_dffe1a_ena[1:1] == 1'b1)   dffe1a1 <= (rsource_parallel_in[1] & rsource_load);
	assign
		wire_dffe1a_ena = {2{(rsource_load | rsource_shift_enable)}};
	// synopsys translate_off
	initial
		dffe2a0 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe2a0 <= 1'b0;
		else if  (wire_dffe2a_ena[0:0] == 1'b1)   dffe2a0 <= ((rsource_load & rsource_state_par_ini[0]) | ((~ rsource_load) & dffe2a1[0:0]));
	// synopsys translate_off
	initial
		dffe2a1 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe2a1 <= 1'b0;
		else if  (wire_dffe2a_ena[1:1] == 1'b1)   dffe2a1 <= ((rsource_load & rsource_state_par_ini[1]) | ((~ rsource_load) & dffe2a2[0:0]));
	// synopsys translate_off
	initial
		dffe2a2 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe2a2 <= 1'b0;
		else if  (wire_dffe2a_ena[2:2] == 1'b1)   dffe2a2 <= (rsource_state_par_ini[2] & rsource_load);
	assign
		wire_dffe2a_ena = {3{(rsource_load | global_vcc)}};
	// synopsys translate_off
	initial
		dffe3a0 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe3a0 <= 1'b0;
		else if  (wire_dffe3a_ena[0:0] == 1'b1)   dffe3a0 <= ((rsource_load & wsource_state_par_ini[0]) | ((~ rsource_load) & dffe3a1[0:0]));
	// synopsys translate_off
	initial
		dffe3a1 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe3a1 <= 1'b0;
		else if  (wire_dffe3a_ena[1:1] == 1'b1)   dffe3a1 <= ((rsource_load & wsource_state_par_ini[1]) | ((~ rsource_load) & dffe3a2[0:0]));
	// synopsys translate_off
	initial
		dffe3a2 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe3a2 <= 1'b0;
		else if  (wire_dffe3a_ena[2:2] == 1'b1)   dffe3a2 <= (wsource_state_par_ini[2] & rsource_load);
	assign
		wire_dffe3a_ena = {3{(rsource_load | global_vcc)}};
	// synopsys translate_off
	initial
		dffe7a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[0:0] <= 1'b0;
		else if  (wire_dffe7a_ena[0:0] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[0:0] <= 1'b0;
			else  dffe7a[0:0] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[2]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[0]))) | ((~ shift_reg_load_enable) & dffe7a[1:1]));
	// synopsys translate_off
	initial
		dffe7a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[1:1] <= 1'b0;
		else if  (wire_dffe7a_ena[1:1] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[1:1] <= 1'b0;
			else  dffe7a[1:1] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[3]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[1]))) | ((~ shift_reg_load_enable) & dffe7a[2:2]));
	// synopsys translate_off
	initial
		dffe7a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[2:2] <= 1'b0;
		else if  (wire_dffe7a_ena[2:2] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[2:2] <= 1'b0;
			else  dffe7a[2:2] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[4]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[2]))) | ((~ shift_reg_load_enable) & dffe7a[3:3]));
	// synopsys translate_off
	initial
		dffe7a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[3:3] <= 1'b0;
		else if  (wire_dffe7a_ena[3:3] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[3:3] <= 1'b0;
			else  dffe7a[3:3] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[5]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[3]))) | ((~ shift_reg_load_enable) & dffe7a[4:4]));
	// synopsys translate_off
	initial
		dffe7a[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[4:4] <= 1'b0;
		else if  (wire_dffe7a_ena[4:4] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[4:4] <= 1'b0;
			else  dffe7a[4:4] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[6]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[4]))) | ((~ shift_reg_load_enable) & dffe7a[5:5]));
	// synopsys translate_off
	initial
		dffe7a[5:5] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[5:5] <= 1'b0;
		else if  (wire_dffe7a_ena[5:5] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[5:5] <= 1'b0;
			else  dffe7a[5:5] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[7]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[5]))) | ((~ shift_reg_load_enable) & dffe7a[6:6]));
	// synopsys translate_off
	initial
		dffe7a[6:6] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[6:6] <= 1'b0;
		else if  (wire_dffe7a_ena[6:6] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[6:6] <= 1'b0;
			else  dffe7a[6:6] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[8]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[6]))) | ((~ shift_reg_load_enable) & dffe7a[7:7]));
	// synopsys translate_off
	initial
		dffe7a[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[7:7] <= 1'b0;
		else if  (wire_dffe7a_ena[7:7] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[7:7] <= 1'b0;
			else  dffe7a[7:7] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[9]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[7]))) | ((~ shift_reg_load_enable) & dffe7a[8:8]));
	// synopsys translate_off
	initial
		dffe7a[8:8] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[8:8] <= 1'b0;
		else if  (wire_dffe7a_ena[8:8] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[8:8] <= 1'b0;
			else  dffe7a[8:8] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[10]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[8]))) | ((~ shift_reg_load_enable) & dffe7a[9:9]));
	// synopsys translate_off
	initial
		dffe7a[9:9] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[9:9] <= 1'b0;
		else if  (wire_dffe7a_ena[9:9] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[9:9] <= 1'b0;
			else  dffe7a[9:9] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[11]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[9]))) | ((~ shift_reg_load_enable) & dffe7a[10:10]));
	// synopsys translate_off
	initial
		dffe7a[10:10] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[10:10] <= 1'b0;
		else if  (wire_dffe7a_ena[10:10] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[10:10] <= 1'b0;
			else  dffe7a[10:10] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[12]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[10]))) | ((~ shift_reg_load_enable) & dffe7a[11:11]));
	// synopsys translate_off
	initial
		dffe7a[11:11] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[11:11] <= 1'b0;
		else if  (wire_dffe7a_ena[11:11] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[11:11] <= 1'b0;
			else  dffe7a[11:11] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[13]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[11]))) | ((~ shift_reg_load_enable) & dffe7a[12:12]));
	// synopsys translate_off
	initial
		dffe7a[12:12] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[12:12] <= 1'b0;
		else if  (wire_dffe7a_ena[12:12] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[12:12] <= 1'b0;
			else  dffe7a[12:12] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[14]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[12]))) | ((~ shift_reg_load_enable) & dffe7a[13:13]));
	// synopsys translate_off
	initial
		dffe7a[13:13] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[13:13] <= 1'b0;
		else if  (wire_dffe7a_ena[13:13] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[13:13] <= 1'b0;
			else  dffe7a[13:13] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[15]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[13]))) | ((~ shift_reg_load_enable) & dffe7a[14:14]));
	// synopsys translate_off
	initial
		dffe7a[14:14] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[14:14] <= 1'b0;
		else if  (wire_dffe7a_ena[14:14] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[14:14] <= 1'b0;
			else  dffe7a[14:14] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[16]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[14]))) | ((~ shift_reg_load_enable) & dffe7a[15:15]));
	// synopsys translate_off
	initial
		dffe7a[15:15] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[15:15] <= 1'b0;
		else if  (wire_dffe7a_ena[15:15] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[15:15] <= 1'b0;
			else  dffe7a[15:15] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[17]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[15]))) | ((~ shift_reg_load_enable) & dffe7a[16:16]));
	// synopsys translate_off
	initial
		dffe7a[16:16] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[16:16] <= 1'b0;
		else if  (wire_dffe7a_ena[16:16] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[16:16] <= 1'b0;
			else  dffe7a[16:16] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[18]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[16]))) | ((~ shift_reg_load_enable) & dffe7a[17:17]));
	// synopsys translate_off
	initial
		dffe7a[17:17] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[17:17] <= 1'b0;
		else if  (wire_dffe7a_ena[17:17] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[17:17] <= 1'b0;
			else  dffe7a[17:17] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[19]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[17]))) | ((~ shift_reg_load_enable) & dffe7a[18:18]));
	// synopsys translate_off
	initial
		dffe7a[18:18] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[18:18] <= 1'b0;
		else if  (wire_dffe7a_ena[18:18] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[18:18] <= 1'b0;
			else  dffe7a[18:18] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[20]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[18]))) | ((~ shift_reg_load_enable) & dffe7a[19:19]));
	// synopsys translate_off
	initial
		dffe7a[19:19] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[19:19] <= 1'b0;
		else if  (wire_dffe7a_ena[19:19] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[19:19] <= 1'b0;
			else  dffe7a[19:19] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[21]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[19]))) | ((~ shift_reg_load_enable) & dffe7a[20:20]));
	// synopsys translate_off
	initial
		dffe7a[20:20] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[20:20] <= 1'b0;
		else if  (wire_dffe7a_ena[20:20] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[20:20] <= 1'b0;
			else  dffe7a[20:20] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[22]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[20]))) | ((~ shift_reg_load_enable) & dffe7a[21:21]));
	// synopsys translate_off
	initial
		dffe7a[21:21] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[21:21] <= 1'b0;
		else if  (wire_dffe7a_ena[21:21] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[21:21] <= 1'b0;
			else  dffe7a[21:21] <= ((shift_reg_load_enable & ((((param[2] & (~ param[1])) & (~ param[0])) & data_in[23]) | ((~ ((param[2] & (~ param[1])) & (~ param[0]))) & data_in[21]))) | ((~ shift_reg_load_enable) & dffe7a[22:22]));
	// synopsys translate_off
	initial
		dffe7a[22:22] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[22:22] <= 1'b0;
		else if  (wire_dffe7a_ena[22:22] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[22:22] <= 1'b0;
			else  dffe7a[22:22] <= ((~ shift_reg_load_enable) & dffe7a[23:23]);
	// synopsys translate_off
	initial
		dffe7a[23:23] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[23:23] <= 1'b0;
		else if  (wire_dffe7a_ena[23:23] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[23:23] <= 1'b0;
			else  dffe7a[23:23] <= ((~ shift_reg_load_enable) & dffe7a[24:24]);
	// synopsys translate_off
	initial
		dffe7a[24:24] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[24:24] <= 1'b0;
		else if  (wire_dffe7a_ena[24:24] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[24:24] <= 1'b0;
			else  dffe7a[24:24] <= ((~ shift_reg_load_enable) & dffe7a[25:25]);
	// synopsys translate_off
	initial
		dffe7a[25:25] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[25:25] <= 1'b0;
		else if  (wire_dffe7a_ena[25:25] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[25:25] <= 1'b0;
			else  dffe7a[25:25] <= ((~ shift_reg_load_enable) & dffe7a[26:26]);
	// synopsys translate_off
	initial
		dffe7a[26:26] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[26:26] <= 1'b0;
		else if  (wire_dffe7a_ena[26:26] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[26:26] <= 1'b0;
			else  dffe7a[26:26] <= ((~ shift_reg_load_enable) & dffe7a[27:27]);
	// synopsys translate_off
	initial
		dffe7a[27:27] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[27:27] <= 1'b0;
		else if  (wire_dffe7a_ena[27:27] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[27:27] <= 1'b0;
			else  dffe7a[27:27] <= ((~ shift_reg_load_enable) & dffe7a[28:28]);
	// synopsys translate_off
	initial
		dffe7a[28:28] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe7a[28:28] <= 1'b0;
		else if  (wire_dffe7a_ena[28:28] == 1'b1) 
			if (shift_reg_clear == 1'b1) dffe7a[28:28] <= 1'b0;
			else  dffe7a[28:28] <= ((~ shift_reg_load_enable) & shift_reg_serial_in);
	assign
		wire_dffe7a_ena = {29{((shift_reg_load_enable | shift_reg_shift_enable) | shift_reg_clear)}};
	// synopsys translate_off
	initial
		dffe9 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) dffe9 <= 1'b0;
		else  dffe9 <= rublock_regout;
	// synopsys translate_off
	initial
		get_addr_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) get_addr_reg <= 1'b0;
		else  get_addr_reg <= (((~ wire_cntr11_q[2]) & wire_cntr11_q[1]) & wire_cntr11_q[0]);
	// synopsys translate_off
	initial
		idle_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) idle_state <= {1{1'b1}};
		else  idle_state <= ((((((((idle & (~ read_param_c3)) & (~ write_param_c3)) & (~ read_control_reg)) | write_wait) | (read_data & width_counter_all_done)) | (read_post & width_counter_all_done)) | power_up) & (~ check_busy_dffe));
	// synopsys translate_off
	initial
		idle_write_wait = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) idle_write_wait <= 1'b0;
		else  idle_write_wait <= ((((((((idle & (~ read_param_c3)) & (~ write_param_c3)) & (~ read_control_reg)) | write_wait) | (read_data & width_counter_all_done)) | (read_post & width_counter_all_done)) | power_up) & write_load);
	// synopsys translate_off
	initial
		load_crc_high_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) load_crc_high_reg <= 1'b0;
		else  load_crc_high_reg <= ((((~ wire_cntr12_q[2]) & wire_cntr12_q[1]) & (~ wire_cntr12_q[0])) & (((((wire_cntr14_q[5] & (~ wire_cntr14_q[4])) & wire_cntr14_q[3]) & (~ wire_cntr14_q[2])) & (~ wire_cntr14_q[1])) & wire_cntr14_q[0]));
	// synopsys translate_off
	initial
		load_crc_low_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) load_crc_low_reg <= 1'b0;
		else  load_crc_low_reg <= ((((~ wire_cntr12_q[2]) & wire_cntr12_q[1]) & (~ wire_cntr12_q[0])) & (((((wire_cntr14_q[5] & (~ wire_cntr14_q[4])) & wire_cntr14_q[3]) & (~ wire_cntr14_q[2])) & (~ wire_cntr14_q[1])) & (~ wire_cntr14_q[0])));
	// synopsys translate_off
	initial
		load_data_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) load_data_reg <= 1'b0;
		else  load_data_reg <= (((~ wire_cntr12_q[2]) & wire_cntr12_q[1]) & (~ wire_cntr12_q[0]));
	// synopsys translate_off
	initial
		pof_counter_l42 = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) pof_counter_l42 <= 1'b0;
		else
			if (crc_check_st_wire == 1'b1) pof_counter_l42 <= 1'b0;
			else  pof_counter_l42 <= (((wire_cntr14_q[5] & wire_cntr14_q[3]) & wire_cntr14_q[0]) | ((wire_cntr14_q[5] & wire_cntr14_q[3]) & wire_cntr14_q[1]));
	// synopsys translate_off
	initial
		pof_error_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) pof_error_reg <= 1'b0;
		else if  (wire_pof_error_reg_ena == 1'b1) 
			if (crc_check_st_wire == 1'b1) pof_error_reg <= 1'b0;
			else  pof_error_reg <= pof_error_wire;
	assign
		wire_pof_error_reg_ena = (crc_check_end | crc_check_st_wire);
	// synopsys translate_off
	initial
		re_config_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) re_config_reg <= 1'b0;
		else
			if (crc_check_st_wire == 1'b1) re_config_reg <= 1'b0;
			else  re_config_reg <= (ru_reconfig_pof & (~ pof_error_reg));
	// synopsys translate_off
	initial
		read_address_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) read_address_state <= 1'b0;
		else if  (wire_read_address_state_ena == 1'b1)   read_address_state <= (((read_param | write_param) & ((param[2] & (~ param[1])) & (~ param[0]))) & (~ ((((~ idle) | check_busy_dffe) | ru_reconfig_pof) | (~ st_v0))));
	assign
		wire_read_address_state_ena = (read_param | write_param);
	// synopsys translate_off
	initial
		read_control_reg_dffe = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) read_control_reg_dffe <= 1'b0;
		else  read_control_reg_dffe <= (((~ wire_cntr11_q[2]) & (~ wire_cntr11_q[1])) & wire_cntr11_q[0]);
	// synopsys translate_off
	initial
		read_data_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) read_data_state <= 1'b0;
		else  read_data_state <= (((read_init_counter & bit_counter_param_start_match) | (read_pre_data & bit_counter_param_start_match)) | ((read_data & (~ width_counter_param_width_match)) & (~ width_counter_all_done)));
	// synopsys translate_off
	initial
		read_init_counter_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) read_init_counter_state <= 1'b0;
		else  read_init_counter_state <= rsource_update_done;
	// synopsys translate_off
	initial
		read_init_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) read_init_state <= 1'b0;
		else  read_init_state <= (idle & (read_param_c3 | read_control_reg));
	// synopsys translate_off
	initial
		read_post_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) read_post_state <= 1'b0;
		else  read_post_state <= (((read_data & width_counter_param_width_match) & (~ width_counter_all_done)) | (read_post & (~ width_counter_all_done)));
	// synopsys translate_off
	initial
		read_pre_data_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) read_pre_data_state <= 1'b0;
		else  read_pre_data_state <= ((read_init_counter & (~ bit_counter_param_start_match)) | (read_pre_data & (~ bit_counter_param_start_match)));
	// synopsys translate_off
	initial
		read_source_update_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) read_source_update_state <= 1'b0;
		else  read_source_update_state <= ((read_init | read_source_update) & (~ rsource_update_done));
	// synopsys translate_off
	initial
		reconfig_width_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) reconfig_width_reg <= 1'b0;
		else
			if (wire_cntr15_cout == 1'b1) reconfig_width_reg <= 1'b0;
			else  reconfig_width_reg <= (((wire_cntr11_q[2] & wire_cntr11_q[1]) & wire_cntr11_q[0]) | reconfig_width_reg);
	// synopsys translate_off
	initial
		ru_reconfig_pof_reg = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) ru_reconfig_pof_reg <= 1'b0;
		else  ru_reconfig_pof_reg <= (((wire_cntr11_q[2] & wire_cntr11_q[1]) & wire_cntr11_q[0]) | ((wire_cntr15_q[2] | wire_cntr15_q[1]) | wire_cntr15_q[0]));
	// synopsys translate_off
	initial
		write_data_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) write_data_state <= 1'b0;
		else  write_data_state <= (((write_init_counter & bit_counter_param_start_match) | (write_pre_data & bit_counter_param_start_match)) | ((write_data & (~ width_counter_param_width_match)) & (~ bit_counter_all_done)));
	// synopsys translate_off
	initial
		write_init_counter_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) write_init_counter_state <= 1'b0;
		else  write_init_counter_state <= wsource_update_done;
	// synopsys translate_off
	initial
		write_init_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) write_init_state <= 1'b0;
		else  write_init_state <= (idle & write_param_c3);
	// synopsys translate_off
	initial
		write_load_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) write_load_state <= 1'b0;
		else  write_load_state <= ((write_data & bit_counter_all_done) | (write_post_data & bit_counter_all_done));
	// synopsys translate_off
	initial
		write_post_data_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) write_post_data_state <= 1'b0;
		else  write_post_data_state <= (((write_data & width_counter_param_width_match) & (~ bit_counter_all_done)) | (write_post_data & (~ bit_counter_all_done)));
	// synopsys translate_off
	initial
		write_pre_data_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) write_pre_data_state <= 1'b0;
		else  write_pre_data_state <= ((write_init_counter & (~ bit_counter_param_start_match)) | (write_pre_data & (~ bit_counter_param_start_match)));
	// synopsys translate_off
	initial
		write_source_update_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) write_source_update_state <= 1'b0;
		else  write_source_update_state <= ((write_init | write_source_update) & (~ wsource_update_done));
	// synopsys translate_off
	initial
		write_wait_state = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge reset)
		if (reset == 1'b1) write_wait_state <= 1'b0;
		else  write_wait_state <= write_load;
	lpm_add_sub   add_sub16
	( 
	.aclr(reset),
	.clken(cal_addr),
	.clock(clock),
	.cout(),
	.dataa(dataa_switch),
	.datab(asmi_addr_st),
	.overflow(),
	.result(wire_add_sub16_result)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.add_sub(1'b1),
	.cin()
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		add_sub16.lpm_direction = "ADD",
		add_sub16.lpm_pipeline = 1,
		add_sub16.lpm_width = 24,
		add_sub16.lpm_type = "lpm_add_sub";
	lpm_counter   cntr11
	( 
	.aclr(reset),
	.clk_en(chk_pof_counter_enable),
	.clock(clock),
	.cout(),
	.eq(),
	.q(wire_cntr11_q)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.data({3{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr11.lpm_port_updown = "PORT_UNUSED",
		cntr11.lpm_width = 3,
		cntr11.lpm_type = "lpm_counter";
	lpm_counter   cntr12
	( 
	.aclr(reset),
	.clk_en(chk_crc_counter_enable),
	.clock(clock),
	.cout(),
	.data({{2{1'b0}}, 1'b1}),
	.eq(),
	.q(wire_cntr12_q),
	.sload(asmi_read_reg)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.sclr(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr12.lpm_modulus = 7,
		cntr12.lpm_port_updown = "PORT_UNUSED",
		cntr12.lpm_width = 3,
		cntr12.lpm_type = "lpm_counter";
	lpm_counter   cntr13
	( 
	.aclr(reset),
	.clk_en(crc_cal_reg),
	.clock(clock),
	.cout(),
	.eq(),
	.q(wire_cntr13_q)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.data({3{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr13.lpm_modulus = 8,
		cntr13.lpm_port_updown = "PORT_UNUSED",
		cntr13.lpm_width = 3,
		cntr13.lpm_type = "lpm_counter";
	lpm_counter   cntr14
	( 
	.aclr(reset),
	.clk_en((asmi_read_wire | ((wire_cntr11_q[2] & (~ wire_cntr11_q[1])) & wire_cntr11_q[0]))),
	.clock(clock),
	.cout(wire_cntr14_cout),
	.eq(),
	.q(wire_cntr14_q),
	.sclr(crc_check_st)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.data({6{1'b0}}),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr14.lpm_modulus = 43,
		cntr14.lpm_port_updown = "PORT_UNUSED",
		cntr14.lpm_width = 6,
		cntr14.lpm_type = "lpm_counter";
	lpm_counter   cntr15
	( 
	.aclr(reset),
	.clk_en((((wire_cntr11_q[2] & wire_cntr11_q[1]) & wire_cntr11_q[0]) | reconfig_width_reg)),
	.clock(clock),
	.cout(wire_cntr15_cout),
	.eq(),
	.q(wire_cntr15_q)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.cnt_en(1'b1),
	.data({3{1'b0}}),
	.sclr(1'b0),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr15.lpm_modulus = 4,
		cntr15.lpm_port_updown = "PORT_UNUSED",
		cntr15.lpm_width = 3,
		cntr15.lpm_type = "lpm_counter";
	lpm_counter   cntr5
	( 
	.aclr(reset),
	.clock(clock),
	.cnt_en(bit_counter_enable),
	.cout(),
	.eq(),
	.q(wire_cntr5_q),
	.sclr(bit_counter_clear)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.clk_en(1'b1),
	.data({6{1'b0}}),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr5.lpm_direction = "UP",
		cntr5.lpm_port_updown = "PORT_UNUSED",
		cntr5.lpm_width = 6,
		cntr5.lpm_type = "lpm_counter";
	lpm_counter   cntr6
	( 
	.aclr(reset),
	.clock(clock),
	.cnt_en(width_counter_enable),
	.cout(),
	.eq(),
	.q(wire_cntr6_q),
	.sclr(width_counter_clear)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.clk_en(1'b1),
	.data({5{1'b0}}),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr6.lpm_direction = "UP",
		cntr6.lpm_port_updown = "PORT_UNUSED",
		cntr6.lpm_width = 5,
		cntr6.lpm_type = "lpm_counter";
	lpm_counter   cntr8
	( 
	.aclr(reset),
	.clock(clock),
	.cnt_en(st_counter_enable),
	.cout(),
	.eq(),
	.q(wire_cntr8_q),
	.sclr(((((st_v4 & (~ (((~ idle) | check_busy_dffe) | ru_reconfig_pof))) | st_v5) | st_v6) | st_v7))
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aload(1'b0),
	.aset(1'b0),
	.cin(1'b1),
	.clk_en(1'b1),
	.data({3{1'b0}}),
	.sload(1'b0),
	.sset(1'b0),
	.updown(1'b1)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		cntr8.lpm_direction = "UP",
		cntr8.lpm_port_updown = "PORT_UNUSED",
		cntr8.lpm_width = 3,
		cntr8.lpm_type = "lpm_counter";
	lpm_shiftreg   shift_reg17
	( 
	.aclr(reset),
	.clock(clock),
	.data(asim_data_reg),
	.enable((crc_cal | load_data)),
	.load(load_data),
	.q(),
	.sclr(crc_check_st),
	.shiftout(wire_shift_reg17_shiftout)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_off
	`endif
	,
	.aset(1'b0),
	.shiftin(1'b1),
	.sset(1'b0)
	`ifndef FORMAL_VERIFICATION
	// synopsys translate_on
	`endif
	);
	defparam
		shift_reg17.lpm_direction = "RIGHT",
		shift_reg17.lpm_width = 8,
		shift_reg17.lpm_type = "lpm_shiftreg";
	cycloneive_rublock   sd4
	( 
	.captnupdt(rublock_captnupdt),
	.clk(rublock_clock),
	.rconfig(rublock_reconfig),
	.regin(rublock_regin),
	.regout(wire_sd4_regout),
	.rsttimer(reset_timer),
	.shiftnld(rublock_shiftnld));
	assign
		asmi_addr = wire_add_sub16_result,
		asmi_rden = asmi_read_out,
		asmi_read = asmi_read_out,
		asmi_read_out = ((crc_chk_st_dffe | asmi_read_reg) & (~ pof_counter_l42)),
		asmi_read_wire = (crc_chk_st_dffe | asmi_read_reg),
		bit_counter_all_done = (((((wire_cntr5_q[0] & (~ wire_cntr5_q[1])) & (~ wire_cntr5_q[2])) & wire_cntr5_q[3]) & (~ wire_cntr5_q[4])) & wire_cntr5_q[5]),
		bit_counter_clear = (rsource_update_done | wsource_update_done),
		bit_counter_enable = (((((((((rsource_update_done | wsource_update_done) | read_init_counter) | write_init_counter) | read_pre_data) | write_pre_data) | read_data) | write_data) | read_post) | write_post_data),
		bit_counter_param_start = start_bit_decoder_out,
		bit_counter_param_start_match = ((((((~ w53w[0]) & (~ w53w[1])) & (~ w53w[2])) & (~ w53w[3])) & (~ w53w[4])) & (~ w53w[5])),
		busy = ((((~ idle) | check_busy_dffe) | ru_reconfig_pof) | (~ st_v0)),
		cal_addr = cal_addr_reg,
		chk_crc_counter_enable = (((((((((((~ wire_cntr12_q[2]) & (~ wire_cntr12_q[1])) & (~ wire_cntr12_q[0])) & crc_check_st) | ((((~ wire_cntr12_q[2]) & (~ wire_cntr12_q[1])) & wire_cntr12_q[0]) & asmi_data_valid)) | (((~ wire_cntr12_q[2]) & wire_cntr12_q[1]) & (~ wire_cntr12_q[0]))) | ((((~ wire_cntr12_q[2]) & wire_cntr12_q[1]) & wire_cntr12_q[0]) & crc_shift_done)) | (((wire_cntr12_q[2] & (~ wire_cntr12_q[1])) & (~ wire_cntr12_q[0])) & (~ asmi_busy))) | ((wire_cntr12_q[2] & (~ wire_cntr12_q[1])) & wire_cntr12_q[0])) | (((wire_cntr12_q[2] & wire_cntr12_q[1]) & (~ wire_cntr12_q[0])) & wire_cntr14_cout)) | ((wire_cntr12_q[2] & wire_cntr12_q[1]) & (~ wire_cntr12_q[0]))),
		chk_pof_counter_enable = (((((((((((~ wire_cntr11_q[2]) & (~ wire_cntr11_q[1])) & (~ wire_cntr11_q[0])) & chk_pof_counter_start) | (((~ wire_cntr11_q[2]) & (~ wire_cntr11_q[1])) & wire_cntr11_q[0])) | (((((~ wire_cntr11_q[2]) & wire_cntr11_q[1]) & (~ wire_cntr11_q[0])) & (~ bit_counter_enable)) & (~ read_control_reg))) | (((~ wire_cntr11_q[2]) & wire_cntr11_q[1]) & wire_cntr11_q[0])) | ((wire_cntr11_q[2] & (~ wire_cntr11_q[1])) & (~ wire_cntr11_q[0]))) | ((wire_cntr11_q[2] & (~ wire_cntr11_q[1])) & wire_cntr11_q[0])) | (((wire_cntr11_q[2] & wire_cntr11_q[1]) & (~ wire_cntr11_q[0])) & wire_cntr14_cout)) | ((wire_cntr11_q[2] & wire_cntr11_q[1]) & wire_cntr11_q[0])),
		chk_pof_counter_start = (idle & reconfig_c3),
		combine_port = {read_param_c3, write_param_c3, read_source_c3, param_c3},
		crc = crc_reg,
		crc_cal = (crc_cal_reg & (~ crc_done_reg)),
		crc_check_end = crc_check_end_reg,
		crc_check_st = crc_chk_st_dffe,
		crc_check_st_wire = ((wire_cntr11_q[2] & (~ wire_cntr11_q[1])) & wire_cntr11_q[0]),
		crc_enable_wire = (crc_cal | crc_check_st_wire),
		crc_reg_wire = {((halt_cal & crc_reg[15]) | ((~ halt_cal) & invert_bits)), ((halt_cal & crc_reg[14]) | ((~ halt_cal) & crc_reg[15])), ((halt_cal & crc_reg[13]) | ((~ halt_cal) & (crc_reg[14] ^ invert_bits))), ((halt_cal & crc_reg[12]) | ((~ halt_cal) & crc_reg[13])), ((halt_cal & crc_reg[11]) | ((~ halt_cal) & crc_reg[12])), ((halt_cal & crc_reg[10]) | ((~ halt_cal) & crc_reg[11])), ((halt_cal & crc_reg[9]) | ((~ halt_cal) & crc_reg[10])), ((halt_cal & crc_reg[8]) | ((~ halt_cal) & crc_reg[9])), ((halt_cal & crc_reg[7]) | ((~ halt_cal) & crc_reg[8])), ((halt_cal & crc_reg[6]) | ((~ halt_cal) & crc_reg[7])), ((halt_cal & crc_reg[5]) | ((~ halt_cal) & crc_reg[6])), ((halt_cal & crc_reg[4]) | ((~ halt_cal) & crc_reg[5])), ((halt_cal & crc_reg[3]) | ((~ halt_cal) & crc_reg[4])), ((halt_cal & crc_reg[2]) | ((~ halt_cal) & crc_reg[3])), ((halt_cal & crc_reg[1]) | ((~ halt_cal) & crc_reg[2])), ((halt_cal & crc_reg[0]) | ((~ halt_cal) & (crc_reg[1] ^ invert_bits)))},
		crc_shift_done = ((wire_cntr13_q[2] & wire_cntr13_q[1]) & (~ wire_cntr13_q[0])),
		data_out = {((read_address & dffe7a[26]) | ((~ read_address) & dffe7a[28])), ((read_address & dffe7a[25]) | ((~ read_address) & dffe7a[27])), ((read_address & dffe7a[24]) | ((~ read_address) & dffe7a[26])), ((read_address & dffe7a[23]) | ((~ read_address) & dffe7a[25])), ((read_address & dffe7a[22]) | ((~ read_address) & dffe7a[24])), ((read_address & dffe7a[21]) | ((~ read_address) & dffe7a[23])), ((read_address & dffe7a[20]) | ((~ read_address) & dffe7a[22])), ((read_address & dffe7a[19]) | ((~ read_address) & dffe7a[21])), ((read_address & dffe7a[18]) | ((~ read_address) & dffe7a[20])), ((read_address & dffe7a[17]) | ((~ read_address) & dffe7a[19])), ((read_address & dffe7a[16]) | ((~ read_address) & dffe7a[18])), ((read_address & dffe7a[15]) | ((~ read_address) & dffe7a[17])), ((read_address & dffe7a[14]) | ((~ read_address) & dffe7a[16])), ((read_address & dffe7a[13]) | ((~ read_address) & dffe7a[15])), ((read_address & dffe7a[12]) | ((~ read_address) & dffe7a[14])), ((read_address & dffe7a[11]) | ((~ read_address) & dffe7a[13])), ((read_address & dffe7a[10]) | ((~ read_address) & dffe7a[12])), ((read_address & dffe7a[9]) | ((~ read_address) & dffe7a[11])), ((read_address & dffe7a[8]) | ((~ read_address) & dffe7a[10])), ((read_address & dffe7a[7]) | ((~ read_address) & dffe7a[9])), ((read_address & dffe7a[6]) | ((~ read_address) & dffe7a[8])), ((read_address & dffe7a[5]) | ((~ read_address) & dffe7a[7])), ((read_address & dffe7a[4]) | ((~ read_address) & dffe7a[6])), ((read_address & dffe7a[3]) | ((~ read_address) & dffe7a[5])), ((read_address & dffe7a[2]) | ((~ read_address) & dffe7a[4])), ((read_address & dffe7a[1]) | ((~ read_address) & dffe7a[3])), ((read_address & dffe7a[0]) | ((~ read_address) & dffe7a[2])), ((~ read_address) & dffe7a[1]), ((~ read_address) & dffe7a[0])},
		get_addr = get_addr_reg,
		global_gnd = 1'b0,
		global_vcc = 1'b1,
		idle = idle_state,
		invert_bits = (wire_shift_reg17_shiftout ^ crc_reg[0]),
		load_crc_high = load_crc_high_reg,
		load_crc_low = load_crc_low_reg,
		load_data = load_data_reg,
		param_c3 = {((param[2] & st_v0) | (st_v1 | st_v2)), (param[1] & st_v0), (param[0] & st_v0)},
		param_decoder_param_latch = dffe10a,
		param_decoder_select = {(((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2]
)) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), ((((((param_decoder_param_latch[0] & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & param_decoder_param_latch[5]) & (~ param_decoder_param_latch[6])), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5]
)) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & param_decoder_param_latch[4]) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), ((((((param_decoder_param_latch[0] & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & param_decoder_param_latch[1]) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & param_decoder_param_latch[3]) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & param_decoder_param_latch[2]) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6]), (((((((~ param_decoder_param_latch[0]) & (~ param_decoder_param_latch[1])) & (~ param_decoder_param_latch[2])) & (~ param_decoder_param_latch[3])) & (~ param_decoder_param_latch[4])) & (~ param_decoder_param_latch[5])) & param_decoder_param_latch[6])},
		pof_counter_40 = (((((wire_cntr14_q[5] & (~ wire_cntr14_q[4])) & wire_cntr14_q[3]) & (~ wire_cntr14_q[2])) & (~ wire_cntr14_q[1])) & (~ wire_cntr14_q[0])),
		pof_error = pof_error_reg,
		pof_error_wire = ((((((((((((((((crc[0] ^ crc_low[0]) | (crc[8] ^ crc_high[0])) | (crc[1] ^ crc_low[1])) | (crc[9] ^ crc_high[1])) | (crc[2] ^ crc_low[2])) | (crc[10] ^ crc_high[2])) | (crc[3] ^ crc_low[3])) | (crc[11] ^ crc_high[3])) | (crc[4] ^ crc_low[4])) | (crc[12] ^ crc_high[4])) | (crc[5] ^ crc_low[5])) | (crc[13] ^ crc_high[5])) | (crc[6] ^ crc_low[6])) | (crc[14] ^ crc_high[6])) | (crc[7] ^ crc_low[7])) | (crc[15] ^ crc_high[7])),
		power_up = (((((((((((((((~ idle) & (~ read_init)) & (~ read_source_update)) & (~ read_init_counter)) & (~ read_pre_data)) & (~ read_data)) & (~ read_post)) & (~ write_init)) & (~ write_init_counter)) & (~ write_source_update)) & (~ write_pre_data)) & (~ write_data)) & (~ write_post_data)) & (~ write_load)) & (~ write_wait)),
		read_address = read_address_state,
		read_control_reg = read_control_reg_dffe,
		read_data = read_data_state,
		read_init = read_init_state,
		read_init_counter = read_init_counter_state,
		read_param_c3 = ((read_param & st_v0) | st_v2),
		read_post = read_post_state,
		read_pre_data = read_pre_data_state,
		read_source_c3 = {((read_source[1] & st_v0) | (st_v1 | st_v2)), ((read_source[0] & st_v0) | (st_v1 | st_v2))},
		read_source_update = read_source_update_state,
		reconfig_c3 = (st_v2 | st_v3),
		rsource_load = (idle & (write_param_c3 | read_param_c3)),
		rsource_parallel_in = {((w4w[1] & read_param_c3) | write_param_c3), ((w4w[0] & read_param_c3) | write_param_c3)},
		rsource_serial_out = dffe1a0[0:0],
		rsource_shift_enable = (read_source_update | write_source_update),
		rsource_state_par_ini = {read_param_c3, {2{global_gnd}}},
		rsource_update_done = dffe2a0[0:0],
		ru_reconfig_pof = ru_reconfig_pof_reg,
		rublock_captnupdt = (~ write_load),
		rublock_clock = (~ (clock | idle_write_wait)),
		rublock_reconfig = re_config_reg,
		rublock_regin = (((((rublock_regout_reg & (~ select_shift_nloop)) & (~ read_source_update)) & (~ write_source_update)) | (((shift_reg_serial_out & select_shift_nloop) & (~ read_source_update)) & (~ write_source_update))) | ((read_source_update | write_source_update) & rsource_serial_out)),
		rublock_regout = wire_sd4_regout,
		rublock_regout_reg = dffe9,
		rublock_shiftnld = (((((((read_pre_data | write_pre_data) | read_data) | write_data) | read_post) | write_post_data) | read_source_update) | write_source_update),
		select_shift_nloop = ((read_data & (~ width_counter_param_width_match)) | (write_data & (~ width_counter_param_width_match))),
		shift_reg_clear = (idle & (read_param_c3 | read_control_reg)),
		shift_reg_load_enable = (idle & write_param_c3),
		shift_reg_q = dffe7a,
		shift_reg_serial_in = (rublock_regout_reg & select_shift_nloop),
		shift_reg_serial_out = dffe7a[0:0],
		shift_reg_shift_enable = (((read_data | write_data) | read_post) | write_post_data),
		st_counter_enable = (((((st_v0 & (~ (((~ idle) | check_busy_dffe) | ru_reconfig_pof))) & reconfig) | st_v1) | st_v2) | st_v3),
		st_v0 = (((~ wire_cntr8_q[2]) & (~ wire_cntr8_q[1])) & (~ wire_cntr8_q[0])),
		st_v1 = (((~ wire_cntr8_q[2]) & (~ wire_cntr8_q[1])) & wire_cntr8_q[0]),
		st_v2 = (((~ wire_cntr8_q[2]) & wire_cntr8_q[1]) & (~ wire_cntr8_q[0])),
		st_v3 = (((~ wire_cntr8_q[2]) & wire_cntr8_q[1]) & wire_cntr8_q[0]),
		st_v4 = ((wire_cntr8_q[2] & (~ wire_cntr8_q[1])) & (~ wire_cntr8_q[0])),
		st_v5 = ((wire_cntr8_q[2] & (~ wire_cntr8_q[1])) & wire_cntr8_q[0]),
		st_v6 = ((wire_cntr8_q[2] & wire_cntr8_q[1]) & (~ wire_cntr8_q[0])),
		st_v7 = ((wire_cntr8_q[2] & wire_cntr8_q[1]) & wire_cntr8_q[0]),
		start_bit_decoder_out = (((((((((((((((((((((({1'b0, {4{start_bit_decoder_param_select[0]}}, 1'b0} | {6{1'b0}}) | {1'b0, {4{start_bit_decoder_param_select[2]}}, 1'b0}) | {6{1'b0}}) | {1'b0, {3{start_bit_decoder_param_select[4]}}, 1'b0, start_bit_decoder_param_select[4]}) | {1'b0, {4{start_bit_decoder_param_select[5]}}, 1'b0}) | {6{1'b0}}) | {1'b0, {2{start_bit_decoder_param_select[7]}}, {3{1'b0}}}) | {6{1'b0}}) | {1'b0, {2{start_bit_decoder_param_select[9]}}, 1'b0, start_bit_decoder_param_select[9], 1'b0}) | {1'b0, {2{start_bit_decoder_param_select[10]}}, {3{1'b0}}}) | {6{1'b0}}) | {1'b0, {2{start_bit_decoder_param_select[12]}}, 1'b0, start_bit_decoder_param_select[12], 1'b0}) | {start_bit_decoder_param_select[13], {2{1'b0}}, start_bit_decoder_param_select[13], 1'b0, start_bit_decoder_param_select[13]}) | {6{1'b0}}) | {start_bit_decoder_param_select[15], {3{1'b0}}, {2{start_bit_decoder_param_select[15]}}}) | {{2{1'b0}}, {2{start_bit_decoder_param_select[16]}}, {2{1'b0}}}) | {start_bit_decoder_param_select[17], {2{1'b0}}, start_bit_decoder_param_select[17], {2{1'b0}}}) | {start_bit_decoder_param_select[18], {2{1'b0}}, start_bit_decoder_param_select[18], 1'b0, start_bit_decoder_param_select[18]}) | {6{1'b0}}) | {start_bit_decoder_param_select[20], {3{1'b0}}, {2{start_bit_decoder_param_select[20]}}}) | {{2{1'b0}}, {2{start_bit_decoder_param_select[21]}}, {2{1'b0}}}) | {start_bit_decoder_param_select[22], {2{1'b0}}, start_bit_decoder_param_select[22], {2{1'b0}}}),
		start_bit_decoder_param_select = param_decoder_select,
		w4w = read_source_c3,
		w53w = (wire_cntr5_q ^ bit_counter_param_start),
		w83w = (wire_cntr6_q ^ width_counter_param_width),
		width_counter_all_done = (((((~ wire_cntr6_q[0]) & (~ wire_cntr6_q[1])) & wire_cntr6_q[2]) & wire_cntr6_q[3]) & wire_cntr6_q[4]),
		width_counter_clear = (rsource_update_done | wsource_update_done),
		width_counter_enable = ((read_data | write_data) | read_post),
		width_counter_param_width = width_decoder_out,
		width_counter_param_width_match = (((((~ w83w[0]) & (~ w83w[1])) & (~ w83w[2])) & (~ w83w[3])) & (~ w83w[4])),
		width_decoder_out = (((((((((((((((((((((({{3{1'b0}}, width_decoder_param_select[0], 1'b0} | {{2{width_decoder_param_select[1]}}, {3{1'b0}}}) | {{3{1'b0}}, width_decoder_param_select[2], 1'b0}) | {{3{width_decoder_param_select[3]}}, 1'b0, width_decoder_param_select[3]}) | {{4{1'b0}}, width_decoder_param_select[4]}) | {{3{1'b0}}, width_decoder_param_select[5], 1'b0}) | {{2{width_decoder_param_select[6]}}, {3{1'b0}}}) | {{3{1'b0}}, width_decoder_param_select[7], 1'b0}) | {{2{width_decoder_param_select[8]}}, {3{1'b0}}}) | {{2{1'b0}}, width_decoder_param_select[9], 1'b0, width_decoder_param_select[9]}) | {{3{1'b0}}, width_decoder_param_select[10], 1'b0}) | {{2{width_decoder_param_select[11]}}, {3{1'b0}}}) | {{2{1'b0}}, width_decoder_param_select[12], 1'b0, width_decoder_param_select[12]}) | {{4{1'b0}}, width_decoder_param_select[13]}) | {1'b0, {2{width_decoder_param_select[14]}}, {2{1'b0}}}) | {{4{1'b0}}, width_decoder_param_select[15]}) | {width_decoder_param_select[16], 1'b0, {2{width_decoder_param_select[16]}}, 1'b0}) | {{4{1'b0}}, width_decoder_param_select[17]}) | {{4{1'b0}}, width_decoder_param_select[18]}) | {1'b0, {2{width_decoder_param_select[19]}}, {2{1'b0}}}) | {{4{1'b0}}, width_decoder_param_select[20]}) | {width_decoder_param_select[21], 1'b0, {2{width_decoder_param_select[21]}}, 1'b0}) | {{4{1'b0}}, width_decoder_param_select[22]}),
		width_decoder_param_select = param_decoder_select,
		write_data = write_data_state,
		write_init = write_init_state,
		write_init_counter = write_init_counter_state,
		write_load = write_load_state,
		write_param_c3 = (write_param & st_v0),
		write_post_data = write_post_data_state,
		write_pre_data = write_pre_data_state,
		write_source_update = write_source_update_state,
		write_wait = write_wait_state,
		wsource_state_par_ini = {write_param_c3, {2{global_gnd}}},
		wsource_update_done = dffe3a0[0:0];
endmodule //altera_remote_update_core
//VALID FILE
