//
// FPGA reset control
//
// Interface with and control of the internal FPGA reset logic.
//
// Altera Cyclone IV E Remote Update block (cycloneiv_rublock):
//
// This block is a primitive, but there doesn't seem to be any
// matching megafunction, except for the remote upgrade IP which
// uses the on-chip active serial controller(?) and generally does
// way more than we want.
//
// See the "Dedicated Remote System Upgrade Circuitry" section of the
// Remote System Upgrade chapter (vol 1, chapter 8) of the Cyclone IV
// manual.
//
// A refinement of this would be to allow shifting in a new boot address;
// see the MAX 10 Configuration User Guide. for low-level protocol details
// and the above reference for higher level protocol.
//
// At some point the Altera remote configuration IP is pretty much
// what's needed anyway, though.
//
module fpgarst
  (
   input rst_n,
   input clk,
   input reconfig
   );

   // The internal primitive connecting to hard logic;
   // ru stands for "remote update block"
   cycloneive_rublock ru
     (
      .clk       ( clk ),	// Is this even needed?
      .rconfig   ( reconfig ),	// Start reconfiguration
      .rsttimer  ( 1'b0 ),	// Don't reset the timer
      .regin     ( 1'bx ),	// Shift register data in
      .regout	 ( ),		// Shift register data out
      .captnupdt ( 1'b0 ),	// Capture/update#
      .shiftnld  ( 1'b0 )	// Shift/load# shift register
      );
endmodule // fpgarst
