module bypass (
	       input	   clock_in,
	       input	   rtc_32khz,
	       input	   board_id,

	       input	   spi_clk,
	       output	   spi_miso,
	       input	   spi_mosi,
	       input	   spi_cs_esp_n,
	       output	   esp_int,
	       output      spi_cs_flash_n, // Really just a GPIO on ESP32

	       output	   flash_cs_n,
	       output	   flash_sck,
	       inout [1:0] flash_io,

	       output	   abc_host_v1,
	       output	   abc_host_v12,
	       output	   abc_d_oe,

	       output	   abc_int800_x,
	       output	   abc_int80_x,
	       output	   abc_nmi_x,
	       output	   abc_rdy_x,
	       output	   abc_resin_x,
	       output	   abc_xm_x,

	       output	   led_0,
	       output	   led_1_v1,
	       output	   led_1_v2,
	       output	   led_2
	       );

   wire			   v1 = board_id;  // High = v1
   wire			   v2 = ~board_id; // Low = v2

   wire [2:0]		   led;

   assign led_0         = led[0];
   assign led_1_v1      = v1 ? led[1] : 1'bz;
   assign led_1_v2      = v2 ? led[1] : 1'bz;
   assign led_2         = led[2];

   assign flash_sck     = spi_clk;
   assign flash_io[0]   = spi_mosi;
   assign flash_io[1]   = 1'bz;
   assign spi_miso      = flash_io[1];
   assign flash_cs_n    = spi_cs_esp_n;

   assign esp_int        = 1'b0;	// Signal FPGA ready
   assign spi_cs_flash_n = board_id;

   assign abc_host_v1   = v1 ? 1'b0 : 1'bz;
   assign abc_host_v12  = 1'b0;
   assign abc_d_oe      = 1'b0;

   assign abc_int800_x = v1 ? 1'b0 : 1'bz;
   assign abc_int80_x  = v1 ? 1'b0 : 1'bz;
   assign abc_nmi_x    = v1 ? 1'b0 : 1'bz;
   assign abc_rdy_x    = v1 ? 1'b0 : 1'bz;
   assign abc_resin_x  = v1 ? 1'b0 : 1'bz;
   assign abc_xm_x     = v1 ? 1'b0 : 1'bz;
   assign abc_int800_x = v1 ? 1'b0 : 1'bz;


   reg [12:0]		   blink;
   always @(negedge rtc_32khz)
     blink <= blink + 1'b1;

   assign led = {3{blink[12]}};
endmodule // bypass
