spirom: revert uploader to arbitrary 8*n-byte bursts

Go back to allowing any burst size that is a multiple of 8 and doesn't
cross bank boundaries, as long as no other user requests access to the
memory.

fpga/output_files/max80.map

@@ -11,7 +11,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 Notes:
 
-- Data checksum for this conversion is 0xF376AD53
+- Data checksum for this conversion is 0xF3795A1E
 
 - All the addresses in this file are byte addresses
 

fpga/sdram.sv

@@ -522,7 +522,7 @@ module sdram
 		 // Streamable write from flash ROM
 		 dram_d      <= wd2;
 		 dram_a[10]  <= 1'b0;  // No auto precharge/precharge one bank
-		 dram_a[8:0] <= { a2[9:2], 1'b0 };
+		 dram_a[8:0] <= a2[9:1];
 
 		 case (op_cycle)
 		   0: begin
@@ -541,9 +541,8 @@ module sdram
 		   end
 		   4: begin
 		      dram_cmd  <= cmd_wr;
-		      if (~&dram_a[3:2] |
-			  (1'b0 & wrq2_more &
-			  ~(rrq0|wrq0|rrq1|wrq1|(|rfsh_prio)|(&dram_a[8:2]))))
+		      if (wrq2_more &
+			  ~(rrq0|wrq0|rrq1|wrq1|(|rfsh_prio)|(&dram_a[8:2])))
 			begin
 			   // Burst can continue
 			   wacc2       <= 1'b1;
@@ -556,14 +555,14 @@ module sdram
 		   7: begin
 		      // tWR completed
 		      dram_cmd    <= cmd_pre;
-		      dram_dqm    <= 2'b11; // This shouldn't be necessary?!
+		      dram_dqm    <= 2'b11;
 		   end
 		   8: begin
-		      dram_dqm    <= 2'b11; // This shouldn't be necessary?!
+		      dram_dqm    <= 2'b11;
 		   end
 		   9: begin
 		      // tRP will be complete in the next cycle
-		      dram_dqm    <= 2'b11; // This shouldn't be necessary?!
+		      dram_dqm    <= 2'b11;
 		      state <= st_idle;
 		   end
 		 endcase // case (op_cycle)

fpga/spirom.sv

@@ -84,8 +84,8 @@ module spirom (
        end
      else
        begin
-	  wrq[0] <= rdusedw >= 9'd16;  //  4*2 =  8 bytes min available
-	  wrq[1] <= rdusedw >= 9'd32; // 12*2 = 24 bytes min available
+	  wrq[0] <= rdusedw >= 9'd4; // 4*2 =  8 bytes min available
+	  wrq[1] <= rdusedw >= 9'd8; // 8*2 = 16 bytes min available
        end
 
    reg [24:1] waddr_q;

fw/boot.mif

@@ -1051,8 +1051,8 @@ CONTENT BEGIN
 414 : 2074634F;
 415 : 32203420;
 416 : 20313230;
-417 : 323A3030;
-418 : 33333A37;
+417 : 333A3030;
+418 : 30353A32;
 419 : 000A0A0D;
 41A : 2B302D23;
 41B : 00000020;

fw/hello.c

@@ -45,7 +45,7 @@ static void test_sdram(void)
     uint32_t start_time = rdtime();
     uint32_t w = 0;
     uint32_t n;
-    
+
     con_printf("Testing SDRAM from 0x%08x to 0x%08x, stride 0x%08x...\r\n",
 	       SDRAM_ADDR, SDRAM_END, stride);
 
@@ -65,12 +65,12 @@ static void test_sdram(void)
 	    CONSOLE = err_char;
 	    err_char = '-';
 	}
-	
+
 	w = (w + stride) & SDRAM_MASK;
     }
 
     con_puts("\r\nReading back to check for aliases...\r\n");
-	
+
     rate_limit = ERROR_RATELIMIT;
     for (n = 1, w = 0; n <= sdram_words; n++) {
 	uint32_t a = w + SDRAM_ADDR;
@@ -115,7 +115,7 @@ void main(void)
 	/* wait */;
 
     done = rdtime();
-    
+
     con_puts(hello);
 
     con_printf("This is loop: %u\n", loops++);
@@ -147,7 +147,7 @@ void main(void)
     }
 
     test_sdram();
-    
+
     p = (uint32_t *)SDRAM_ADDR;
     for (unsigned int w = 0; w < words; w++)
 	*p++ = 0xdeadbeef;
@@ -158,4 +158,3 @@ void main(void)
     while ( 1 )
       RESET_CMD = 1;
 }
-