hack: binary counter on ESP pins to test connectivity

fpga/max80.sv

@@ -447,11 +447,6 @@ module max80 (
 		);
 
 
-   // ESP32
-   assign spi_cs_flash_n = 1'bz;
-   assign esp_io0  = 1'b1;	 // If pulled down on reset, ESP32 will enter
-				 // firmware download mode
-
    // I2C
    assign i2c_scl = 1'bz;
    assign i2c_sda = 1'bz;
@@ -726,33 +721,6 @@ module max80 (
 	   );
    assign sd_dat[2:1] = 2'bzz;
 
-   // SPI bus to ESP32; using the sdcard IP as a SPI master for now at
-   // least...
-   sdcard #(
-	    .with_irq_mask ( 8'b0000_0101 ),
-	    .with_crc7     ( 1'b0 ),
-	    .with_crc16    ( 1'b0 )
-	    )
-   esp (
-	.rst_n    ( rst_n ),
-
-	.clk      ( sys_clk ),
-	.sd_cs_n  ( spi_cs_esp_n ),
-	.sd_di    ( spi_mosi ),
-	.sd_sclk  ( spi_clk ),
-	.sd_do    ( spi_miso ),
-	.sd_cd_n  ( 1'b0 ),
-	.sd_irq_n ( esp_int ),
-
-	.wdata  ( cpu_mem_wdata ),
-	.rdata  ( iodev_rdata_esp ),
-	.valid  ( iodev_valid_esp ),
-	.wstrb  ( cpu_mem_wstrb ),
-	.addr   ( cpu_mem_addr[6:2] ),
-	.wait_n ( iodev_wait_n_esp ),
-	.irq	( iodev_irq_esp )
-	);
-
    // System local clock (not an RTC, but settable from one)
    // Also provides a periodic interrupt (set to 32 Hz)
    // XXX: the RTC 32 kHz signal is missing a pull-up,
@@ -788,6 +756,54 @@ module max80 (
 		      .periodic ( iodev_irq_sysclock )
 		      );
 
+   // SPI bus to ESP32; using the sdcard IP as a SPI master for now at
+   // least...
+`ifdef REALLY_ESP32
+   // ESP32
+   assign spi_cs_flash_n = 1'bz;
+   assign esp_io0  = 1'b1;	 // If pulled down on reset, ESP32 will enter
+				 // firmware download mode
+
+   sdcard #(
+	    .with_irq_mask ( 8'b0000_0101 ),
+	    .with_crc7     ( 1'b0 ),
+	    .with_crc16    ( 1'b0 )
+	    )
+   esp (
+	.rst_n    ( rst_n ),
+
+	.clk      ( sys_clk ),
+	.sd_cs_n  ( spi_cs_esp_n ),
+	.sd_di    ( spi_mosi ),
+	.sd_sclk  ( spi_clk ),
+	.sd_do    ( spi_miso ),
+	.sd_cd_n  ( 1'b0 ),
+	.sd_irq_n ( esp_int ),
+
+	.wdata  ( cpu_mem_wdata ),
+	.rdata  ( iodev_rdata_esp ),
+	.valid  ( iodev_valid_esp ),
+	.wstrb  ( cpu_mem_wstrb ),
+	.addr   ( cpu_mem_addr[6:2] ),
+	.wait_n ( iodev_wait_n_esp ),
+	.irq	( iodev_irq_esp )
+	);
+`else // !`ifdef REALLY_ESP32
+   reg [5:0] esp_ctr;
+   
+   always @(posedge ctr_32khz)
+     esp_ctr <= esp_ctr + 1'b1;
+
+   assign spi_clk        = esp_ctr[0];
+   assign spi_mosi       = esp_ctr[1];
+   assign spi_miso       = esp_ctr[2];
+   assign spi_cs_flash_n = esp_ctr[3]; // IO01
+   assign spi_cs_esp_n   = esp_ctr[4]; // IO10
+   assign spi_int        = esp_ctr[5]; // IO09
+   assign esp_io0        = 1'b1;
+
+`endif
+
    //
    // Registering of I/O data and handling of iodev_mem_ready
    //