USB: fix data loss due to bad rewind on CRC error

On a CRC error, it is necessary to rewind the data FIFO to the
beginning of the packet, not just to the previous data item.

Design a new FIFO IP to handle that.

Add a hack to deliberately corrupt the CRC to test this.

Move max packet handling into the device core, where it belongs. This
simplifies code elsewhere, too.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

fpga/dcpktfifo.sv

@@ -0,0 +1,182 @@
+//
+// dcpktfifo.sv
+//
+// Dual-clock RAM-based FIFO with transaction support (commit/abort)
+//
+
+// Parametric synchronous RAM module, dual clock,
+// one read and one write port; output data registered
+module dcqram
+#(
+  parameter wbits,		// log2(size in words)
+  parameter width = 8
+)
+   (
+    input  wclk,
+    input  wstb,
+    input  [wbits-1:0] waddr,
+    input  [width-1:0] wdata,
+
+    input  rclk,
+    input  [wbits-1:0] raddr,
+    output [width-1:0] rdata
+    );
+
+`ifdef ALTERA_RESERVED_QIS
+   (* ramstyle = "no_rw_check" *)
+`endif
+   reg [width-1:0]     mem[0:(1 << wbits)-1];
+
+   always @(posedge wclk)
+     if (wstb)
+       mem[waddr] <= wdata;
+
+   reg [wbits-1:0]     raddr_q;
+   reg [width-1:0]     rdata_q;
+
+   assign rdata = rdata_q;
+
+   always @(posedge rclk)
+     begin
+	raddr_q <= raddr;
+	rdata_q <= mem[raddr_q];
+     end
+endmodule // dcqram
+
+module dcpktfifo
+  #(
+    parameter	    wbits     = 10,
+    parameter	    width     = 8,
+    parameter [0:0] wtrans    = 1'b1, // Support transactions on write side
+    parameter [0:0] rtrans    = 1'b1  // Support transactions on read side
+    )
+   (
+    input		   rst_n,
+
+    input		   wclk,
+    input		   wstb,
+    input		   wcommit,
+    input		   wabort,
+    input [width-1:0]	   wdata,
+    output reg [wbits-1:0] wnfree,
+    output reg		   wempty,
+    output reg		   wfull,
+
+    input		   rclk,
+    input		   rstb,
+    input		   rcommit,
+    input		   rabort,
+    output [width-1:0]	   rdata,
+    output reg [wbits-1:0] rnavail,
+    output reg		   rempty,
+    output reg		   rlast,
+    output reg		   rfull
+    );
+
+   reg [wbits-1:0]  wtaddr;	// Transient write address
+   reg [wbits-1:0]  wcaddr;	// Committed write address
+   wire [wbits-1:0] w_rcaddr;	// rcaddr latched in the wclk domain
+
+   wire		    wcommit_w = wtrans ? wcommit : 1'b1;
+   wire		    wabort_w  = wtrans ? wabort : 1'b0;
+   wire [wbits-1:0] wcaddr_w  = wtrans ? wcaddr : wtaddr;
+
+   wire		    wstb_w = wstb & ~wfull;
+   wire [wbits-1:0] wnused = wtaddr + wstb_w - w_rcaddr;
+
+   always @(negedge rst_n or posedge wclk)
+     if (~rst_n)
+       begin
+	  wtaddr   <= 'b0;
+	  wcaddr   <= 'b0;
+	  wempty   <= 1'b1;
+	  wfull    <= 1'b0;
+       end
+     else
+       begin
+	  if (wabort_w)
+	    wtaddr <= wcaddr_w;
+	  else
+	    begin
+	       wtaddr <= wtaddr + wstb_w;
+	       if (wcommit_w)
+		 wcaddr <= wtaddr + wstb_w;
+	    end
+
+	  wnfree <= ~wnused;
+	  wempty <= ~|wnused;
+	  wfull  <= &wnused;
+       end // else: !if(~rst_n)
+
+   reg [wbits-1:0]  rtaddr;	// Transient read address
+   reg [wbits-1:0]  rcaddr;	// Committed read address
+   wire [wbits-1:0] r_wcaddr;	// wcaddr latched in the rclk domain
+
+   wire		    rcommit_w = rtrans ? rcommit : 1'b1;
+   wire		    rabort_w  = rtrans ? rabort : 1'b0;
+   wire [wbits-1:0] rcaddr_w  = rtrans ? rcaddr : rtaddr;
+
+   wire		    rstb_w    = rstb & ~rempty;
+   wire [wbits-1:0] rnused    = r_wcaddr - (rtaddr + rstb_w);
+
+   always @(negedge rst_n or posedge rclk)
+     if (~rst_n)
+       begin
+	  rtaddr  <= 'b0;
+	  rcaddr  <= 'b0;
+	  rnavail <= 'b0;
+	  rempty  <= 1'b1;
+	  rlast   <= 1'b1;
+	  rfull   <= 1'b0;
+       end
+     else
+       begin
+	  if (rabort_w)
+	    rtaddr <= rcaddr_w;
+	  else
+	    begin
+	       rtaddr <= rtaddr + rstb_w;
+	       if (rcommit_w)
+		 rcaddr <= rtaddr + rstb_w;
+	    end // else: !if(rabort_w)
+
+	  rnavail <= rnused;
+	  rempty  <= ~|rnused;
+	  rlast   <= rnused < 2;
+	  rfull   <= &rnused;
+       end // else: !if(~rst_n)
+
+   // Address pointer synchronizers.
+
+   synchronizer #(.width(wbits))
+   syncrcaddr (
+	       .rst_n (rst_n),
+	       .clk   (wclk),
+	       .d     (rcaddr_w),
+	       .q     (w_rcaddr)
+	       );
+
+   synchronizer #(.width(wbits))
+   syncwcaddr (
+	       .rst_n (rst_n),
+	       .clk   (rclk),
+	       .d     (wcaddr_w),
+	       .q     (r_wcaddr)
+	       );
+
+   //
+   // Memory array
+   //
+   dcqram #(.wbits(wbits), .width(width))
+   ram (
+	.wclk  (wclk),
+	.wstb  (wstb),
+	.waddr (wtaddr),
+	.wdata (wdata),
+
+	.rclk  (rclk),
+	.raddr (rtaddr),
+	.rdata (rdata)
+	);
+
+endmodule // dcpktfifo

fpga/ip/cdc_rxfifo.qip

@@ -1,5 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "FIFO"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cdc_rxfifo.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cdc_rxfifo_bb.v"]

fpga/ip/cdc_rxfifo.v

@@ -1,204 +0,0 @@
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: dcfifo 
-
-// ============================================================
-// File Name: cdc_rxfifo.v
-// Megafunction Name(s):
-// 			dcfifo
-//
-// Simulation Library Files(s):
-// 			
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and any partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details, at
-//https://fpgasoftware.intel.com/eula.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module cdc_rxfifo (
-	aclr,
-	data,
-	rdclk,
-	rdreq,
-	wrclk,
-	wrreq,
-	q,
-	rdempty,
-	rdfull,
-	rdusedw,
-	wrempty,
-	wrfull,
-	wrusedw);
-
-	input	  aclr;
-	input	[7:0]  data;
-	input	  rdclk;
-	input	  rdreq;
-	input	  wrclk;
-	input	  wrreq;
-	output	[7:0]  q;
-	output	  rdempty;
-	output	  rdfull;
-	output	[9:0]  rdusedw;
-	output	  wrempty;
-	output	  wrfull;
-	output	[9:0]  wrusedw;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0	  aclr;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [7:0] sub_wire0;
-	wire  sub_wire1;
-	wire  sub_wire2;
-	wire [9:0] sub_wire3;
-	wire  sub_wire4;
-	wire  sub_wire5;
-	wire [9:0] sub_wire6;
-	wire [7:0] q = sub_wire0[7:0];
-	wire  rdempty = sub_wire1;
-	wire  rdfull = sub_wire2;
-	wire [9:0] rdusedw = sub_wire3[9:0];
-	wire  wrempty = sub_wire4;
-	wire  wrfull = sub_wire5;
-	wire [9:0] wrusedw = sub_wire6[9:0];
-
-	dcfifo	dcfifo_component (
-				.aclr (aclr),
-				.data (data),
-				.rdclk (rdclk),
-				.rdreq (rdreq),
-				.wrclk (wrclk),
-				.wrreq (wrreq),
-				.q (sub_wire0),
-				.rdempty (sub_wire1),
-				.rdfull (sub_wire2),
-				.rdusedw (sub_wire3),
-				.wrempty (sub_wire4),
-				.wrfull (sub_wire5),
-				.wrusedw (sub_wire6),
-				.eccstatus ());
-	defparam
-		dcfifo_component.intended_device_family = "Cyclone IV E",
-		dcfifo_component.lpm_numwords = 1024,
-		dcfifo_component.lpm_showahead = "ON",
-		dcfifo_component.lpm_type = "dcfifo",
-		dcfifo_component.lpm_width = 8,
-		dcfifo_component.lpm_widthu = 10,
-		dcfifo_component.overflow_checking = "ON",
-		dcfifo_component.rdsync_delaypipe = 5,
-		dcfifo_component.read_aclr_synch = "OFF",
-		dcfifo_component.underflow_checking = "ON",
-		dcfifo_component.use_eab = "ON",
-		dcfifo_component.write_aclr_synch = "ON",
-		dcfifo_component.wrsync_delaypipe = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "1024"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "8"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "8"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "1"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
-// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]"
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
-// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_rxfifo_bb.v TRUE

fpga/ip/cdc_txfifo.qip

@@ -1,5 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "FIFO"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
-set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cdc_txfifo.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "cdc_txfifo_bb.v"]

fpga/ip/cdc_txfifo.v

@@ -1,204 +0,0 @@
-// megafunction wizard: %FIFO%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: dcfifo 
-
-// ============================================================
-// File Name: cdc_txfifo.v
-// Megafunction Name(s):
-// 			dcfifo
-//
-// Simulation Library Files(s):
-// 			
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-// ************************************************************
-
-
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
-//Your use of Intel Corporation's design tools, logic functions 
-//and other software and tools, and any partner logic 
-//functions, and any output files from any of the foregoing 
-//(including device programming or simulation files), and any 
-//associated documentation or information are expressly subject 
-//to the terms and conditions of the Intel Program License 
-//Subscription Agreement, the Intel Quartus Prime License Agreement,
-//the Intel FPGA IP License Agreement, or other applicable license
-//agreement, including, without limitation, that your use is for
-//the sole purpose of programming logic devices manufactured by
-//Intel and sold by Intel or its authorized distributors.  Please
-//refer to the applicable agreement for further details, at
-//https://fpgasoftware.intel.com/eula.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module cdc_txfifo (
-	aclr,
-	data,
-	rdclk,
-	rdreq,
-	wrclk,
-	wrreq,
-	q,
-	rdempty,
-	rdfull,
-	rdusedw,
-	wrempty,
-	wrfull,
-	wrusedw);
-
-	input	  aclr;
-	input	[7:0]  data;
-	input	  rdclk;
-	input	  rdreq;
-	input	  wrclk;
-	input	  wrreq;
-	output	[7:0]  q;
-	output	  rdempty;
-	output	  rdfull;
-	output	[9:0]  rdusedw;
-	output	  wrempty;
-	output	  wrfull;
-	output	[9:0]  wrusedw;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0	  aclr;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	wire [7:0] sub_wire0;
-	wire  sub_wire1;
-	wire  sub_wire2;
-	wire [9:0] sub_wire3;
-	wire  sub_wire4;
-	wire  sub_wire5;
-	wire [9:0] sub_wire6;
-	wire [7:0] q = sub_wire0[7:0];
-	wire  rdempty = sub_wire1;
-	wire  rdfull = sub_wire2;
-	wire [9:0] rdusedw = sub_wire3[9:0];
-	wire  wrempty = sub_wire4;
-	wire  wrfull = sub_wire5;
-	wire [9:0] wrusedw = sub_wire6[9:0];
-
-	dcfifo	dcfifo_component (
-				.aclr (aclr),
-				.data (data),
-				.rdclk (rdclk),
-				.rdreq (rdreq),
-				.wrclk (wrclk),
-				.wrreq (wrreq),
-				.q (sub_wire0),
-				.rdempty (sub_wire1),
-				.rdfull (sub_wire2),
-				.rdusedw (sub_wire3),
-				.wrempty (sub_wire4),
-				.wrfull (sub_wire5),
-				.wrusedw (sub_wire6),
-				.eccstatus ());
-	defparam
-		dcfifo_component.intended_device_family = "Cyclone IV E",
-		dcfifo_component.lpm_numwords = 1024,
-		dcfifo_component.lpm_showahead = "OFF",
-		dcfifo_component.lpm_type = "dcfifo",
-		dcfifo_component.lpm_width = 8,
-		dcfifo_component.lpm_widthu = 10,
-		dcfifo_component.overflow_checking = "ON",
-		dcfifo_component.rdsync_delaypipe = 5,
-		dcfifo_component.read_aclr_synch = "ON",
-		dcfifo_component.underflow_checking = "ON",
-		dcfifo_component.use_eab = "ON",
-		dcfifo_component.write_aclr_synch = "OFF",
-		dcfifo_component.wrsync_delaypipe = 5;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "1024"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "2"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "8"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-// Retrieval info: PRIVATE: output_width NUMERIC "8"
-// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: rsFull NUMERIC "1"
-// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
-// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
-// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
-// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]"
-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
-// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
-// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cdc_txfifo_bb.v TRUE

fpga/max80.qpf

@@ -19,12 +19,12 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 01:24:01  September 02, 2022
+# Date created = 00:52:28  December 19, 2022
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "01:24:01  September 02, 2022"
+DATE = "00:52:28  December 19, 2022"
 
 # Revisions
 

fpga/max80.qsf

@@ -211,6 +211,7 @@ set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_defs.v
 set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_crc16.v
 set_global_assignment -name SYSTEMVERILOG_FILE usb/usb.sv
 set_global_assignment -name VERILOG_INCLUDE_FILE usb/usbparam.vh
+set_global_assignment -name SYSTEMVERILOG_FILE dcpktfifo.sv
 set_global_assignment -name VERILOG_FILE ip/statusram.v
 set_global_assignment -name VERILOG_INCLUDE_FILE iodevs.vh
 set_global_assignment -name SYSTEMVERILOG_FILE serial.sv
@@ -242,10 +243,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 set_global_assignment -name VERILOG_FILE ip/fifo.v
 set_global_assignment -name VERILOG_FILE ip/ddufifo.v
-set_global_assignment -name VERILOG_FILE ip/cdc_txfifo.v
-set_global_assignment -name VERILOG_FILE ip/cdc_rxfifo.v
-set_global_assignment -name QIP_FILE ip/cdc_txfifo.qip
-set_global_assignment -name QIP_FILE ip/cdc_rxfifo.qip
 set_global_assignment -name SYSTEMVERILOG_FILE vjtag_max80.sv
 set_global_assignment -name VERILOG_FILE ip/vjtag/synthesis/vjtag.v
 set_global_assignment -name QIP_FILE ip/vjtag/synthesis/vjtag.qip

fpga/usb/usb_serial/src_v/ulpi_wrapper.v

@@ -9,26 +9,26 @@
 //                         License: LGPL
 //-----------------------------------------------------------------
 //
-// This source file may be used and distributed without         
-// restriction provided that this copyright statement is not    
-// removed from the file and that any derivative work contains  
-// the original copyright notice and the associated disclaimer. 
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
 //
-// This source file is free software; you can redistribute it   
-// and/or modify it under the terms of the GNU Lesser General   
-// Public License as published by the Free Software Foundation; 
-// either version 2.1 of the License, or (at your option) any   
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
 // later version.
 //
-// This source is distributed in the hope that it will be       
-// useful, but WITHOUT ANY WARRANTY; without even the implied   
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-// PURPOSE.  See the GNU Lesser General Public License for more 
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE.  See the GNU Lesser General Public License for more
 // details.
 //
-// You should have received a copy of the GNU Lesser General    
-// Public License along with this source; if not, write to the 
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
 // Boston, MA  02111-1307  USA
 //-----------------------------------------------------------------
 
@@ -107,8 +107,8 @@ reg         mode_write_q;
 
 // Detect register write completion
 wire mode_complete_w = (state_q == STATE_REG &&
-                        mode_write_q         && 
-                        ulpi_nxt_i           && 
+                        mode_write_q         &&
+                        ulpi_nxt_i           &&
                         !ulpi_dir_i);           // Not interrupted by a Rx
 
 always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
@@ -147,8 +147,8 @@ reg otg_write_q;
 
 // Detect register write completion
 wire otg_complete_w  = (state_q == STATE_REG &&
-                        otg_write_q         && 
-                        ulpi_nxt_i           && 
+                        otg_write_q         &&
+                        ulpi_nxt_i           &&
                         !ulpi_dir_i);           // Not interrupted by a Rx
 
 always @ (posedge ulpi_clk60_i or posedge ulpi_rst_i)
@@ -221,7 +221,7 @@ begin
     tx_valid_q[1]  <= 1'b0;
     tx_wr_idx_q    <= 1'b0;
     tx_rd_idx_q    <= 1'b0;
-end    
+end
 else
 begin
     // Push
@@ -329,7 +329,7 @@ begin
                 utmi_rxactive_q <= 1'b0;
                 utmi_rxerror_q  <= 1'b0;
             end
-            2'b01: 
+            2'b01:
             begin
                 utmi_rxactive_q <= 1'b1;
                 utmi_rxerror_q  <= 1'b0;
@@ -355,7 +355,7 @@ begin
         // Output
         //-----------------------------------------------------------------
         else if (!ulpi_dir_i)
-        begin        
+        begin
             // IDLE: Pending mode update
             if ((state_q == STATE_IDLE) && mode_update_q)
             begin

fpga/usb/usb_serial/src_v/usb_cdc_core.sv

@@ -126,97 +126,86 @@ module usb_cdc_channel
 
    wire		        txempty;
    wire		        txfull;
-   wire [fifo_bits-1:0]  txused;
-   wire [water_bits-1:0] txused_msb = txused[fifo_bits-1:fifo_bits-water_bits];
+   wire [fifo_bits-1:0]  txfree;
+   wire [water_bits-1:0] txused_msb = ~txfree[fifo_bits-1:fifo_bits-water_bits];
    wire		        inport_empty_w;
-   reg			inport_valid_q;
+   wire		        inport_last_w;
    reg			flush_tx_data;
 
-   // cdc_txfifo does not have lookahead data output,
-   // aclr assumed synchronous with wrclk
-   cdc_txfifo txfifo (
-		    .aclr    ( flush_tx_data ),
-
-		    .wrclk   ( sys_clk ),
-		    .data    ( cpu_wdata[7:0] ),
-		    .wrreq   ( fifo_access & ~fifo_access_q & cpu_wstrb[0] ),
-		    .wrempty ( txempty ),
-		    .wrfull  ( txfull ),
-		    .wrusedw ( txused ),
-
-		    .rdclk   ( clk_i ),
-		    .q       ( data_ep.d.tx_data ),
-		    .rdreq   ( inport_valid_q
-			       ? data_ep.u.tx_data_accept
-			       : ~inport_empty_w ),
-		    .rdempty ( inport_empty_w ),
-		    .rdfull  ( ),
-		    .rdusedw ( )
-		    );
+   dcpktfifo #(
+	       .wbits     ( fifo_bits ),
+	       .width     ( 8 ),
+	       .wtrans    ( 1'b0 ),
+	       .rtrans    ( 1'b1 )
+	       )
+   txfifo (
+	   .rst_n   ( ~flush_tx_data ),
+
+	   .wclk    ( sys_clk ),
+	   .wcommit ( ),
+	   .wabort  ( ),
+	   .wstb    ( fifo_access & ~fifo_access_q & cpu_wstrb[0] ),
+	   .wdata   ( cpu_wdata[7:0] ),
+	   .wnfree  ( txfree ),
+	   .wempty  ( txempty ),
+	   .wfull   ( txfull ),
+
+	   .rclk    ( clk_i ),
+	   .rdata   ( data_ep.d.tx_data ),
+	   .rstb    ( data_ep.u.tx_data_accept ),
+	   .rcommit ( data_ep.u.tx_ack ),
+	   .rabort  ( data_ep.u.tx_init ),
+	   .rnavail ( ),
+	   .rempty  ( inport_empty_w ),
+	   .rlast   ( inport_last_w )
+	   );
 
    // If RTS is not asserted, suspend data transmit
    wire inport_has_data = ~inport_empty_w & inport_rts_w;
 
-   always @(posedge clk_i or posedge rst_i)
-     if (rst_i)
-       inport_valid_q <= 1'b0;
-     else if ( inport_has_data )
-       inport_valid_q <= 1'b1;
-     else if ( data_ep.u.tx_data_accept )
-       inport_valid_q <= 1'b0;
-
-   assign data_ep.d.tx_data_valid = inport_valid_q;
-   assign data_ep.d.tx_ready      = inport_valid_q;
-   assign data_ep.d.tx_data_strb  = inport_valid_q;
-
-   // Must terminate a transfer at the max packet size
-   reg [packet_bits-1:0] inport_cnt_q;
-   wire			 inport_last_w = ~inport_has_data | &inport_cnt_q;
-
-   always @(posedge clk_i or posedge rst_i)
-     if (rst_i)
-       inport_cnt_q <= 'd0;
-     else if (inport_last_w & data_ep.u.tx_data_accept)
-       inport_cnt_q <= 'd0;
-     else if (inport_valid_q & data_ep.u.tx_data_accept)
-       inport_cnt_q <= inport_cnt_q + 1'b1;
-
-   assign data_ep.d.tx_data_last = inport_last_w;
+   assign data_ep.d.tx_data_valid = inport_has_data;
+   assign data_ep.d.tx_ready      = inport_has_data;
+   assign data_ep.d.tx_data_strb  = inport_has_data;
+   assign data_ep.d.tx_data_last  = inport_last_w;
 
    wire [7:0]	        rdata_fifo;
    wire		        rxempty;
-   wire		        rxfull;
    reg			flush_rx_data;
    wire [fifo_bits-1:0] rxused;
+   wire			rxfull = &rxused;
    wire [water_bits-1:0] rxused_msb = rxused[fifo_bits-1:fifo_bits-water_bits];
-   wire [fifo_bits-1:0] outport_used_w;
+   wire [fifo_bits-1:0] outport_free_w;
    wire			outport_full_w;
 
    wire			outport_valid_w = data_ep.u.rx_valid & data_ep.uc.rx_strb;
 
    // Should be space for a max-sized packet before allowing input
-   assign data_ep.d.rx_space = ~outport_full_w &
-			       (outport_used_w < fifo_size - packet_size);
-
-   // cdc_rxfifo has lookahead data output, aclr assumed synchronous with
-   // rdclk
-   cdc_rxfifo rxfifo (
-		    .aclr    ( flush_rx_data ),
-
-		    .rdclk   ( sys_clk ),
-		    .q       ( rdata_fifo ),
-		    .rdreq   ( ~fifo_access & fifo_read_q ),
-		    .rdempty ( rxempty ),
-		    .rdfull  ( rxfull ),
-		    .rdusedw ( rxused ),
-
-		    .wrclk   ( clk_i ),
-		    .data    ( data_ep.uc.rx_data ),
-		    .wrreq   ( outport_valid_w ),
-		    .wrempty ( ),
-		    .wrfull  ( outport_full_w ),
-		    .wrusedw ( outport_used_w )
-		    );
+   assign data_ep.d.rx_space = (outport_free_w >= packet_size);
+
+   dcpktfifo #(
+	       .wbits     ( fifo_bits ),
+	       .width     ( 8 ),
+	       .wtrans    ( 1'b1 ),
+	       .rtrans    ( 1'b0 )
+	       )
+   rxfifo (
+	   .rst_n ( ~flush_rx_data ),
+
+	   .rclk    ( sys_clk ),
+	   .rdata   ( rdata_fifo ),
+	   .rstb    ( ~fifo_access & fifo_read_q ),
+	   .rempty  ( rxempty ),
+	   .rnavail ( rxused ),
+
+	   .wclk    ( clk_i ),
+	   .wdata   ( data_ep.uc.rx_data ),
+	   .wstb    ( outport_valid_w ),
+	   .wcommit ( data_ep.u.rx_ack ),
+	   .wabort  ( data_ep.u.rx_init ),
+	   .wempty  ( ),
+	   .wfull   ( outport_full_w ),
+	   .wnfree  ( outport_free_w )
+	   );
 
    // Queued data wakeup
    reg [1:0]		had_rxdata;
@@ -270,8 +259,8 @@ module usb_cdc_channel
 	  irq_mask      <= 16'b0;
 	  irq_pol       <= 16'b0;
 	  recv_break_q  <= 1'b0;
-	  flush_rx_data <= 1'b0;
-	  flush_tx_data <= 1'b0;
+	  flush_rx_data <= 1'b1;
+	  flush_tx_data <= 1'b1;
        end
      else
        begin
@@ -350,10 +339,13 @@ module usb_cdc_channel
      endcase // case (cpu_addr)
 
    // Channel configurations
-   assign data_ep.c.ep_num  = data_ep_num;
-   assign data_ep.c.ep_mask = 4'b1111;
-   assign intr_ep.c.ep_num  = intr_ep_num;
-   assign intr_ep.c.ep_mask = 4'b1111;
+   assign data_ep.c.ep_max_pkt    = 1'b1 << `USB_PACKET_BITS;
+   assign data_ep.c.ep_num        = data_ep_num;
+   assign data_ep.c.ep_mask       = 4'b1111;
+
+   assign intr_ep.c.ep_max_pkt    = 1'b1 << `USB_PACKET_BITS;
+   assign intr_ep.c.ep_num        = intr_ep_num;
+   assign intr_ep.c.ep_mask       = 4'b1111;
 
    // Data channel endpoint: unused signals
    assign data_ep.d.ep_iso        = 1'b0;
@@ -782,8 +774,9 @@ module usb_cdc_core
    reg       setup_data_q;
    reg       status_ready_q; // STATUS response received
 
-   assign usb_ep[0].c.ep_num   = 4'd0;
-   assign usb_ep[0].c.ep_mask  = 4'b1111;
+   assign usb_ep[0].c.ep_num     = 4'd0;
+   assign usb_ep[0].c.ep_max_pkt = 8;
+   assign usb_ep[0].c.ep_mask    = 4'b1111;
 
    assign usb_ep[0].d.rx_space = 1'b1;
 

fpga/usb/usb_serial/src_v/usb_desc_rom.v

@@ -9,26 +9,26 @@
 //                         License: LGPL
 //-----------------------------------------------------------------
 //
-// This source file may be used and distributed without         
-// restriction provided that this copyright statement is not    
-// removed from the file and that any derivative work contains  
-// the original copyright notice and the associated disclaimer. 
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
 //
-// This source file is free software; you can redistribute it   
-// and/or modify it under the terms of the GNU Lesser General   
-// Public License as published by the Free Software Foundation; 
-// either version 2.1 of the License, or (at your option) any   
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
 // later version.
 //
-// This source is distributed in the hope that it will be       
-// useful, but WITHOUT ANY WARRANTY; without even the implied   
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-// PURPOSE.  See the GNU Lesser General Public License for more 
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE.  See the GNU Lesser General Public License for more
 // details.
 //
-// You should have received a copy of the GNU Lesser General    
-// Public License along with this source; if not, write to the 
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
 // Boston, MA  02111-1307  USA
 //-----------------------------------------------------------------
 
@@ -57,7 +57,7 @@ begin
     8'd7: desc_rom_r = hs_i ? 8'h40 : 8'h08;
     8'd8: desc_rom_r = 8'h50;  // VID_L
     8'd9: desc_rom_r = 8'h1d;  // VID_H
-    8'd10: desc_rom_r = 8'h49; // PID_L 
+    8'd10: desc_rom_r = 8'h49; // PID_L
     8'd11: desc_rom_r = 8'h61; // PID_H
     8'd12: desc_rom_r = 8'h01;
     8'd13: desc_rom_r = 8'h01;

fpga/usb/usb_serial/src_v/usbf_crc16.v

@@ -9,26 +9,26 @@
 //                         License: LGPL
 //-----------------------------------------------------------------
 //
-// This source file may be used and distributed without         
-// restriction provided that this copyright statement is not    
-// removed from the file and that any derivative work contains  
-// the original copyright notice and the associated disclaimer. 
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
 //
-// This source file is free software; you can redistribute it   
-// and/or modify it under the terms of the GNU Lesser General   
-// Public License as published by the Free Software Foundation; 
-// either version 2.1 of the License, or (at your option) any   
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
 // later version.
 //
-// This source is distributed in the hope that it will be       
-// useful, but WITHOUT ANY WARRANTY; without even the implied   
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-// PURPOSE.  See the GNU Lesser General Public License for more 
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE.  See the GNU Lesser General Public License for more
 // details.
 //
-// You should have received a copy of the GNU Lesser General    
-// Public License along with this source; if not, write to the 
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
 // Boston, MA  02111-1307  USA
 //-----------------------------------------------------------------
 
@@ -51,25 +51,25 @@ module usbf_crc16
 //-----------------------------------------------------------------
 // Logic
 //-----------------------------------------------------------------
-assign crc_out_o[15] =    din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^ 
+assign crc_out_o[15] =    din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^ din_i[7] ^
                         crc_in_i[7] ^ crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
 assign crc_out_o[14] =    din_i[0] ^ din_i[1] ^ din_i[2] ^ din_i[3] ^ din_i[4] ^ din_i[5] ^ din_i[6] ^
                         crc_in_i[6] ^ crc_in_i[5] ^ crc_in_i[4] ^ crc_in_i[3] ^ crc_in_i[2] ^ crc_in_i[1] ^ crc_in_i[0];
-assign crc_out_o[13] =    din_i[6] ^ din_i[7] ^ 
+assign crc_out_o[13] =    din_i[6] ^ din_i[7] ^
                         crc_in_i[7] ^ crc_in_i[6];
-assign crc_out_o[12] =    din_i[5] ^ din_i[6] ^ 
+assign crc_out_o[12] =    din_i[5] ^ din_i[6] ^
                         crc_in_i[6] ^ crc_in_i[5];
-assign crc_out_o[11] =    din_i[4] ^ din_i[5] ^ 
+assign crc_out_o[11] =    din_i[4] ^ din_i[5] ^
                         crc_in_i[5] ^ crc_in_i[4];
-assign crc_out_o[10] =    din_i[3] ^ din_i[4] ^ 
+assign crc_out_o[10] =    din_i[3] ^ din_i[4] ^
                         crc_in_i[4] ^ crc_in_i[3];
-assign crc_out_o[9] =     din_i[2] ^ din_i[3] ^ 
+assign crc_out_o[9] =     din_i[2] ^ din_i[3] ^
                         crc_in_i[3] ^ crc_in_i[2];
-assign crc_out_o[8] =     din_i[1] ^ din_i[2] ^ 
+assign crc_out_o[8] =     din_i[1] ^ din_i[2] ^
                         crc_in_i[2] ^ crc_in_i[1];
-assign crc_out_o[7] =     din_i[0] ^ din_i[1] ^ 
+assign crc_out_o[7] =     din_i[0] ^ din_i[1] ^
                         crc_in_i[15] ^ crc_in_i[1] ^ crc_in_i[0];
-assign crc_out_o[6] =     din_i[0] ^ 
+assign crc_out_o[6] =     din_i[0] ^
                         crc_in_i[14] ^ crc_in_i[0];
 assign crc_out_o[5] =     crc_in_i[13];
 assign crc_out_o[4] =     crc_in_i[12];

fpga/usb/usb_serial/src_v/usbf_defs.v

@@ -9,26 +9,26 @@
 //                         License: LGPL
 //-----------------------------------------------------------------
 //
-// This source file may be used and distributed without         
-// restriction provided that this copyright statement is not    
-// removed from the file and that any derivative work contains  
-// the original copyright notice and the associated disclaimer. 
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
 //
-// This source file is free software; you can redistribute it   
-// and/or modify it under the terms of the GNU Lesser General   
-// Public License as published by the Free Software Foundation; 
-// either version 2.1 of the License, or (at your option) any   
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
 // later version.
 //
-// This source is distributed in the hope that it will be       
-// useful, but WITHOUT ANY WARRANTY; without even the implied   
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-// PURPOSE.  See the GNU Lesser General Public License for more 
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE.  See the GNU Lesser General Public License for more
 // details.
 //
-// You should have received a copy of the GNU Lesser General    
-// Public License along with this source; if not, write to the 
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
 // Boston, MA  02111-1307  USA
 //-----------------------------------------------------------------
 

fpga/usb/usb_serial/src_v/usbf_device_core.sv

@@ -36,11 +36,16 @@
 //                          Generated File
 //-----------------------------------------------------------------
 
+`include "../../usbparam.vh"
+
+`define MAX_PKT_LG2	`USB_PACKET_BITS
+
 package usb_endpoint_types;
    // Endpoint channel configuration (normally static)
    typedef struct {
       logic [3:0] ep_num;
       logic [3:0] ep_mask;
+      logic [`MAX_PKT_LG2:0] ep_max_pkt;
    } usb_ep_c_t;
 
    // Downstream data
@@ -62,20 +67,25 @@ package usb_endpoint_types;
       logic	  ep_selected;
       logic       rx_valid;
       logic       tx_data_accept;
+      logic	  tx_init;
+      logic	  tx_ack;
+      logic	  rx_init;
+      logic	  rx_ack;
+      logic	  rx_err;
    } usb_ep_u_t;
 
    // Upstream data, shared between all endpoints; included here
    // to make the interface complete. If suitable for the upstream
    // device core, however, they do not need to be multiplexed.
    typedef struct {
-      logic       rx_setup;
+      logic [3:0] ep_select;	  // Currently selected endpoint
       logic [7:0] rx_data;
+      logic       rx_setup;
       logic       rx_strb;
       logic       rx_last;
       logic       rx_crc_err;
-      logic [3:0] ep_select;	  // Currently selected endpoint
-      logic	  ep_select_rx;	  // Selected for read
    } usb_ep_uc_t;
+
 endpackage
 
 interface usb_endpoint;
@@ -84,6 +94,7 @@ interface usb_endpoint;
    usb_ep_c_t  c;
    usb_ep_d_t  d;
    usb_ep_u_t  u;
+   usb_ep_u_t  ux;		// Unmultiplexed
    usb_ep_uc_t uc;
 
    // Upstream interface (toward application)
@@ -91,6 +102,7 @@ interface usb_endpoint;
 		 input  c,
 		 input	d,
 		 output u,
+		 output ux,
 		 output uc
 		 );
 
@@ -99,6 +111,7 @@ interface usb_endpoint;
 		 output c,
 		 output d,
 		 input	u,
+		 input  ux,
 		 input	uc
 		 );
 endinterface // usb_endpoint
@@ -145,6 +158,7 @@ module usbf_endpoint_mux
 			      ((ep_d_uc.ep_select & ep_u[i].c.ep_mask) ==
 			       ep_u[i].c.ep_num);
 
+		ep_u[i].ux = ep_d_u;
 		ep_u[i].uc = ep_d_uc;
 		if (selected[i])
 		  ep_u[i].u = ep_d_u;
@@ -289,8 +303,10 @@ module usbf_device_core
    //-----------------------------------------------------------------
    usb_endpoint ept ();		// Endpoint selected by token
 
-   assign ept.uc.ep_select    = token_ep_w;
-   assign ept.uc.ep_select_rx = token_pid_w == `PID_IN | token_pid_w == `PID_PING;
+   assign ept.uc.ep_select = token_ep_w;
+   assign ept.u.rx_init    = token_valid_w & (token_pid_w == `PID_OUT);
+   assign ept.u.tx_init    = token_valid_w & (token_pid_w == `PID_IN ||
+					      token_pid_w == `PID_PING);
 
    usbf_endpoint_mux #(.endpoint_channels(endpoint_channels))
    u_endpoint_mux
@@ -337,10 +353,20 @@ module usbf_device_core
    assign tx_data_valid_r      = ept.d.tx_data_valid;
    assign tx_data_strb_r       = ept.d.tx_data_strb;
    assign tx_data_r            = ept.d.tx_data;
-   assign tx_data_last_r       = ept.d.tx_data_last;
 
    assign ept.u.tx_data_accept = tx_data_accept_w;
 
+   // Always terminate a packet upon reaching the max size
+   reg [`MAX_PKT_LG2-1:0]   tx_max_pkt_ctr;
+
+   always @(posedge clk_i)
+     if (token_valid_w)
+       tx_max_pkt_ctr <= ept.c.ep_max_pkt - 1'b1;
+     else if (tx_data_accept_w)
+       tx_max_pkt_ctr <= tx_max_pkt_ctr - 1'b1;
+
+   assign tx_data_last_r = ept.d.tx_data_last || !tx_max_pkt_ctr;
+
    //-----------------------------------------------------------------
    // SIE - RX
    //-----------------------------------------------------------------
@@ -395,6 +421,7 @@ module usbf_device_core
    assign ept.uc.rx_strb    = rx_strb_w;
    assign ept.uc.rx_last    = rx_last_w;
    assign ept.uc.rx_crc_err = rx_crc_err_w;
+   assign ept.u.rx_err      = rx_crc_err_w;
 
    //-----------------------------------------------------------------
    // Next state
@@ -770,15 +797,17 @@ module usbf_device_core
        current_addr_q  <= reg_dev_addr_i;
 
    //-----------------------------------------------------------------
-   // Endpoint data bit toggle
+   // Endpoint data bit toggle/ACK transmit
    //-----------------------------------------------------------------
-   reg	new_out_bit_r;
-   reg	new_in_bit_r;
+   reg	rx_ack_r;
+   reg	tx_ack_r;
+   reg	setup_r;
 
    always @ *
      begin
-	new_out_bit_r = out_data_bit_r;
-	new_in_bit_r  = in_data_bit_r;
+	rx_ack_r = 1'b0;
+	tx_ack_r = 1'b0;
+	setup_r  = 1'b0;
 
 	case (state_q)
 	  //-----------------------------------------
@@ -791,7 +820,7 @@ module usbf_device_core
 		 begin
 		    // No toggle on CRC16 error
 		    if (rx_crc_err_w)
-                      ;
+		      ;
 		    // ISO endpoint, no response?
 		    else if (ep_iso_r)
                       ; // TODO: HS handling
@@ -807,7 +836,7 @@ module usbf_device_core
                       ;
 		    // Data accepted - toggle data bit
 		    else
-                      new_out_bit_r = !out_data_bit_r;
+		      rx_ack_r = 1'b1;
 		 end
 	    end
 	  //-----------------------------------------
@@ -820,16 +849,11 @@ module usbf_device_core
 		 begin
 		    // SETUP packets always start with DATA0
 		    if (token_pid_w == `PID_SETUP)
-		      begin
-			 new_out_bit_r = 1'b0;
-			 new_in_bit_r  = 1'b1;
-		      end
+		      setup_r = 1'b1;
 		 end
                // ACK received
                else if (rx_handshake_w && token_pid_w == `PID_ACK)
-		 begin
-		    new_in_bit_r = !in_data_bit_r;
-		 end
+		 tx_ack_r = 1'b1;
 	    end
 	  default:
             ;
@@ -848,15 +872,23 @@ module usbf_device_core
 	    out_data_bit_q <= 'b0;
 	    in_data_bit_q  <= 'b0;
 	 end
+       else if (setup_r)
+	 begin
+	    out_data_bit_q[token_ep_w] <= 1'b0;
+	    in_data_bit_q [token_ep_w] <= 1'b1;
+	 end
        else
 	 begin
-	    out_data_bit_q[token_ep_w] <= new_out_bit_r;
-	    in_data_bit_q [token_ep_w] <= new_in_bit_r;
+	    out_data_bit_q[token_ep_w] <= out_data_bit_r ^ rx_ack_r;
+	    in_data_bit_q [token_ep_w] <= in_data_bit_r  ^ tx_ack_r;
 	 end // else: !if(rst_i)
 
    assign out_data_bit_r = out_data_bit_q[token_ep_w];
    assign in_data_bit_r  = in_data_bit_q [token_ep_w];
 
+   assign ept.u.tx_ack  = tx_ack_r;
+   assign ept.u.rx_ack  = rx_ack_r;
+
    //-----------------------------------------------------------------
    // Reset event
    //-----------------------------------------------------------------

fpga/usb/usb_serial/src_v/usbf_sie_rx.v

@@ -9,29 +9,31 @@
 //                         License: LGPL
 //-----------------------------------------------------------------
 //
-// This source file may be used and distributed without         
-// restriction provided that this copyright statement is not    
-// removed from the file and that any derivative work contains  
-// the original copyright notice and the associated disclaimer. 
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
 //
-// This source file is free software; you can redistribute it   
-// and/or modify it under the terms of the GNU Lesser General   
-// Public License as published by the Free Software Foundation; 
-// either version 2.1 of the License, or (at your option) any   
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
 // later version.
 //
-// This source is distributed in the hope that it will be       
-// useful, but WITHOUT ANY WARRANTY; without even the implied   
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-// PURPOSE.  See the GNU Lesser General Public License for more 
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE.  See the GNU Lesser General Public License for more
 // details.
 //
-// You should have received a copy of the GNU Lesser General    
-// Public License along with this source; if not, write to the 
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
 // Boston, MA  02111-1307  USA
 //-----------------------------------------------------------------
 
+//`define USB_RANDOM_CORRUPT 6
+
 //-----------------------------------------------------------------
 //                          Generated File
 //-----------------------------------------------------------------
@@ -385,6 +387,17 @@ reg [15:0]  crc_sum_q;
 wire [15:0] crc_out_w;
 reg         crc_err_q;
 
+`ifdef USB_RANDOM_CORRUPT
+   reg [`USB_RANDOM_CORRUPT-1:0] corrupt_ctr_q;
+
+   always @(posedge clk_i)
+     corrupt_ctr_q <= corrupt_ctr_q + 1'b1;
+
+   wire			     corrupt_rx = !corrupt_ctr_q;
+`else
+   wire			     corrupt_rx = 1'b0;
+`endif
+
 usbf_crc16
 u_crc16
 (
@@ -397,7 +410,7 @@ always @ (posedge clk_i or posedge rst_i)
 if (rst_i)
     crc_sum_q   <= 16'hFFFF;
 else if (state_q == STATE_RX_IDLE)
-    crc_sum_q   <= 16'hFFFF;
+    crc_sum_q   <= 16'hFFFF ^ corrupt_rx;
 else if (data_ready_w)
     crc_sum_q   <= crc_out_w;
 

fpga/usb/usb_serial/src_v/usbf_sie_tx.v

@@ -9,29 +9,31 @@
 //                         License: LGPL
 //-----------------------------------------------------------------
 //
-// This source file may be used and distributed without         
-// restriction provided that this copyright statement is not    
-// removed from the file and that any derivative work contains  
-// the original copyright notice and the associated disclaimer. 
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
 //
-// This source file is free software; you can redistribute it   
-// and/or modify it under the terms of the GNU Lesser General   
-// Public License as published by the Free Software Foundation; 
-// either version 2.1 of the License, or (at your option) any   
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
 // later version.
 //
-// This source is distributed in the hope that it will be       
-// useful, but WITHOUT ANY WARRANTY; without even the implied   
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-// PURPOSE.  See the GNU Lesser General Public License for more 
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE.  See the GNU Lesser General Public License for more
 // details.
 //
-// You should have received a copy of the GNU Lesser General    
-// Public License along with this source; if not, write to the 
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
 // Boston, MA  02111-1307  USA
 //-----------------------------------------------------------------
 
+//`define USB_RANDOM_CORRUPT 6
+
 //-----------------------------------------------------------------
 //                          Generated File
 //-----------------------------------------------------------------
@@ -262,6 +264,17 @@ reg [15:0]  crc_sum_q;
 wire [15:0] crc_out_w;
 reg         crc_err_q;
 
+`ifdef USB_RANDOM_CORRUPT
+   reg [`USB_RANDOM_CORRUPT-1:0] corrupt_ctr_q;
+
+   always @(posedge clk_i)
+     corrupt_ctr_q <= corrupt_ctr_q + 1'b1;
+
+   wire			     corrupt_tx = !corrupt_ctr_q;
+`else
+   wire			     corrupt_tx = 1'b0;
+`endif
+
 usbf_crc16
 u_crc16
 (
@@ -274,7 +287,7 @@ always @ (posedge clk_i or posedge rst_i)
 if (rst_i)
     crc_sum_q   <= 16'hFFFF;
 else if (state_q == STATE_TX_IDLE)
-    crc_sum_q   <= 16'hFFFF;
+    crc_sum_q   <= 16'hFFFF ^ corrupt_tx;
 else if (state_q == STATE_TX_DATA && utmi_txvalid_o && utmi_txready_i)
     crc_sum_q   <= crc_out_w;
 

fpga/v2.qsf

@@ -10,204 +10,6 @@ set_global_assignment -name VERILOG_FILE ip/pll2_16.v
 set_global_assignment -name QIP_FILE ip/pll2_16.qip
 set_global_assignment -name VERILOG_INCLUDE_FILE v2.vh
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE max80.qsf
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE15F17C8
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:21:14  DECEMBER 22, 2021"
-set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name DEVICE_MIGRATION_LIST EP4CE15F17C8
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name VCCA_USER_VOLTAGE 2.5V
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
-set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
-set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
-set_global_assignment -name MUX_RESTRUCTURE AUTO
-set_global_assignment -name WEAK_PULL_UP_RESISTOR ON
-set_global_assignment -name ENABLE_OCT_DONE OFF
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
-set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name GENERATE_JBC_FILE ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clk
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_*
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6
-set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[2]
-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[1]
-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[0]
-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_clk
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[2]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[1]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[0]
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_clk
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to board_id
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to led[1]
-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCQ128A
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:scripts/preflow.tcl"
-set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/postmodule.tcl"
-set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
-set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
-set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
-set_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name EDA_TEST_BENCH_NAME testclk -section_id eda_simulation
-set_global_assignment -name EDA_DESIGN_INSTANCE_NAME max80 -section_id testclk
-set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ms" -section_id testclk
-set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testclk -section_id testclk
-set_global_assignment -name EDA_TEST_BENCH_FILE simulation/testclk.sv -section_id testclk
-set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulation
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rtc_32khz
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hc
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hh
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdo
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tck
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdi
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tms
-set_global_assignment -name OCP_HW_EVAL DISABLE
-set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON
-set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS ON
-set_global_assignment -name POWER_REPORT_POWER_DISSIPATION ON
-set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
-set_global_assignment -name POWER_USE_TA_VALUE 35
-set_location_assignment PLL_3 -to "max80:max80|pll3:pll3|altpll:altpll_component|pll3_altpll:auto_generated|pll1"
-set_location_assignment PLL_4 -to "max80:max80|pll4:pll4|altpll:altpll_component|pll4_altpll:auto_generated|pll1"
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[15]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[14]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[13]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[12]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[11]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[10]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[9]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[8]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[7]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[5]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[4]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[3]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[2]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[1]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[0]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rngio[0]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rngio[1]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rngio[2]
-set_global_assignment -name VERILOG_FILE usb/usb_desc.v
-set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usb_cdc_core.sv
-set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usbf_device_core.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rng.sv
-set_global_assignment -name QIP_FILE ip/int_osc/synthesis/int_osc.qip
-set_global_assignment -name VERILOG_FILE ip/pll4.v
-set_global_assignment -name VERILOG_FILE ip/pll3.v
-set_global_assignment -name VERILOG_FILE usb/usb_fs_phy/src_v/usb_fs_phy.v
-set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_tx.v
-set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_rx.v
-set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_defs.v
-set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_crc16.v
-set_global_assignment -name SYSTEMVERILOG_FILE usb/usb.sv
-set_global_assignment -name VERILOG_FILE ip/statusram.v
-set_global_assignment -name VERILOG_INCLUDE_FILE iodevs.vh
-set_global_assignment -name SYSTEMVERILOG_FILE serial.sv
-set_global_assignment -name SYSTEMVERILOG_FILE sdcard.sv
-set_global_assignment -name SYSTEMVERILOG_FILE sysclock.sv
-set_global_assignment -name SYSTEMVERILOG_FILE i2c.sv
-set_global_assignment -name SYSTEMVERILOG_FILE abcbus.sv
-set_global_assignment -name VERILOG_FILE ip/abcmapram.v
-set_global_assignment -name SYSTEMVERILOG_FILE fast_mem.sv
-set_global_assignment -name MIF_FILE mif/sram.mif
-set_global_assignment -name VERILOG_FILE picorv32.v
-set_global_assignment -name SYSTEMVERILOG_FILE functions.sv
-set_global_assignment -name SYSTEMVERILOG_FILE spi_master.sv
-set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
-set_global_assignment -name SYSTEMVERILOG_FILE spirom.sv
-set_global_assignment -name SYSTEMVERILOG_FILE clkbuf.sv
-set_global_assignment -name VERILOG_FILE ip/ddio_out.v
-set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
-set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl
-set_global_assignment -name VERILOG_FILE ip/hdmitx.v
-set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
-set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
-set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
-set_global_assignment -name SYSTEMVERILOG_FILE video.sv
-set_global_assignment -name SDC_FILE max80.sdc
-set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
-set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
-set_global_assignment -name VERILOG_FILE ip/fifo.v
-set_global_assignment -name VERILOG_FILE ip/ddufifo.v
-set_global_assignment -name VERILOG_FILE ip/cdc_txfifo.v
-set_global_assignment -name VERILOG_FILE ip/cdc_rxfifo.v
-set_global_assignment -name QIP_FILE ip/cdc_txfifo.qip
-set_global_assignment -name QIP_FILE ip/cdc_rxfifo.qip
-set_global_assignment -name SYSTEMVERILOG_FILE vjtag_max80.sv
-set_global_assignment -name VERILOG_FILE ip/vjtag/synthesis/vjtag.v
-set_global_assignment -name QIP_FILE ip/vjtag/synthesis/vjtag.qip
-set_global_assignment -name SYSTEMVERILOG_FILE fpgarst.sv
-set_global_assignment -name VERILOG_FILE ip/altera_remote_update_core.v
-set_instance_assignment -name IO_STANDARD "BUS LVDS" -to usb_rx
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb_rx
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb_dp
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb_dn
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to usb_pu
-set_instance_assignment -name TERMINATION OFF -to usb_rx
-set_instance_assignment -name IO_STANDARD "2.5 V" -to sd_cd_n
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd_n
 
 # Quartus insists on this line...
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
-set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
-set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testclk -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME max80 -section_id eda_simulation
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

rv32/checksum.h

@@ -1,4 +1,4 @@
 #ifndef CHECKSUM_H
 #define CHECKSUM_H
-#define SDRAM_SUM 0xe2aecb1e
+#define SDRAM_SUM 0xe3fd05cf
 #endif