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@@ -34,42 +34,303 @@
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// Boston, MA 02111-1307 USA
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//-----------------------------------------------------------------
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-module usb_cdc_core
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+// Multiport CDC interface
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+//
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+// Each channel contains the following registers seen from the CPU:
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+//
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+// 0 - RW - FIFO read/write data register
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+// 1 - RW - watermark control
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+// 3:1 - transmit FIFO low watermark (resets to 1/4)
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+// 7:5 - transmit FIFO high watermark (resets to 3/4)
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+// 11:9 - receive FIFO low watermark (resets to 1/4)
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+// 15:13 - receive FIFO high watermark (resets to 3/4)
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+// 2 - RO - status register (some bits W1C)
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+// 0 - transmit FIFO empty
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+// 1 - transmit FIFO <= low watermark
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+// 2 - transmit FIFO >= high watermark
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+// 3 - transmit FIFO full
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+// 4 - receive FIFO empty
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+// 5 - receive FIFO <= low watermark
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+// 6 - receive FIFO >= high watermark
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+// 7 - receive FIFO full
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+// 8 - receive FIFO not empty after two USB frames
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+// 9 - BREAK received (sticky, W1C)
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+// 10 - USB device configured
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+// 3 - RW - interrupt enable register
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+// * - mask of corresponding status bits
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+
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+module usb_cdc_channel
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+ #(parameter [3:0] data_ep_num = 4'd1,
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+ parameter [3:0] intr_ep_num = data_ep_num+1'b1)
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(
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- // Inputs
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- input clk_i
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- ,input rst_i
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- ,input enable_i
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- ,input [ 7:0] utmi_data_in_i
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- ,input utmi_txready_i
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- ,input utmi_rxvalid_i
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- ,input utmi_rxactive_i
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- ,input utmi_rxerror_i
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- ,input [ 1:0] utmi_linestate_i
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- ,input inport_valid_i
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- ,input [ 7:0] inport_data_i
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- ,input outport_accept_i
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-
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- // Outputs
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- ,output [ 7:0] utmi_data_out_o
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- ,output utmi_txvalid_o
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- ,output [ 1:0] utmi_op_mode_o
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- ,output [ 1:0] utmi_xcvrselect_o
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- ,output utmi_termselect_o
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- ,output utmi_dppulldown_o
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- ,output utmi_dmpulldown_o
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- ,output inport_accept_o
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- ,output outport_valid_o
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- ,output [ 7:0] outport_data_o
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- ,output outport_break_o,
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-
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// CPU bus
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+ input rst_n,
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input sys_clk,
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input cpu_valid,
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- input [15:0] cpu_addr,
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+ input [1:0] cpu_addr,
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output [31:0] cpu_rdata,
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input [31:0] cpu_wdata,
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- input [3:0] cpu_wstrb
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+ input cpu_wstrb,
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+ output irq,
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+
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+ // Core FIFO interface
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+ input clk_i,
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+ input rst_i,
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+ usb_endpoint.dstr data_ep,
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+ usb_endpoint.dstr intr_ep,
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+
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+ // Control signals
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+ input recv_break_i,
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+ output recv_break_o, // sys_clk domain, reflects the status register
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+
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+ // USB status
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+ input usb_configured,
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+
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+ // Top of frame strobe *in sys_clk domain*
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+ input start_of_frame_s
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+ );
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+
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+ localparam fifo_size = 511;
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+ localparam fifo_bits = $clog2(fifo_size);
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+ localparam packet_bits = 6;
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+ localparam packet_size = 1 << packet_bits;
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+
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+ // Up to four bits per watermark, but all are not necessarily
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+ // implemented
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+ localparam water_bits = 3;
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+
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+ wire fifo_access = cpu_valid & cpu_addr == 2'b00;
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+ reg fifo_access_q;
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+ reg fifo_read_q;
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+
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+ always @(posedge sys_clk)
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+ begin
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+ fifo_access_q <= fifo_access;
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+ fifo_read_q <= fifo_access & ~cpu_wstrb;
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+ end
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+
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+ wire txempty;
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+ wire txfull;
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+ wire [fifo_bits-1:0] txused;
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+ wire [water_bits:0] txused_msb = txused[fifo_bits-1:fifo_bits-water_bits];
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+ wire inport_empty_w;
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+ reg inport_valid_q;
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+
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+ cdc_fifo txfifo (
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+ .wrclk ( sys_clk ),
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+ .data ( cpu_wdata[7:0] ),
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+ .wrreq ( fifo_access & ~fifo_access_q & cpu_wstrb ),
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+ .wrempty ( txempty ),
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+ .wrfull ( txfull ),
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+ .wrusedw ( txused ),
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+
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+ .rdclk ( clk_i ),
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+ .q ( data_ep.d.tx_data ),
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+ .rdreq ( ~inport_valid_q | data_ep.u.tx_data_accept ),
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+ .rdempty ( inport_empty_w ),
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+ .rdfull ( ),
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+ .rdusedw ( )
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+ );
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+
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+ always @(posedge clk_i or posedge rst_i)
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+ if (rst_i)
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+ inport_valid_q <= 1'b0;
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+ else if ( ~inport_empty_w )
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+ inport_valid_q <= 1'b1;
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+ else if ( data_ep.u.tx_data_accept )
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+ inport_valid_q <= 1'b0;
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+
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+ assign data_ep.d.tx_data_valid = inport_valid_q;
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+ assign data_ep.d.tx_ready = inport_valid_q;
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+ assign data_ep.d.tx_data_strb = inport_valid_q;
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+
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+ // Must terminate a transfer at the max packet size
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+ reg [packet_bits-1:0] inport_cnt_q;
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+ wire inport_last_w = inport_empty_w | &inport_cnt_q;
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+
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+ always @(posedge clk_i or posedge rst_i)
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+ if (rst_i)
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+ inport_cnt_q <= 'd0;
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+ else if (inport_last_w & data_ep.u.tx_data_accept)
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+ inport_cnt_q <= 'd0;
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+ else if (inport_valid_q & data_ep.u.tx_data_accept)
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+ inport_cnt_q <= inport_cnt_q + 1'b1;
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+
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+ assign data_ep.d.tx_data_last = inport_last_w;
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+
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+ wire [7:0] rdata_fifo;
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+ wire rxempty;
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+ wire rxfull;
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+ wire [fifo_bits-1:0] rxused;
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+ wire [water_bits:0] rxused_msb = rxused[fifo_bits-1:fifo_bits-water_bits];
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+ wire [fifo_bits-1:0] outport_used_w;
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+
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+ wire outport_valid_w = data_ep.u.rx_valid & data_ep.uc.rx_strb;
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+
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+ assign data_ep.d.rx_space = outport_used_w <= fifo_size - packet_size;
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+
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+ cdc_fifo rxfifo (
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+ .rdclk ( sys_clk ),
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+ .q ( rdata_fifo ),
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+ .rdreq ( fifo_access & ~fifo_access_q & ~cpu_wstrb ),
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+ .rdempty ( rxempty ),
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+ .rdfull ( rxfull ),
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+ .rdusedw ( rxused ),
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+
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+ .wrclk ( clk_i ),
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+ .data ( data_ep.uc.rx_data ),
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+ .wrreq ( outport_valid_w ),
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+ .wrempty ( ),
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+ .wrfull ( ),
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+ .wrusedw ( outport_used_w )
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+ );
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+
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+ // Queued data wakeup
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+ reg [1:0] had_rxdata;
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+
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+ always @(posedge sys_clk)
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+ begin
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+ if (start_of_frame_s)
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+ had_rxdata <= { had_rxdata[0], 1'b1 };
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+ if (rxempty)
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+ had_rxdata <= 2'b00;
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+ end
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+
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+ wire [15:0] status_mask = 16'b0000_0111_1111_1111; // Implemented bit mask
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+ reg [15:0] irq_mask;
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+ wire [ 3:0] water_mask = 4'b1111 << (4-water_bits);
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+ wire [15:0] water_ctl_mask = {4{water_mask}};
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+ reg [15:0] water_ctl;
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+
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+ wire recv_break_s;
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+ reg recv_break_q;
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+
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+ synchronizer #(.width(1)) break_synchro
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+ (
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+ .rst_n ( rst_n ),
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+ .clk ( sys_clk ),
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+ .d ( recv_break_i ),
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+ .q ( recv_break_s )
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+ );
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+
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+ always @(negedge rst_n or posedge sys_clk)
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+ if (~rst_n)
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+ begin
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+ water_ctl <= 16'h8787 & water_ctl_mask;
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+ irq_mask <= 16'b0;
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+ recv_break_q <= 1'b0;
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+ end
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+ else
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+ begin
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+ if (recv_break_s)
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+ recv_break_q <= 1'b1;
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+
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+ if (cpu_valid & cpu_wstrb)
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+ case (cpu_addr)
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+ 2'b01: water_ctl <= cpu_wdata[15:0] & water_ctl_mask;
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+ 2'b10: if (cpu_wdata[9]) recv_break_q <= 1'b0;
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+ 2'b11: irq_mask <= cpu_wdata[15:0] & status_mask;
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+ default: /* do nothing */;
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+ endcase // case (cpu_addr)
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+ end // else: !if(~rst_n)
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+
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+ assign recv_break_o = recv_break_q; // Available to external logic
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+
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+ tri0 [15:0] status;
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+ assign status[0] = txempty;
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+ assign status[1] = (txused_msb <= water_ctl[3:4-water_bits]);
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+ assign status[2] = (txused_msb >= water_ctl[7:8-water_bits]);
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+ assign status[3] = txfull;
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+
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+ assign status[4] = rxempty;
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+ assign status[5] = (rxused_msb <= water_ctl[11:12-water_bits]);
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+ assign status[6] = (rxused_msb >= water_ctl[15:16-water_bits]);
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+ assign status[7] = rxfull;
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+
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+ assign status[8] = had_rxdata[1];
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+ assign status[9] = recv_break_q;
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+ assign status[10] = usb_configured;
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+
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+ assign irq = |(status & irq_mask);
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+
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+ always @(*)
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+ case (cpu_addr)
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+ 2'b00: cpu_rdata = { 24'b0, rdata_fifo };
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+ 2'b01: cpu_rdata = { 16'b0, water_ctl };
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+ 2'b10: cpu_rdata = { 16'b0, status };
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+ 2'b11: cpu_rdata = { 16'b0, irq_mask };
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+ default: cpu_rdata = 32'bx;
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+ endcase // case (cpu_addr)
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+
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+ // Channel configurations
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+ assign data_ep.c.ep_num = data_ep_num;
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+ assign data_ep.c.ep_mask = 4'b1111;
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+ assign intr_ep.c.ep_num = intr_ep_num;
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+ assign intr_ep.c.ep_mask = 4'b1111;
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+
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+ // Data channel endpoint: unused signals
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+ assign data_ep.d.ep_iso = 1'b0;
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+ assign data_ep.d.cfg_int_rx = 1'b0;
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+ assign data_ep.d.cfg_int_tx = 1'b0;
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+ assign data_ep.d.ep_stall = 1'b0;
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+
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+ // Notification channel endpoint: currently never used at all
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+ assign intr_ep.d.ep_iso = 1'b0;
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+ assign intr_ep.d.cfg_int_rx = 1'b0;
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+ assign intr_ep.d.cfg_int_tx = 1'b0;
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+ assign intr_ep.d.ep_stall = 1'b0;
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+ assign intr_ep.d.tx_ready = 1'b0;
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+ assign intr_ep.d.tx_data_valid = 1'b0;
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+ assign intr_ep.d.tx_data_strb = 1'b0;
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+ assign intr_ep.d.tx_data = 8'bx;
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+ assign intr_ep.d.tx_data_last = 1'b0;
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+ assign intr_ep.d.rx_space = 1'b0;
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+
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+endmodule // usb_cdc_channel
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+
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+module usb_cdc_core
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+ #( parameter [2:0] channels = 3'd1 )
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+ (
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+ // Inputs
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+ input clk_i,
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+ input rst_i,
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+ input enable_i,
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+ input [ 7:0] utmi_data_in_i,
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+ input utmi_txready_i,
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+ input utmi_rxvalid_i,
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+ input utmi_rxactive_i,
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+ input utmi_rxerror_i,
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+ input [ 1:0] utmi_linestate_i,
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+ //input inport_valid_i,
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+ //input [ 7:0] inport_data_i,
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+ //input outport_accept_i,
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+
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+ // Outputs
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+ output [ 7:0] utmi_data_out_o,
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+ output utmi_txvalid_o,
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+ output [ 1:0] utmi_op_mode_o,
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+ output [ 1:0] utmi_xcvrselect_o,
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+ output utmi_termselect_o,
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+ output utmi_dppulldown_o,
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+ output utmi_dmpulldown_o,
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+ output [channels-1:0] recv_break_o,
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+
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+ //output inport_accept_o,
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+ //output outport_valid_o,
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+ //output [ 7:0] outport_data_o,
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+ //output outport_break_o,
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+
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+ // CPU bus
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+ input rst_n,
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+ input sys_clk,
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+ input cpu_valid_cdc,
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+ input cpu_valid_usbdesc,
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+ input [31:0] cpu_addr,
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+ output [31:0] cpu_rdata_cdc,
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+ output [31:0] cpu_rdata_usbdesc,
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+ input [31:0] cpu_wdata,
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+ input [3:0] cpu_wstrb,
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+ output [channels-1:0] irq
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);
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parameter USB_SPEED_HS = "False"; // True or False
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@@ -168,7 +429,7 @@ module usb_cdc_core
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wire usb_reset_w;
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reg [6:0] device_addr_q;
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- localparam endpoint_channels = 4;
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+ localparam endpoint_channels = channels*2 + 1;
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usb_endpoint usb_ep [0:endpoint_channels-1] ();
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wire utmi_chirp_en_w;
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@@ -391,13 +652,15 @@ module usb_cdc_core
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//-----------------------------------------------------------------
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// Core
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//-----------------------------------------------------------------
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+ wire start_of_frame_w; // Or reset, but close enough
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+
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usbf_device_core #(.endpoint_channels(endpoint_channels))
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u_core
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(
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.clk_i(clk_i),
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.rst_i(rst_i),
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- .intr_o(),
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+ .intr_o(start_of_frame_w),
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// UTMI interface
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.utmi_data_o(utmi_data_out_o),
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@@ -519,8 +782,7 @@ module usb_cdc_core
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reg [15:0] desc_base_addr_r;
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reg [15:0] desc_len_r;
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- reg rx_break_q;
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- reg rx_break_r;
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+ reg [7:0] rx_break_r;
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reg addressed_q;
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reg addressed_r;
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@@ -546,13 +808,14 @@ module usb_cdc_core
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always @ *
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begin
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- ctrl_stall_r = 1'b0;
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- ctrl_ack_r = 1'b0;
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- device_addr_r = device_addr_q;
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- addressed_r = addressed_q;
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- configured_r = configured_q;
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- set_with_data_r = set_with_data_q;
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- rx_break_r = 1'b0;
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+ ctrl_stall_r = 1'b0;
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+ ctrl_ack_r = 1'b0;
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+ ctrl_send_data_r = 1'b0;
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+ device_addr_r = device_addr_q;
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|
+ addressed_r = addressed_q;
|
|
|
+ configured_r = configured_q;
|
|
|
+ set_with_data_r = set_with_data_q;
|
|
|
+ rx_break_r = 8'b0;
|
|
|
|
|
|
if (setup_valid_q)
|
|
|
begin
|
|
|
@@ -596,15 +859,10 @@ module usb_cdc_core
|
|
|
begin
|
|
|
$display("SET_CONF: Configuration %x", wValue_w);
|
|
|
|
|
|
- if (wValue_w == 16'd0)
|
|
|
- begin
|
|
|
- configured_r = 1'b0;
|
|
|
- ctrl_ack_r = setup_set_w && setup_no_data_w;
|
|
|
- end
|
|
|
// Only support one configuration for now
|
|
|
- else if (wValue_w == 16'd1)
|
|
|
+ if (wValue_w < 16'd2)
|
|
|
begin
|
|
|
- configured_r = 1'b1;
|
|
|
+ configured_r = wValue_w[0];
|
|
|
ctrl_ack_r = setup_set_w && setup_no_data_w;
|
|
|
end
|
|
|
else
|
|
|
@@ -615,14 +873,16 @@ module usb_cdc_core
|
|
|
$display("GET_INTERFACE");
|
|
|
ctrl_stall_r = 1'b1;
|
|
|
end
|
|
|
+//`ifdef HANDLE_SET_INTERFACE
|
|
|
`REQ_SET_INTERFACE:
|
|
|
begin
|
|
|
$display("SET_INTERFACE: %x %x", wValue_w, wIndex_w);
|
|
|
- if (wValue_w == 16'd0 && wIndex_w == 16'd0)
|
|
|
+ if (wValue_w == 16'd0 && wIndex_w < (channels << 1))
|
|
|
ctrl_ack_r = setup_set_w && setup_no_data_w;
|
|
|
else
|
|
|
ctrl_stall_r = 1'b1;
|
|
|
end
|
|
|
+//`endif
|
|
|
default:
|
|
|
begin
|
|
|
ctrl_stall_r = 1'b1;
|
|
|
@@ -647,7 +907,7 @@ module usb_cdc_core
|
|
|
end
|
|
|
`CDC_SEND_BREAK:
|
|
|
begin
|
|
|
- rx_break_r = (wValue_w != 16'd0);
|
|
|
+ rx_break_r[wIndex_w[3:1]] = wIndex_w[0] & |wValue_w;
|
|
|
end
|
|
|
default:
|
|
|
begin
|
|
|
@@ -672,7 +932,6 @@ module usb_cdc_core
|
|
|
addressed_q <= 1'b0;
|
|
|
configured_q <= 1'b0;
|
|
|
set_with_data_q <= 1'b0;
|
|
|
- rx_break_q <= 1'b0;
|
|
|
end
|
|
|
else if (usb_reset_w)
|
|
|
begin
|
|
|
@@ -680,7 +939,6 @@ module usb_cdc_core
|
|
|
addressed_q <= 1'b0;
|
|
|
configured_q <= 1'b0;
|
|
|
set_with_data_q <= 1'b0;
|
|
|
- rx_break_q <= 1'b0;
|
|
|
end
|
|
|
else
|
|
|
begin
|
|
|
@@ -688,7 +946,6 @@ module usb_cdc_core
|
|
|
addressed_q <= addressed_r;
|
|
|
configured_q <= configured_r;
|
|
|
set_with_data_q <= set_with_data_r;
|
|
|
- rx_break_q <= rx_break_r;
|
|
|
end
|
|
|
|
|
|
//-----------------------------------------------------------------
|
|
|
@@ -874,126 +1131,85 @@ module usb_cdc_core
|
|
|
assign usb_ep[0].d.tx_data_last = ctrl_txlast_q;
|
|
|
assign usb_ep[0].d.ep_stall = ctrl_txstall_q;
|
|
|
|
|
|
+ // Unused endpoint 0 signals
|
|
|
+ assign usb_ep[0].d.ep_iso = 1'b0;
|
|
|
+ assign usb_ep[0].d.cfg_int_rx = 1'b0;
|
|
|
+ assign usb_ep[0].d.cfg_int_tx = 1'b0;
|
|
|
+
|
|
|
//-----------------------------------------------------------------
|
|
|
// Descriptor ROM
|
|
|
//-----------------------------------------------------------------
|
|
|
+ wire [7:0] rdata_usbdesc;
|
|
|
+
|
|
|
usb_desc_rom
|
|
|
u_rom
|
|
|
(
|
|
|
- .clk (clk_i),
|
|
|
- .usb_addr (desc_addr_r),
|
|
|
- .usb_rdata (desc_data_w),
|
|
|
+ .clk ( clk_i ),
|
|
|
+ .usb_addr ( desc_addr_r ),
|
|
|
+ .usb_rdata ( desc_data_w ),
|
|
|
|
|
|
// CPU interface for modifications
|
|
|
- .cpu_clk (sys_clk),
|
|
|
- .cpu_addr (cpu_addr),
|
|
|
- .cpu_rdata (cpu_rdata[7:0]),
|
|
|
- .cpu_wdata (cpu_wdata[7:0]),
|
|
|
- .cpu_wren (cpu_valid & cpu_wstrb[0])
|
|
|
+ .cpu_clk ( sys_clk ),
|
|
|
+ .cpu_addr ( cpu_addr[17:2] ),
|
|
|
+ .cpu_rdata ( cpu_rdata_usbdesc[7:0] ),
|
|
|
+ .cpu_wdata ( cpu_wdata[7:0] ),
|
|
|
+ .cpu_wren ( cpu_valid_usbdesc & cpu_wstrb[0] )
|
|
|
);
|
|
|
- assign cpu_rdata[31:8] = 24'bx;
|
|
|
-
|
|
|
- //-----------------------------------------------------------------
|
|
|
- // Unused Endpoint Downstream Signals
|
|
|
- //-----------------------------------------------------------------
|
|
|
-
|
|
|
- assign usb_ep[0].d.ep_iso = 1'b0;
|
|
|
- assign usb_ep[0].d.cfg_int_rx = 1'b0;
|
|
|
- assign usb_ep[0].d.cfg_int_tx = 1'b0;
|
|
|
|
|
|
- // EP1: unused
|
|
|
- assign usb_ep[1].d.ep_iso = 1'b0;
|
|
|
- assign usb_ep[1].d.cfg_int_rx = 1'b0;
|
|
|
- assign usb_ep[1].d.cfg_int_tx = 1'b0;
|
|
|
- assign usb_ep[1].d.ep_stall = 1'b1;
|
|
|
- assign usb_ep[1].d.tx_ready = 1'b0;
|
|
|
- assign usb_ep[1].d.tx_data_valid = 1'b0;
|
|
|
- assign usb_ep[1].d.tx_data_strb = 1'b0;
|
|
|
- assign usb_ep[1].d.tx_data = 8'bx;
|
|
|
- assign usb_ep[1].d.tx_data_last = 1'b0;
|
|
|
- assign usb_ep[1].d.rx_space = 1'b0;
|
|
|
-
|
|
|
- // EP2: data channel
|
|
|
- assign usb_ep[2].d.ep_iso = 1'b0;
|
|
|
- assign usb_ep[2].d.cfg_int_rx = 1'b0;
|
|
|
- assign usb_ep[2].d.cfg_int_tx = 1'b0;
|
|
|
- assign usb_ep[2].d.ep_stall = 1'b0;
|
|
|
-
|
|
|
- // EP3: notification output
|
|
|
- assign usb_ep[3].d.ep_iso = 1'b0;
|
|
|
- assign usb_ep[3].d.cfg_int_rx = 1'b0;
|
|
|
- assign usb_ep[3].d.cfg_int_tx = 1'b0;
|
|
|
- assign usb_ep[3].d.ep_stall = 1'b0;
|
|
|
- assign usb_ep[3].d.tx_ready = 1'b0;
|
|
|
- assign usb_ep[3].d.tx_data_valid = 1'b0;
|
|
|
- assign usb_ep[3].d.tx_data_strb = 1'b0;
|
|
|
- assign usb_ep[3].d.tx_data = 8'bx;
|
|
|
- assign usb_ep[3].d.tx_data_last = 1'b0;
|
|
|
- assign usb_ep[3].d.rx_space = 1'b0;
|
|
|
+ assign cpu_rdata_usbdesc[31:8] = 24'b0;
|
|
|
|
|
|
//-----------------------------------------------------------------
|
|
|
- // Stream endpoint channel configuration
|
|
|
+ // Channel streaming interfaces and CPU interfaces
|
|
|
//-----------------------------------------------------------------
|
|
|
- assign usb_ep[1].c.ep_num = 4'd1;
|
|
|
- assign usb_ep[1].c.ep_mask = 4'b1111;
|
|
|
- assign usb_ep[2].c.ep_num = 4'd2;
|
|
|
- assign usb_ep[2].c.ep_mask = 4'b1111;
|
|
|
- assign usb_ep[3].c.ep_num = 4'd3;
|
|
|
- assign usb_ep[3].c.ep_mask = 4'b1111;
|
|
|
|
|
|
- //-----------------------------------------------------------------
|
|
|
- // Stream I/O
|
|
|
- //-----------------------------------------------------------------
|
|
|
- reg inport_valid_q;
|
|
|
- reg [7:0] inport_data_q;
|
|
|
- reg [10:0] inport_cnt_q;
|
|
|
- reg outport_break_q;
|
|
|
+ wire start_of_frame_ws;
|
|
|
+ reg start_of_frame_q;
|
|
|
|
|
|
- always @ (posedge clk_i or posedge rst_i)
|
|
|
- if (rst_i)
|
|
|
- begin
|
|
|
- inport_valid_q <= 1'b0;
|
|
|
- inport_data_q <= 8'b0;
|
|
|
- end
|
|
|
- else if (inport_accept_o)
|
|
|
- begin
|
|
|
- inport_valid_q <= inport_valid_i;
|
|
|
- inport_data_q <= inport_data_i;
|
|
|
- end
|
|
|
+ synchronizer #(.width(1))
|
|
|
+ sof_sync (
|
|
|
+ .rst_n ( 1'b1 ),
|
|
|
+ .clk ( sys_clk ),
|
|
|
+ .d ( start_of_frame_w ),
|
|
|
+ .q ( start_of_frame_ws )
|
|
|
+ );
|
|
|
|
|
|
- wire [10:0] max_packet_w = usb_hs_w ? 11'd511 : 11'd63;
|
|
|
- wire inport_last_w = !inport_valid_i || (inport_cnt_q == max_packet_w);
|
|
|
+ always @(posedge sys_clk)
|
|
|
+ start_of_frame_q <= start_of_frame_ws;
|
|
|
|
|
|
- always @ (posedge clk_i or posedge rst_i)
|
|
|
- if (rst_i)
|
|
|
- inport_cnt_q <= 11'b0;
|
|
|
- else if (inport_last_w && usb_ep[2].u.tx_data_accept)
|
|
|
- inport_cnt_q <= 11'b0;
|
|
|
- else if (inport_valid_q && usb_ep[2].u.tx_data_accept)
|
|
|
- inport_cnt_q <= inport_cnt_q + 11'd1;
|
|
|
-
|
|
|
- assign usb_ep[2].d.tx_data_valid = inport_valid_q;
|
|
|
- assign usb_ep[2].d.tx_ready = inport_valid_q;
|
|
|
- assign usb_ep[2].d.tx_data_strb = inport_valid_q;
|
|
|
- assign usb_ep[2].d.tx_data = inport_data_q;
|
|
|
- assign usb_ep[2].d.tx_data_last = inport_last_w;
|
|
|
+ wire start_of_frame_s = start_of_frame_ws & ~start_of_frame_q;
|
|
|
|
|
|
- assign inport_accept_o = !inport_valid_q | usb_ep[2].u.tx_data_accept;
|
|
|
+ tri0 [31:0] rdata_chan[0:7];
|
|
|
|
|
|
- assign outport_valid_o = usb_ep[2].u.rx_valid && usb_ep[2].uc.rx_strb;
|
|
|
- assign outport_data_o = usb_ep[2].uc.rx_data;
|
|
|
- assign usb_ep[2].d.rx_space = outport_accept_i;
|
|
|
-
|
|
|
- always @(posedge clk_i or posedge rst_i)
|
|
|
- if (rst_i)
|
|
|
- outport_break_q <= 1'b0;
|
|
|
- else
|
|
|
- outport_break_q <= rx_break_q |
|
|
|
- (outport_break_q &
|
|
|
- ~setup_set_w &
|
|
|
- ~outport_valid_o &
|
|
|
- ~(inport_valid_q & usb_ep[2].u.tx_data_accept));
|
|
|
+ generate
|
|
|
+ genvar cn;
|
|
|
+ for (cn = 0; cn < channels; cn++)
|
|
|
+ begin : chan
|
|
|
+ usb_cdc_channel #(.data_ep_num ( cn*2+1 ),
|
|
|
+ .intr_ep_num ( cn*2+2 ))
|
|
|
+ cchan (
|
|
|
+ .rst_n ( rst_n ),
|
|
|
+ .sys_clk ( sys_clk ),
|
|
|
+ .cpu_valid ( cpu_valid_cdc & cpu_addr[6:4] == cn ),
|
|
|
+ .cpu_addr ( cpu_addr[3:2] ),
|
|
|
+ .cpu_rdata ( rdata_chan[cn] ),
|
|
|
+ .cpu_wdata ( cpu_wdata ),
|
|
|
+ .cpu_wstrb ( cpu_wstrb[0] ),
|
|
|
+ .irq ( irq[cn] ),
|
|
|
+
|
|
|
+ .clk_i ( clk_i ),
|
|
|
+ .rst_i ( rst_i ),
|
|
|
+ .data_ep ( usb_ep[cn*2+1].dstr ),
|
|
|
+ .intr_ep ( usb_ep[cn*2+2].dstr ),
|
|
|
+
|
|
|
+ .usb_configured ( configured_q ),
|
|
|
+
|
|
|
+ .recv_break_i ( rx_break_r[cn] ),
|
|
|
+ .recv_break_o ( recv_break_o[cn] ),
|
|
|
+ .start_of_frame_s ( start_of_frame_s )
|
|
|
+ );
|
|
|
+ end // block: chan
|
|
|
+ endgenerate
|
|
|
|
|
|
- assign outport_break_o = outport_break_q;
|
|
|
+ assign cpu_rdata_cdc = rdata_chan[cpu_addr[6:4]];
|
|
|
|
|
|
endmodule
|
H. Peter Anvin