tty: actually clock tty unit; alternative serial port on GPIO

Actually clock the tty unit! Rename clk to sys_clk globally; it really
makes more sense to have all clocks match the names *_clk.

To support both reworked and unreworked boards, use either CP2102 or
GPIOs depending on where we get an asserted DTR#. The pinout for GPIOs
are (with the FPGA as DCE)

0 : TxD
1 : RxD
2 : RTS#
3 : CTS#
4 : DTR#

Configure most I/Os with weak pullups.

fpga/max80.qsf

@@ -76,7 +76,7 @@ set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
 set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
 set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
 set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
-set_global_assignment -name WEAK_PULL_UP_RESISTOR OFF
+set_global_assignment -name WEAK_PULL_UP_RESISTOR ON
 set_global_assignment -name ENABLE_OCT_DONE OFF
 set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
 set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
@@ -181,4 +181,57 @@ set_global_assignment -name SOURCE_FILE max80.pins
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 set_global_assignment -name VERILOG_FILE ip/fifo.v
 
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_dtr
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_rts
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to tty_txd
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_rxd
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tty_cts
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdmi_scl
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to hdmi_sda
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i2c_scl
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i2c_sda
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rtc_32khz
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rtc_int_n
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_ha
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_hb
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hc
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_hd
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_he
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_hf
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to exth_hg
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hh
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to esp_int
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to esp_io0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_dat[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_dat[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_dat[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_dat[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_dat
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_cs_esp_n
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_cs_flash_n
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_miso
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to spi_mosi
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to gpio
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_inp_n[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[13]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[1]
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdo
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tck
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to abc_xinpstb_n
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdi
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tms
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/max80.sv

@@ -125,15 +125,16 @@ module max80 (
 
    // Clocks
    wire	    sdram_clk;
-   wire	    clk;		// System clock
+   wire	    sys_clk;		// System clock
    wire	    vid_clk;		// Video pixel clock
    wire	    vid_hdmiclk;	// D:o in the HDMI clock domain
+   wire     tty_clk = vid_clk; // 48 MHz
 
    pll pll (
 	    .areset ( 1'b0 ),
 	    .inclk0 ( clock_48 ),
 	    .c0 ( sdram_clk ),		// SDRAM clock  (168 MHz)
-	    .c1 ( clk ),		// System clock (84 MHz)
+	    .c1 ( sys_clk ),		// System clock (84 MHz)
 	    .c2 ( vid_clk ),		// Video pixel clock (48 MHz)
 	    .locked ( pll_locked[0] ),
 	    .phasestep ( 1'b0 ),
@@ -145,7 +146,7 @@ module max80 (
 
    wire all_plls_locked = &pll_locked;
 
-   always @(negedge all_plls_locked or posedge clk)
+   always @(negedge all_plls_locked or posedge sys_clk)
      if (~&all_plls_locked)
        begin
 	  rst_ctr <= 1'b0;
@@ -311,17 +312,6 @@ module max80 (
    assign exth_q  = 6'b0;
    assign exth_oe = 6'b0;
 
-   // LED blink counter
-   reg [28:0] led_ctr;
-
-   always @(posedge clk or negedge rst_n)
-     if (~rst_n)
-       led_ctr <= 29'b0;
-     else
-       led_ctr <= led_ctr + 1'b1;
-
-   //assign led = led_ctr[28:26];
-
    // SDRAM controller
    reg	      abc_rrq;
    reg	      abc_wrq;
@@ -461,7 +451,7 @@ module max80 (
 	      .STACKADDR ( 32'h4 << cpu_fast_mem_bits )
 	      )
    cpu (
-	.clk ( clk ),
+	.clk ( sys_clk ),
 	.resetn ( rst_n ),
 	.trap ( ),
 
@@ -499,7 +489,7 @@ module max80 (
    fast_mem // #(.bits(cpu_fast_mem_bits), .mif("../fw/boot"))
    fast_mem(
 	    .rst_n ( rst_n ),
-	    .clk   ( clk ),
+	    .clk   ( sys_clk ),
 	    .read  ( cpu_la_read  & cpu_la_addr[31:30] == 2'b00 ),
 	    .write ( cpu_la_write & cpu_la_addr[31:30] == 2'b00 ),
 	    .wstrb ( cpu_la_wstrb ),
@@ -520,7 +510,7 @@ module max80 (
 
    // LED indication from the CPU
    reg [2:0]   led_q;
-   always @(negedge rst_n or posedge clk)
+   always @(negedge rst_n or posedge sys_clk)
      if (~rst_n)
        led_q <= 3'b000;
      else
@@ -529,18 +519,59 @@ module max80 (
 
    assign led = led_q;
 
-   // USB serial
-   assign tty_cts   = 1'b0;	// Assert CTS#
+   //
+   // Serial port. Direct to the CP2102N for reworked
+   // boards or to GPIO for non-reworked boards, depending on
+   // whether DTR# is asserted on either.
+   //
+   // The GPIO numbering matches the order of pins for FT[2]232H.
+   // gpio[0] - TxD
+   // gpio[1] - RxD
+   // gpio[2] - RTS#
+   // gpio[3] - CTS#
+   // gpio[4] - DTR#
+   //
+   wire        tty_data_out;	// Output data
+   wire        tty_data_in;	// Input data
+   wire        tty_cts_out;	// Assert CTS# externally
+   wire        tty_rts_in;	// RTS# received from outside
+
+   assign tty_cts_out  = 1'b0;	// Assert CTS#
    tty tty (
 	    .rst_n ( rst_n ),
 	    .sys_clk ( sys_clk ),
-	    .tty_clk ( vid_clk ), // 48 MHz
+	    .tty_clk ( tty_clk ),
 
 	    .valid ( iodev[1] ),
 	    .wstrb ( cpu_mem_wstrb ),
 	    .wdata ( cpu_mem_wdata ),
 	    .addr ( cpu_mem_addr[2] ),
 
-	    .tty_txd ( tty_rxd ) // DTE -> DCE
+	    .tty_txd ( tty_data_out ) // DTE -> DCE
 	    );
+
+   reg [1:0]   tty_dtr_q;
+   always @(posedge tty_clk)
+     begin
+	tty_dtr_q[0] <= tty_dtr;
+	tty_dtr_q[1] <= gpio[4];
+     end
+
+   //
+   // Route data to the two output ports
+   //
+
+   // tty_rxd because pins are DCE named
+   assign tty_data_in = (tty_txd | tty_dtr_q[0]) &
+			(gpio[0] | tty_dtr_q[1]);
+
+   assign tty_rxd = tty_dtr_q[0] ? 1'bz : tty_data_out;
+   assign gpio[1] = tty_dtr_q[1] ? 1'bz : tty_data_out;
+
+   assign tty_rts_in = (tty_rts | tty_dtr_q[0]) &
+		       (gpio[2] | tty_dtr_q[1]);
+
+   assign tty_cts = tty_dtr_q[0] ? 1'bz : tty_cts_out;
+   assign gpio[3] = tty_dtr_q[1] ? 1'bz : tty_cts_out;
+
 endmodule

fpga/output_files/max80.map

@@ -10,7 +10,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 Notes:
 
-- Data checksum for this conversion is 0xF77977EA
+- Data checksum for this conversion is 0xF783E86E
 
 - All the addresses in this file are byte addresses
 

fpga/tty.sv

@@ -94,11 +94,11 @@ module tty (
    always @(posedge sys_clk)
      old_wstrb <= wstrb[0];
 
-   assign tx_wrreq = rst_n & wstrb[0] & (addr == 0);
+   assign tx_wrreq = valid & wstrb[0] & ~old_wstrb & (addr == 0);
 
    // Divisor register
    always @(posedge sys_clk)
-     if (wstrb[0] & (addr == 1))
+     if (wstrb[0] & valid & (addr == 1))
        divisor_q <= wdata[divisor_bits-1:0] & wmask;
 
    synchronizer #(.width(divisor_bits), .stages(2)) sync_divisor