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@@ -1,215 +1,7 @@
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# -*- tcl -*-
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#
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# This file contains no real content, so when Quartus messes it up it
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-# can just be reset.
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-#
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-
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+# can just be reset. The only real line is:
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+# set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v1_main.qsf
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set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v1_main.qsf
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-set_global_assignment -name VERILOG_FILE ip/pll2_48.v
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[1]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[3]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[5]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_clk
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_inp_n[1]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[13]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[2]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[6]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[0]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[1]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to tty_txd
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-set_global_assignment -name TOP_LEVEL_ENTITY v1
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-set_global_assignment -name SOURCE_FILE v1.pins
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-set_global_assignment -name SYSTEMVERILOG_FILE v1.sv
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-set_global_assignment -name QIP_FILE ip/pll2_48.qip
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-set_global_assignment -name SOURCE_FILE output/v1.jic.cof
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-set_global_assignment -name SOURCE_TCL_SCRIPT_FILE max80.qsf
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-set_global_assignment -name FAMILY "Cyclone IV E"
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-set_global_assignment -name DEVICE EP4CE15F17C8
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-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
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-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:21:14 DECEMBER 22, 2021"
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-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
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-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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-set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
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-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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-set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
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-set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
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-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
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-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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-set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
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-set_global_assignment -name DEVICE_MIGRATION_LIST EP4CE15F17C8
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-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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-set_global_assignment -name VCCA_USER_VOLTAGE 2.5V
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-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
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-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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-set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
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-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
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-set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
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-set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
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-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
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-set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
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-set_global_assignment -name MUX_RESTRUCTURE AUTO
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-set_global_assignment -name WEAK_PULL_UP_RESISTOR ON
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-set_global_assignment -name ENABLE_OCT_DONE OFF
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-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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-set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
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-set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
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-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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-set_global_assignment -name GENERATE_JBC_FILE ON
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-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clk
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_*
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-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6
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-set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
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-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[2]
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-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[1]
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-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[0]
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-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_clk
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[2]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[1]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[0]
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-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
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-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
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-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
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-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
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-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
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-set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
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-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_clk
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to board_id
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-set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
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-set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
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-set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME max80 -section_id eda_simulation
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-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to led[1]
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-set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCQ128A
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-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
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-set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
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-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
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-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:scripts/preflow.tcl"
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-set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/postmodule.tcl"
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-set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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-set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
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-set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
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-set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
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-set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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-set_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"
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-set_global_assignment -name SAVE_DISK_SPACE OFF
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-set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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-set_global_assignment -name SMART_RECOMPILE ON
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-set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testclk -section_id eda_simulation
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-set_global_assignment -name EDA_TEST_BENCH_NAME testclk -section_id eda_simulation
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-set_global_assignment -name EDA_DESIGN_INSTANCE_NAME max80 -section_id testclk
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-set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ms" -section_id testclk
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-set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testclk -section_id testclk
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-set_global_assignment -name EDA_TEST_BENCH_FILE simulation/testclk.sv -section_id testclk
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-set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulation
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rtc_32khz
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hc
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hh
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdo
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tck
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdi
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tms
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-set_global_assignment -name OCP_HW_EVAL DISABLE
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-set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON
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-set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS ON
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-set_global_assignment -name POWER_REPORT_POWER_DISSIPATION ON
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-set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
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-set_global_assignment -name POWER_USE_TA_VALUE 35
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-set_location_assignment PLL_3 -to "max80:max80|pll3:pll3|altpll:altpll_component|pll3_altpll:auto_generated|pll1"
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-set_location_assignment PLL_4 -to "max80:max80|pll4:pll4|altpll:altpll_component|pll4_altpll:auto_generated|pll1"
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[15]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[14]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[13]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[12]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[11]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[10]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[9]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[8]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[7]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[6]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[5]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[4]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[3]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[2]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[1]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[0]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rngio[0]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rngio[1]
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-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rngio[2]
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-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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-set_global_assignment -name VERILOG_FILE usb/usb_desc.v
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-set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usb_cdc_core.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usbf_device_core.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE rng.sv
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-set_global_assignment -name QIP_FILE ip/int_osc/synthesis/int_osc.qip
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-set_global_assignment -name VERILOG_FILE ip/pll4.v
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-set_global_assignment -name VERILOG_FILE ip/pll3.v
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-set_global_assignment -name VERILOG_FILE usb/usb_fs_phy/src_v/usb_fs_phy.v
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-set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_tx.v
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-set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_rx.v
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-set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_defs.v
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-set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_crc16.v
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-set_global_assignment -name SYSTEMVERILOG_FILE usb/usb.sv
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-set_global_assignment -name VERILOG_INCLUDE_FILE usb/usbparam.vh
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-set_global_assignment -name SYSTEMVERILOG_FILE dcpktfifo.sv
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-set_global_assignment -name VERILOG_FILE ip/statusram.v
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-set_global_assignment -name VERILOG_INCLUDE_FILE iodevs.vh
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-set_global_assignment -name SYSTEMVERILOG_FILE serial.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE sdcard.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE sysclock.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE i2c.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE abcbus.sv
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-set_global_assignment -name VERILOG_FILE ip/abcmapram.v
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-set_global_assignment -name SYSTEMVERILOG_FILE fast_mem.sv
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-set_global_assignment -name MIF_FILE mif/sram.mif
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-set_global_assignment -name VERILOG_FILE picorv32.v
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-set_global_assignment -name SYSTEMVERILOG_FILE functions.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE spi_master.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE spirom.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE clkbuf.sv
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-set_global_assignment -name VERILOG_FILE ip/ddio_out.v
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-set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
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-set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl
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-set_global_assignment -name VERILOG_FILE ip/hdmitx.v
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-set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE video.sv
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-set_global_assignment -name SYSTEMVERILOG_FILE esp.sv
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-set_global_assignment -name SDC_FILE max80.sdc
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-set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
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-set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
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-set_global_assignment -name VERILOG_FILE ip/fifo.v
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-set_global_assignment -name VERILOG_FILE ip/ddufifo.v
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-set_global_assignment -name SYSTEMVERILOG_FILE vjtag_max80.sv
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-set_global_assignment -name VERILOG_FILE ip/vjtag/synthesis/vjtag.v
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-set_global_assignment -name QIP_FILE ip/vjtag/synthesis/vjtag.qip
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-set_global_assignment -name SYSTEMVERILOG_FILE fpgarst.sv
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-set_global_assignment -name VERILOG_FILE ip/altera_remote_update_core.v
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-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
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H. Peter Anvin