sdram: simpler implementation of the arbiter/multiplexer

Easier/more scalable implementation of the sdram arbiter/multiplexer.

fpga/output_files/max80.jdi

@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="82012839ae94794ce2bd"/>
+    <hash md5_digest_80b="37b389424706a6c44117"/>
   </project>
   <file_info>
     <file device="EP4CE15F17C8" path="max80.sof" usercode="0xFFFFFFFF"/>

fpga/sdram.sv

@@ -43,13 +43,13 @@ interface dram_bus;
    logic [1:0]	prio;		// Priority vs refresh
    logic        rst_n;
    logic        clk;
-   logic [24:0] addr;
+   tri   [24:0] addr;
    logic	addr0;		// addr[0] latched at transaction start
    logic [15:0] rd;
    logic	req;
    logic  [1:0]	rstrb;		// Data read strobe
-   logic [31:0] wd;
-   logic  [3:0] wstrb;
+   tri   [31:0] wd;
+   tri    [3:0] wstrb;
    logic	start;		// Transaction start
    logic	wrack;		// Transaction is a write
 
@@ -173,68 +173,32 @@ module dram_arbiter
     output logic do_rfsh
     );
 
-   logic [port_count:0] requesting;
-   logic [24:0] addr  [1:port_count];
-   logic [31:0] wd    [1:port_count];
-   logic [3:0]  wstrb [1:port_count];
-   logic [1:0]	prio  [1:port_count];
+   logic [port_count:0] grant;
+   assign grant[0] = 1'b0;	// Dummy to make the below logic simpler
 
-   always_comb
-     requesting[0] = 1'b0;
-
-   genvar  i;
    generate
+      genvar i;
       for (i = 1; i <= port_count; i++)
 	begin : u
-	   always_comb
-	     begin
-		ustr[i].rst_n = dstr.rst_n;
-		ustr[i].clk   = dstr.clk;
-		ustr[i].addr0 = dstr.addr0;
-		ustr[i].rd    = dstr.rd;
-		ustr[i].rstrb = dstr.rstrb;
-		ustr[i].wrack = dstr.wrack;
-		ustr[i].start = 1'b0;
-
-		addr[i]       = ustr[i].addr;
-		wd[i]         = ustr[i].wd;
-		wstrb[i]      = ustr[i].wstrb;
-		prio[i]       = ustr[i].prio;
-
-		if (~|requesting[i-1:0] & ustr[i].req)
-		  begin
-		     requesting[i] = 1'b1;
-		     ustr[i].start = dstr.start & (ustr[i].prio >= rfsh_prio);
-		  end
-		else
-		  begin
-		     requesting[i] = 1'b0;
-		     ustr[i].start = 1'b0;
-		  end
-	     end // always_comb
-	end // for (i = 1; i <= port_count; i++)
+	   assign ustr[i].rst_n = dstr.rst_n;
+	   assign ustr[i].clk   = dstr.clk;
+	   assign ustr[i].addr0 = dstr.addr0;
+	   assign ustr[i].rd    = dstr.rd;
+	   assign ustr[i].rstrb = dstr.rstrb;
+	   assign ustr[i].wrack = dstr.wrack;
+
+	   assign grant[i] = ~|grant[i-1:0] & ustr[i].req &
+			     (ustr[i].prio >= rfsh_prio);
+
+	   assign ustr[i].start = grant[i] & dstr.start;
+	   assign dstr.addr     = grant[i] ? ustr[i].addr  : 'z;
+	   assign dstr.wd       = grant[i] ? ustr[i].wd    : 'z;
+	   assign dstr.wstrb    = grant[i] ? ustr[i].wstrb : 'z;
+	end // block: u
    endgenerate
 
-   always_comb
-     begin
-	dstr.req   = 1'b0;
-	dstr.addr  = 25'bx;
-	dstr.wd    = 32'bx;
-	dstr.wstrb = 4'bx;
-	do_rfsh    = |rfsh_prio;
-
-	for (int j = 1; j <= port_count; j++)
-	  begin
-	     if (requesting[j])
-	       begin
-		  dstr.req   = 1'b1;
-		  dstr.addr  = addr[j];
-		  dstr.wd    = wd[j];
-		  dstr.wstrb = wstrb[j];
-		  do_rfsh    = prio[j] < rfsh_prio;
-	       end
-	  end // for (int j = 1; j <= port_count; j++)
-     end // always_comb
+   assign dstr.req =  |grant;
+   assign do_rfsh  = ~|grant & |rfsh_prio;
 endmodule // dram_arbiter
 
 module sdram