usbparam.vh: corect Verilog `define syntax

Verilog always confuses me where the backquotes go and don't go...

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

fpga/usb/usbparam.vh

@@ -1,2 +1,2 @@
 // Legal values are 3, 4, 5, or 6 for 8, 16, 32 or 64 bytes
-`define `USB_PACKET_BITS	6
+`define USB_PACKET_BITS	6