pll: change system clock to 84 MHz

Set the system clock to 84 MHz (half of the SDRAM speed) as that
seems to be the frequency that picorv32 can be realistically
synthesized at.

ip/pll.v

@@ -131,7 +131,7 @@ module pll (
 		altpll_component.clk0_duty_cycle = 50,
 		altpll_component.clk0_multiply_by = 7,
 		altpll_component.clk0_phase_shift = "0",
-		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_divide_by = 4,
 		altpll_component.clk1_duty_cycle = 50,
 		altpll_component.clk1_multiply_by = 7,
 		altpll_component.clk1_phase_shift = "0",
@@ -216,13 +216,13 @@ endmodule
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "4"
 // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "168.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "168.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "84.000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "48.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -257,7 +257,7 @@ endmodule
 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "168.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "168.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "84.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "48.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
@@ -315,7 +315,7 @@ endmodule
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"

max80.sv

@@ -122,16 +122,18 @@ module max80 (
    reg [reset_pow2-1:0]     rst_ctr = 1'b0;
    reg			    rst_n   = 1'b0;	// Internal reset
    wire [1:0]		    pll_locked;
-   wire			    sdram_clk;
-   wire			    clk;		// System clock
-   wire			    vid_clk;		// Video pixel clock
-   wire			    vid_hdmiclk;	// D:o in the HDMI clock domain
+
+   // Clocks
+   wire	    sdram_clk;
+   wire	    clk;		// System clock
+   wire	    vid_clk;		// Video pixel clock
+   wire	    vid_hdmiclk;	// D:o in the HDMI clock domain
 
    pll pll (
 	    .areset ( 1'b0 ),
 	    .inclk0 ( clock_48 ),
 	    .c0 ( sdram_clk ),		// SDRAM clock  (168 MHz)
-	    .c1 ( clk ),		// System clock (168 MHz)
+	    .c1 ( clk ),		// System clock (84 MHz)
 	    .c2 ( vid_clk ),		// Video pixel clock (48 MHz)
 	    .locked ( pll_locked[0] ),
 	    .phasestep ( 1'b0 ),

output_files/max80.map

@@ -10,7 +10,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 Notes:
 
-- Data checksum for this conversion is 0xF76073A6
+- Data checksum for this conversion is 0xF7602CD0
 
 - All the addresses in this file are byte addresses