sdram: fix some timing calculations, pre-ack, cleanups

- Fix some timing calculation errors (tREF was used where tRFC was
  supposed to be used.)
- Generate pipelined ACK signals, giving ACK for X cycles in
  advance.
- Cleanups; use enum for state machine.

max80.qsf

@@ -154,7 +154,7 @@ set_global_assignment -name SOURCE_FILE max80.pins
 set_global_assignment -name TCL_SCRIPT_FILE scripts/pins.tcl
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_global_assignment -name OPTIMIZATION_MODE BALANCED
 set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
 set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
 set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON

output_files/max80.map

@@ -10,7 +10,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 Notes:
 
-- Data checksum for this conversion is 0xF75F281E
+- Data checksum for this conversion is 0xF75F578A
 
 - All the addresses in this file are byte addresses
 

output_files/max80.map.eqn

@@ -19,25 +19,25 @@ DB1_dataout[0] = DDIO_OUT(.DATAINHI(GND), .DATAINLO(VCC), , , , );
 --F1_dram_a[0] is sdram:sdram|dram_a[0]
 --register power-up is low
 
-F1_dram_a[0] = DFFEAS(F1L65, T1_wire_pll1_clk[0], rst_n,  ,  , abc_a[1],  ,  , F1L232);
+F1_dram_a[0] = DFFEAS(F1L56, T1_wire_pll1_clk[0], rst_n,  ,  , abc_a[1],  ,  , F1L207);
 
 
 --F1_dram_a[1] is sdram:sdram|dram_a[1]
 --register power-up is low
 
-F1_dram_a[1] = DFFEAS(F1L68, T1_wire_pll1_clk[0], rst_n,  ,  , abc_a[2],  ,  , F1L232);
+F1_dram_a[1] = DFFEAS(F1L59, T1_wire_pll1_clk[0], rst_n,  ,  , abc_a[2],  ,  , F1L207);
 
 
 --F1_dram_dqm[0] is sdram:sdram|dram_dqm[0]
 --register power-up is low
 
-F1_dram_dqm[0] = DFFEAS(F1L48, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_state.st_p0_rd,  );
+F1_dram_dqm[0] = DFFEAS(F1L43, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_state.st_p0_rd,  );
 
 
 --F1_dram_dqm[1] is sdram:sdram|dram_dqm[1]
 --register power-up is low
 
-F1_dram_dqm[1] = DFFEAS(F1L47, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_state.st_p0_rd,  );
+F1_dram_dqm[1] = DFFEAS(F1L42, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_state.st_p0_rd,  );
 
 
 --led_ctr[26] is led_ctr[26]
@@ -93,63 +93,63 @@ T1_wire_pll1_clk[2] = EQUATION NOT SUPPORTED;
 --F1_op_cycle[0] is sdram:sdram|op_cycle[0]
 --register power-up is low
 
-F1_op_cycle[0] = DFFEAS(F1L164, T1_wire_pll1_clk[0], rst_n,  ,  , VCC,  ,  , F1L37);
+F1_op_cycle[0] = DFFEAS(F1L146, T1_wire_pll1_clk[0], rst_n,  ,  , VCC,  ,  , F1L35);
 
 
---F1_op_cycle[3] is sdram:sdram|op_cycle[3]
+--F1_op_cycle[1] is sdram:sdram|op_cycle[1]
 --register power-up is low
 
-F1_op_cycle[3] = DFFEAS(F1_op_cycle[3]_OTERM7, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+F1_op_cycle[1] = DFFEAS(F1L149, T1_wire_pll1_clk[0], rst_n,  ,  , A1L394,  ,  , F1L35);
 
 
---F1_op_cycle[2] is sdram:sdram|op_cycle[2]
+--F1_op_cycle[3] is sdram:sdram|op_cycle[3]
 --register power-up is low
 
-F1_op_cycle[2] = DFFEAS(F1_op_cycle[2]_OTERM5, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+F1_op_cycle[3] = DFFEAS(F1L155, T1_wire_pll1_clk[0], rst_n,  ,  , A1L394,  ,  , F1L35);
 
 
---F1_op_cycle[1] is sdram:sdram|op_cycle[1]
+--F1_op_cycle[2] is sdram:sdram|op_cycle[2]
 --register power-up is low
 
-F1_op_cycle[1] = DFFEAS(F1_op_cycle[1]_OTERM3, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+F1_op_cycle[2] = DFFEAS(F1L152, T1_wire_pll1_clk[0], rst_n,  ,  , A1L394,  ,  , F1L35);
 
 
 --F1_op_cycle[4] is sdram:sdram|op_cycle[4]
 --register power-up is low
 
-F1_op_cycle[4] = DFFEAS(F1_op_cycle[4]_OTERM1, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+F1_op_cycle[4] = DFFEAS(F1L158, T1_wire_pll1_clk[0], rst_n,  ,  , A1L394,  ,  , F1L35);
 
 
---F1L65 is sdram:sdram|dram_a[0]~0
-F1L65 = (F1_state.st_idle & ((F1L10))) # (!F1_state.st_idle & (F1L36));
+--F1L56 is sdram:sdram|dram_a[0]~0
+F1L56 = (F1_state.st_idle & ((F1L8))) # (!F1_state.st_idle & (F1L34));
 
 
---F1L68 is sdram:sdram|dram_a[1]~1
-F1L68 = (F1_state.st_idle & ((F1L9))) # (!F1_state.st_idle & (F1L36));
+--F1L59 is sdram:sdram|dram_a[1]~1
+F1L59 = (F1_state.st_idle & ((F1L7))) # (!F1_state.st_idle & (F1L34));
 
 
 --F1_init_ctr[15] is sdram:sdram|init_ctr[15]
 --register power-up is low
 
-F1_init_ctr[15] = DFFEAS(F1L159, T1_wire_pll1_clk[0], rst_n,  , F1L58,  ,  ,  ,  );
+F1_init_ctr[15] = DFFEAS(F1L142, T1_wire_pll1_clk[0], rst_n,  , F1L53,  ,  ,  ,  );
 
 
 --F1_rfsh_ctr[8] is sdram:sdram|rfsh_ctr[8]
 --register power-up is low
 
-F1_rfsh_ctr[8] = DFFEAS(F1L222, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[8] = DFFEAS(F1L197, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
 --F1_rfsh_ctr[9] is sdram:sdram|rfsh_ctr[9]
 --register power-up is low
 
-F1_rfsh_ctr[9] = DFFEAS(F1L225, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[9] = DFFEAS(F1L200, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
 --F1_state.st_rfsh is sdram:sdram|state.st_rfsh
 --register power-up is low
 
-F1_state.st_rfsh = DFFEAS(F1L247, T1_wire_pll1_clk[0], rst_n,  , F1L244,  ,  , !F1_state.st_idle,  );
+F1_state.st_rfsh = DFFEAS(F1L221, T1_wire_pll1_clk[0], rst_n,  , F1L218,  ,  , !F1_state.st_idle,  );
 
 
 --led_ctr[25] is led_ctr[25]
@@ -601,225 +601,219 @@ A1L22 = CARRY((rst_ctr[11] & !A1L20));
 A1L23 = A1L22;
 
 
---F1_wack0_q is sdram:sdram|wack0_q
---register power-up is low
-
-F1_wack0_q = DFFEAS(F1L7, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , !F1_state.st_p0_wr,  );
-
-
---F1L164 is sdram:sdram|op_cycle[0]~5
-F1L164 = F1_op_cycle[0] $ (VCC);
+--F1L146 is sdram:sdram|op_cycle[0]~5
+F1L146 = F1_op_cycle[0] $ (VCC);
 
---F1L165 is sdram:sdram|op_cycle[0]~6
-F1L165 = CARRY(F1_op_cycle[0]);
+--F1L147 is sdram:sdram|op_cycle[0]~6
+F1L147 = CARRY(F1_op_cycle[0]);
 
 
---F1L169 is sdram:sdram|op_cycle[1]~7
-F1L169 = (F1_op_cycle[1] & (!F1L165)) # (!F1_op_cycle[1] & ((F1L165) # (GND)));
+--F1L149 is sdram:sdram|op_cycle[1]~7
+F1L149 = (F1_op_cycle[1] & (!F1L147)) # (!F1_op_cycle[1] & ((F1L147) # (GND)));
 
---F1L170 is sdram:sdram|op_cycle[1]~8
-F1L170 = CARRY((!F1L165) # (!F1_op_cycle[1]));
+--F1L150 is sdram:sdram|op_cycle[1]~8
+F1L150 = CARRY((!F1L147) # (!F1_op_cycle[1]));
 
 
---F1L174 is sdram:sdram|op_cycle[2]~9
-F1L174 = (F1_op_cycle[2] & (F1L170 $ (GND))) # (!F1_op_cycle[2] & (!F1L170 & VCC));
+--F1L152 is sdram:sdram|op_cycle[2]~9
+F1L152 = (F1_op_cycle[2] & (F1L150 $ (GND))) # (!F1_op_cycle[2] & (!F1L150 & VCC));
 
---F1L175 is sdram:sdram|op_cycle[2]~10
-F1L175 = CARRY((F1_op_cycle[2] & !F1L170));
+--F1L153 is sdram:sdram|op_cycle[2]~10
+F1L153 = CARRY((F1_op_cycle[2] & !F1L150));
 
 
---F1L179 is sdram:sdram|op_cycle[3]~11
-F1L179 = (F1_op_cycle[3] & (!F1L175)) # (!F1_op_cycle[3] & ((F1L175) # (GND)));
+--F1L155 is sdram:sdram|op_cycle[3]~11
+F1L155 = (F1_op_cycle[3] & (!F1L153)) # (!F1_op_cycle[3] & ((F1L153) # (GND)));
 
---F1L180 is sdram:sdram|op_cycle[3]~12
-F1L180 = CARRY((!F1L175) # (!F1_op_cycle[3]));
+--F1L156 is sdram:sdram|op_cycle[3]~12
+F1L156 = CARRY((!F1L153) # (!F1_op_cycle[3]));
 
 
---F1L184 is sdram:sdram|op_cycle[4]~13
-F1L184 = F1_op_cycle[4] $ (!F1L180);
+--F1L158 is sdram:sdram|op_cycle[4]~13
+F1L158 = F1_op_cycle[4] $ (!F1L156);
 
 
 --F1_init_ctr[14] is sdram:sdram|init_ctr[14]
 --register power-up is low
 
-F1_init_ctr[14] = DFFEAS(F1L156, T1_wire_pll1_clk[0], rst_n,  , F1L58,  ,  ,  ,  );
+F1_init_ctr[14] = DFFEAS(F1L139, T1_wire_pll1_clk[0], rst_n,  , F1L53,  ,  ,  ,  );
 
 
 --F1_init_ctr[13] is sdram:sdram|init_ctr[13]
 --register power-up is low
 
-F1_init_ctr[13] = DFFEAS(F1L153, T1_wire_pll1_clk[0], rst_n,  , F1L58,  ,  ,  ,  );
+F1_init_ctr[13] = DFFEAS(F1L136, T1_wire_pll1_clk[0], rst_n,  , F1L53,  ,  ,  ,  );
 
 
 --F1_init_ctr[12] is sdram:sdram|init_ctr[12]
 --register power-up is low
 
-F1_init_ctr[12] = DFFEAS(F1L150, T1_wire_pll1_clk[0], rst_n,  , F1L58,  ,  ,  ,  );
+F1_init_ctr[12] = DFFEAS(F1L133, T1_wire_pll1_clk[0], rst_n,  , F1L53,  ,  ,  ,  );
 
 
 --F1_init_ctr[11] is sdram:sdram|init_ctr[11]
 --register power-up is low
 
-F1_init_ctr[11] = DFFEAS(F1L147, T1_wire_pll1_clk[0], rst_n,  , F1L58,  ,  ,  ,  );
+F1_init_ctr[11] = DFFEAS(F1L130, T1_wire_pll1_clk[0], rst_n,  , F1L53,  ,  ,  ,  );
 
 
---F1L147 is sdram:sdram|init_ctr[11]~5
-F1L147 = (F1_init_ctr[10] & (F1_init_ctr[11] $ (VCC))) # (!F1_init_ctr[10] & (F1_init_ctr[11] & VCC));
+--F1L130 is sdram:sdram|init_ctr[11]~5
+F1L130 = (F1_init_ctr[10] & (F1_init_ctr[11] $ (VCC))) # (!F1_init_ctr[10] & (F1_init_ctr[11] & VCC));
 
---F1L148 is sdram:sdram|init_ctr[11]~6
-F1L148 = CARRY((F1_init_ctr[10] & F1_init_ctr[11]));
+--F1L131 is sdram:sdram|init_ctr[11]~6
+F1L131 = CARRY((F1_init_ctr[10] & F1_init_ctr[11]));
 
 
---F1L150 is sdram:sdram|init_ctr[12]~7
-F1L150 = (F1_init_ctr[12] & (!F1L148)) # (!F1_init_ctr[12] & ((F1L148) # (GND)));
+--F1L133 is sdram:sdram|init_ctr[12]~7
+F1L133 = (F1_init_ctr[12] & (!F1L131)) # (!F1_init_ctr[12] & ((F1L131) # (GND)));
 
---F1L151 is sdram:sdram|init_ctr[12]~8
-F1L151 = CARRY((!F1L148) # (!F1_init_ctr[12]));
+--F1L134 is sdram:sdram|init_ctr[12]~8
+F1L134 = CARRY((!F1L131) # (!F1_init_ctr[12]));
 
 
---F1L153 is sdram:sdram|init_ctr[13]~9
-F1L153 = (F1_init_ctr[13] & (F1L151 $ (GND))) # (!F1_init_ctr[13] & (!F1L151 & VCC));
+--F1L136 is sdram:sdram|init_ctr[13]~9
+F1L136 = (F1_init_ctr[13] & (F1L134 $ (GND))) # (!F1_init_ctr[13] & (!F1L134 & VCC));
 
---F1L154 is sdram:sdram|init_ctr[13]~10
-F1L154 = CARRY((F1_init_ctr[13] & !F1L151));
+--F1L137 is sdram:sdram|init_ctr[13]~10
+F1L137 = CARRY((F1_init_ctr[13] & !F1L134));
 
 
---F1L156 is sdram:sdram|init_ctr[14]~11
-F1L156 = (F1_init_ctr[14] & (!F1L154)) # (!F1_init_ctr[14] & ((F1L154) # (GND)));
+--F1L139 is sdram:sdram|init_ctr[14]~11
+F1L139 = (F1_init_ctr[14] & (!F1L137)) # (!F1_init_ctr[14] & ((F1L137) # (GND)));
 
---F1L157 is sdram:sdram|init_ctr[14]~12
-F1L157 = CARRY((!F1L154) # (!F1_init_ctr[14]));
+--F1L140 is sdram:sdram|init_ctr[14]~12
+F1L140 = CARRY((!F1L137) # (!F1_init_ctr[14]));
 
 
---F1L159 is sdram:sdram|init_ctr[15]~13
-F1L159 = F1_init_ctr[15] $ (!F1L157);
+--F1L142 is sdram:sdram|init_ctr[15]~13
+F1L142 = F1_init_ctr[15] $ (!F1L140);
 
 
 --F1_rfsh_ctr[7] is sdram:sdram|rfsh_ctr[7]
 --register power-up is low
 
-F1_rfsh_ctr[7] = DFFEAS(F1L219, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[7] = DFFEAS(F1L194, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
 --F1_rfsh_ctr[6] is sdram:sdram|rfsh_ctr[6]
 --register power-up is low
 
-F1_rfsh_ctr[6] = DFFEAS(F1L216, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[6] = DFFEAS(F1L191, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
 --F1_rfsh_ctr[5] is sdram:sdram|rfsh_ctr[5]
 --register power-up is low
 
-F1_rfsh_ctr[5] = DFFEAS(F1L213, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[5] = DFFEAS(F1L188, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
 --F1_rfsh_ctr[4] is sdram:sdram|rfsh_ctr[4]
 --register power-up is low
 
-F1_rfsh_ctr[4] = DFFEAS(F1L210, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[4] = DFFEAS(F1L185, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
 --F1_rfsh_ctr[3] is sdram:sdram|rfsh_ctr[3]
 --register power-up is low
 
-F1_rfsh_ctr[3] = DFFEAS(F1L207, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[3] = DFFEAS(F1L182, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
 --F1_rfsh_ctr[2] is sdram:sdram|rfsh_ctr[2]
 --register power-up is low
 
-F1_rfsh_ctr[2] = DFFEAS(F1L204, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[2] = DFFEAS(F1L179, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
 --F1_rfsh_ctr[1] is sdram:sdram|rfsh_ctr[1]
 --register power-up is low
 
-F1_rfsh_ctr[1] = DFFEAS(F1L201, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[1] = DFFEAS(F1L176, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
 --F1_rfsh_ctr[0] is sdram:sdram|rfsh_ctr[0]
 --register power-up is low
 
-F1_rfsh_ctr[0] = DFFEAS(F1L198, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_is_rfsh,  );
+F1_rfsh_ctr[0] = DFFEAS(F1L173, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  , F1_dram_cmd[4],  );
 
 
---F1L198 is sdram:sdram|rfsh_ctr[0]~10
-F1L198 = F1_rfsh_ctr[0] $ (VCC);
+--F1L173 is sdram:sdram|rfsh_ctr[0]~10
+F1L173 = F1_rfsh_ctr[0] $ (VCC);
 
---F1L199 is sdram:sdram|rfsh_ctr[0]~11
-F1L199 = CARRY(F1_rfsh_ctr[0]);
+--F1L174 is sdram:sdram|rfsh_ctr[0]~11
+F1L174 = CARRY(F1_rfsh_ctr[0]);
 
 
---F1L201 is sdram:sdram|rfsh_ctr[1]~12
-F1L201 = (F1_rfsh_ctr[1] & (!F1L199)) # (!F1_rfsh_ctr[1] & ((F1L199) # (GND)));
+--F1L176 is sdram:sdram|rfsh_ctr[1]~12
+F1L176 = (F1_rfsh_ctr[1] & (!F1L174)) # (!F1_rfsh_ctr[1] & ((F1L174) # (GND)));
 
---F1L202 is sdram:sdram|rfsh_ctr[1]~13
-F1L202 = CARRY((!F1L199) # (!F1_rfsh_ctr[1]));
+--F1L177 is sdram:sdram|rfsh_ctr[1]~13
+F1L177 = CARRY((!F1L174) # (!F1_rfsh_ctr[1]));
 
 
---F1L204 is sdram:sdram|rfsh_ctr[2]~14
-F1L204 = (F1_rfsh_ctr[2] & (F1L202 $ (GND))) # (!F1_rfsh_ctr[2] & (!F1L202 & VCC));
+--F1L179 is sdram:sdram|rfsh_ctr[2]~14
+F1L179 = (F1_rfsh_ctr[2] & (F1L177 $ (GND))) # (!F1_rfsh_ctr[2] & (!F1L177 & VCC));
 
---F1L205 is sdram:sdram|rfsh_ctr[2]~15
-F1L205 = CARRY((F1_rfsh_ctr[2] & !F1L202));
+--F1L180 is sdram:sdram|rfsh_ctr[2]~15
+F1L180 = CARRY((F1_rfsh_ctr[2] & !F1L177));
 
 
---F1L207 is sdram:sdram|rfsh_ctr[3]~16
-F1L207 = (F1_rfsh_ctr[3] & (!F1L205)) # (!F1_rfsh_ctr[3] & ((F1L205) # (GND)));
+--F1L182 is sdram:sdram|rfsh_ctr[3]~16
+F1L182 = (F1_rfsh_ctr[3] & (!F1L180)) # (!F1_rfsh_ctr[3] & ((F1L180) # (GND)));
 
---F1L208 is sdram:sdram|rfsh_ctr[3]~17
-F1L208 = CARRY((!F1L205) # (!F1_rfsh_ctr[3]));
+--F1L183 is sdram:sdram|rfsh_ctr[3]~17
+F1L183 = CARRY((!F1L180) # (!F1_rfsh_ctr[3]));
 
 
---F1L210 is sdram:sdram|rfsh_ctr[4]~18
-F1L210 = (F1_rfsh_ctr[4] & (F1L208 $ (GND))) # (!F1_rfsh_ctr[4] & (!F1L208 & VCC));
+--F1L185 is sdram:sdram|rfsh_ctr[4]~18
+F1L185 = (F1_rfsh_ctr[4] & (F1L183 $ (GND))) # (!F1_rfsh_ctr[4] & (!F1L183 & VCC));
 
---F1L211 is sdram:sdram|rfsh_ctr[4]~19
-F1L211 = CARRY((F1_rfsh_ctr[4] & !F1L208));
+--F1L186 is sdram:sdram|rfsh_ctr[4]~19
+F1L186 = CARRY((F1_rfsh_ctr[4] & !F1L183));
 
 
---F1L213 is sdram:sdram|rfsh_ctr[5]~20
-F1L213 = (F1_rfsh_ctr[5] & (!F1L211)) # (!F1_rfsh_ctr[5] & ((F1L211) # (GND)));
+--F1L188 is sdram:sdram|rfsh_ctr[5]~20
+F1L188 = (F1_rfsh_ctr[5] & (!F1L186)) # (!F1_rfsh_ctr[5] & ((F1L186) # (GND)));
 
---F1L214 is sdram:sdram|rfsh_ctr[5]~21
-F1L214 = CARRY((!F1L211) # (!F1_rfsh_ctr[5]));
+--F1L189 is sdram:sdram|rfsh_ctr[5]~21
+F1L189 = CARRY((!F1L186) # (!F1_rfsh_ctr[5]));
 
 
---F1L216 is sdram:sdram|rfsh_ctr[6]~22
-F1L216 = (F1_rfsh_ctr[6] & (F1L214 $ (GND))) # (!F1_rfsh_ctr[6] & (!F1L214 & VCC));
+--F1L191 is sdram:sdram|rfsh_ctr[6]~22
+F1L191 = (F1_rfsh_ctr[6] & (F1L189 $ (GND))) # (!F1_rfsh_ctr[6] & (!F1L189 & VCC));
 
---F1L217 is sdram:sdram|rfsh_ctr[6]~23
-F1L217 = CARRY((F1_rfsh_ctr[6] & !F1L214));
+--F1L192 is sdram:sdram|rfsh_ctr[6]~23
+F1L192 = CARRY((F1_rfsh_ctr[6] & !F1L189));
 
 
---F1L219 is sdram:sdram|rfsh_ctr[7]~24
-F1L219 = (F1_rfsh_ctr[7] & (!F1L217)) # (!F1_rfsh_ctr[7] & ((F1L217) # (GND)));
+--F1L194 is sdram:sdram|rfsh_ctr[7]~24
+F1L194 = (F1_rfsh_ctr[7] & (!F1L192)) # (!F1_rfsh_ctr[7] & ((F1L192) # (GND)));
 
---F1L220 is sdram:sdram|rfsh_ctr[7]~25
-F1L220 = CARRY((!F1L217) # (!F1_rfsh_ctr[7]));
+--F1L195 is sdram:sdram|rfsh_ctr[7]~25
+F1L195 = CARRY((!F1L192) # (!F1_rfsh_ctr[7]));
 
 
---F1L222 is sdram:sdram|rfsh_ctr[8]~26
-F1L222 = (F1_rfsh_ctr[8] & (F1L220 $ (GND))) # (!F1_rfsh_ctr[8] & (!F1L220 & VCC));
+--F1L197 is sdram:sdram|rfsh_ctr[8]~26
+F1L197 = (F1_rfsh_ctr[8] & (F1L195 $ (GND))) # (!F1_rfsh_ctr[8] & (!F1L195 & VCC));
 
---F1L223 is sdram:sdram|rfsh_ctr[8]~27
-F1L223 = CARRY((F1_rfsh_ctr[8] & !F1L220));
+--F1L198 is sdram:sdram|rfsh_ctr[8]~27
+F1L198 = CARRY((F1_rfsh_ctr[8] & !F1L195));
 
 
---F1L225 is sdram:sdram|rfsh_ctr[9]~28
-F1L225 = F1_rfsh_ctr[9] $ (F1L223);
+--F1L200 is sdram:sdram|rfsh_ctr[9]~28
+F1L200 = F1_rfsh_ctr[9] $ (F1L198);
 
 
 --B1_qreg[6] is tmdsenc:hdmitmds[0].enc|qreg[6]
 --register power-up is low
 
-B1_qreg[6] = DFFEAS(B1L62, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
+B1_qreg[6] = DFFEAS(B1L58, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
 
 
 --B2_qreg[0] is tmdsenc:hdmitmds[1].enc|qreg[0]
 --register power-up is low
 
-B2_qreg[0] = DFFEAS(B2L60, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B2_qreg[0] = DFFEAS(B2L59, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B3_qreg[0] is tmdsenc:hdmitmds[2].enc|qreg[0]
@@ -855,55 +849,55 @@ B3_disparity[2] = DFFEAS(B3L39, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_
 --B1_disparity[3] is tmdsenc:hdmitmds[0].enc|disparity[3]
 --register power-up is low
 
-B1_disparity[3] = DFFEAS(B1L47, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B1_disparity[3] = DFFEAS(B1L43, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B1_disparity[0] is tmdsenc:hdmitmds[0].enc|disparity[0]
 --register power-up is low
 
-B1_disparity[0] = DFFEAS(B1L38, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B1_disparity[0] = DFFEAS(B1L34, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B1_disparity[1] is tmdsenc:hdmitmds[0].enc|disparity[1]
 --register power-up is low
 
-B1_disparity[1] = DFFEAS(B1L41, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B1_disparity[1] = DFFEAS(B1L37, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B1_disparity[2] is tmdsenc:hdmitmds[0].enc|disparity[2]
 --register power-up is low
 
-B1_disparity[2] = DFFEAS(B1L44, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B1_disparity[2] = DFFEAS(B1L40, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B2_qreg[4] is tmdsenc:hdmitmds[1].enc|qreg[4]
 --register power-up is low
 
-B2_qreg[4] = DFFEAS(B2L63, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
+B2_qreg[4] = DFFEAS(B2L62, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
 
 
 --B2_disparity[3] is tmdsenc:hdmitmds[1].enc|disparity[3]
 --register power-up is low
 
-B2_disparity[3] = DFFEAS(B2L44, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B2_disparity[3] = DFFEAS(B2L43, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B2_disparity[0] is tmdsenc:hdmitmds[1].enc|disparity[0]
 --register power-up is low
 
-B2_disparity[0] = DFFEAS(B2L35, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B2_disparity[0] = DFFEAS(B2L34, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B2_disparity[1] is tmdsenc:hdmitmds[1].enc|disparity[1]
 --register power-up is low
 
-B2_disparity[1] = DFFEAS(B2L38, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B2_disparity[1] = DFFEAS(B2L37, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B2_disparity[2] is tmdsenc:hdmitmds[1].enc|disparity[2]
 --register power-up is low
 
-B2_disparity[2] = DFFEAS(B2L41, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B2_disparity[2] = DFFEAS(B2L40, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B3_qreg[4] is tmdsenc:hdmitmds[2].enc|qreg[4]
@@ -921,38 +915,41 @@ B3_qreg[1] = DFFEAS(B3L61, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denre
 --B1_qreg[0] is tmdsenc:hdmitmds[0].enc|qreg[0]
 --register power-up is low
 
-B1_qreg[0] = DFFEAS(B1L66, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B1_qreg[0] = DFFEAS(B1L62, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B3L32 is tmdsenc:hdmitmds[2].enc|disparity[0]~5
-B3L32 = CARRY(B3L20);
+B3L32 = CARRY(B3L26);
 
 
 --B3L33 is tmdsenc:hdmitmds[2].enc|disparity[0]~6
-B3L33 = (B3L26 & ((B3_disparity[0] & (B3L32 & VCC)) # (!B3_disparity[0] & (!B3L32)))) # (!B3L26 & ((B3_disparity[0] & (!B3L32)) # (!B3_disparity[0] & ((B3L32) # (GND)))));
+B3L33 = (B3L23 & ((B3_disparity[0] & (B3L32 & VCC)) # (!B3_disparity[0] & (!B3L32)))) # (!B3L23 & ((B3_disparity[0] & (!B3L32)) # (!B3_disparity[0] & ((B3L32) # (GND)))));
 
 --B3L34 is tmdsenc:hdmitmds[2].enc|disparity[0]~7
-B3L34 = CARRY((B3L26 & (!B3_disparity[0] & !B3L32)) # (!B3L26 & ((!B3L32) # (!B3_disparity[0]))));
+B3L34 = CARRY((B3L23 & (!B3_disparity[0] & !B3L32)) # (!B3L23 & ((!B3L32) # (!B3_disparity[0]))));
 
 
 --B3L36 is tmdsenc:hdmitmds[2].enc|disparity[1]~8
-B3L36 = ((B3L25 $ (B3_disparity[1] $ (!B3L34)))) # (GND);
+B3L36 = ((B3L22 $ (B3_disparity[1] $ (!B3L34)))) # (GND);
 
 --B3L37 is tmdsenc:hdmitmds[2].enc|disparity[1]~9
-B3L37 = CARRY((B3L25 & ((B3_disparity[1]) # (!B3L34))) # (!B3L25 & (B3_disparity[1] & !B3L34)));
+B3L37 = CARRY((B3L22 & ((B3_disparity[1]) # (!B3L34))) # (!B3L22 & (B3_disparity[1] & !B3L34)));
 
 
 --B3L39 is tmdsenc:hdmitmds[2].enc|disparity[2]~10
-B3L39 = (B3L23 & ((B3_disparity[2] & (B3L37 & VCC)) # (!B3_disparity[2] & (!B3L37)))) # (!B3L23 & ((B3_disparity[2] & (!B3L37)) # (!B3_disparity[2] & ((B3L37) # (GND)))));
+B3L39 = (B3L20 & ((B3_disparity[2] & (B3L37 & VCC)) # (!B3_disparity[2] & (!B3L37)))) # (!B3L20 & ((B3_disparity[2] & (!B3L37)) # (!B3_disparity[2] & ((B3L37) # (GND)))));
 
 --B3L40 is tmdsenc:hdmitmds[2].enc|disparity[2]~11
-B3L40 = CARRY((B3L23 & (!B3_disparity[2] & !B3L37)) # (!B3L23 & ((!B3L37) # (!B3_disparity[2]))));
+B3L40 = CARRY((B3L20 & (!B3_disparity[2] & !B3L37)) # (!B3L20 & ((!B3L37) # (!B3_disparity[2]))));
 
 
 --B3L42 is tmdsenc:hdmitmds[2].enc|disparity[3]~12
-B3L42 = B3L19 $ (B3_disparity[3] $ (!B3L40));
+B3L42 = B3L18 $ (B3_disparity[3] $ (!B3L40));
 
 
+--L2_wire_counter_comb_bita_0combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_0combout[0]
+L2_wire_counter_comb_bita_0combout[0] = L2_counter_reg_bit[0] $ (((VCC) # (!J1_sync_dffe12a)));
+
 --L2_wire_counter_comb_bita_0cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|wire_counter_comb_bita_0cout[0]
 L2_wire_counter_comb_bita_0cout[0] = CARRY(L2_counter_reg_bit[0] $ (!J1_sync_dffe12a));
 
@@ -975,81 +972,84 @@ L2_wire_counter_comb_bita_2cout[0] = CARRY((!L2_wire_counter_comb_bita_1cout[0]
 L2L24 = L2_wire_counter_comb_bita_2cout[0];
 
 
---B1L37 is tmdsenc:hdmitmds[0].enc|disparity[0]~5
-B1L37 = CARRY(B1L28);
+--B1L33 is tmdsenc:hdmitmds[0].enc|disparity[0]~5
+B1L33 = CARRY(B1L25);
 
 
---B1L38 is tmdsenc:hdmitmds[0].enc|disparity[0]~6
-B1L38 = (B1L26 & ((B1_disparity[0] & (B1L37 & VCC)) # (!B1_disparity[0] & (!B1L37)))) # (!B1L26 & ((B1_disparity[0] & (!B1L37)) # (!B1_disparity[0] & ((B1L37) # (GND)))));
+--B1L34 is tmdsenc:hdmitmds[0].enc|disparity[0]~6
+B1L34 = (B1L23 & ((B1_disparity[0] & (B1L33 & VCC)) # (!B1_disparity[0] & (!B1L33)))) # (!B1L23 & ((B1_disparity[0] & (!B1L33)) # (!B1_disparity[0] & ((B1L33) # (GND)))));
 
---B1L39 is tmdsenc:hdmitmds[0].enc|disparity[0]~7
-B1L39 = CARRY((B1L26 & (!B1_disparity[0] & !B1L37)) # (!B1L26 & ((!B1L37) # (!B1_disparity[0]))));
+--B1L35 is tmdsenc:hdmitmds[0].enc|disparity[0]~7
+B1L35 = CARRY((B1L23 & (!B1_disparity[0] & !B1L33)) # (!B1L23 & ((!B1L33) # (!B1_disparity[0]))));
 
 
---B1L41 is tmdsenc:hdmitmds[0].enc|disparity[1]~8
-B1L41 = ((B1L25 $ (B1_disparity[1] $ (!B1L39)))) # (GND);
+--B1L37 is tmdsenc:hdmitmds[0].enc|disparity[1]~8
+B1L37 = ((B1L22 $ (B1_disparity[1] $ (!B1L35)))) # (GND);
 
---B1L42 is tmdsenc:hdmitmds[0].enc|disparity[1]~9
-B1L42 = CARRY((B1L25 & ((B1_disparity[1]) # (!B1L39))) # (!B1L25 & (B1_disparity[1] & !B1L39)));
+--B1L38 is tmdsenc:hdmitmds[0].enc|disparity[1]~9
+B1L38 = CARRY((B1L22 & ((B1_disparity[1]) # (!B1L35))) # (!B1L22 & (B1_disparity[1] & !B1L35)));
 
 
---B1L44 is tmdsenc:hdmitmds[0].enc|disparity[2]~10
-B1L44 = (B1L22 & ((B1_disparity[2] & (B1L42 & VCC)) # (!B1_disparity[2] & (!B1L42)))) # (!B1L22 & ((B1_disparity[2] & (!B1L42)) # (!B1_disparity[2] & ((B1L42) # (GND)))));
+--B1L40 is tmdsenc:hdmitmds[0].enc|disparity[2]~10
+B1L40 = (B1L20 & ((B1_disparity[2] & (B1L38 & VCC)) # (!B1_disparity[2] & (!B1L38)))) # (!B1L20 & ((B1_disparity[2] & (!B1L38)) # (!B1_disparity[2] & ((B1L38) # (GND)))));
 
---B1L45 is tmdsenc:hdmitmds[0].enc|disparity[2]~11
-B1L45 = CARRY((B1L22 & (!B1_disparity[2] & !B1L42)) # (!B1L22 & ((!B1L42) # (!B1_disparity[2]))));
+--B1L41 is tmdsenc:hdmitmds[0].enc|disparity[2]~11
+B1L41 = CARRY((B1L20 & (!B1_disparity[2] & !B1L38)) # (!B1L20 & ((!B1L38) # (!B1_disparity[2]))));
 
 
---B1L47 is tmdsenc:hdmitmds[0].enc|disparity[3]~12
-B1L47 = B1L19 $ (B1_disparity[3] $ (!B1L45));
+--B1L43 is tmdsenc:hdmitmds[0].enc|disparity[3]~12
+B1L43 = B1L17 $ (B1_disparity[3] $ (!B1L41));
 
 
---B2L34 is tmdsenc:hdmitmds[1].enc|disparity[0]~5
-B2L34 = CARRY(B2L28);
+--B2L33 is tmdsenc:hdmitmds[1].enc|disparity[0]~5
+B2L33 = CARRY(B2L26);
 
 
---B2L35 is tmdsenc:hdmitmds[1].enc|disparity[0]~6
-B2L35 = (B2L26 & ((B2_disparity[0] & (B2L34 & VCC)) # (!B2_disparity[0] & (!B2L34)))) # (!B2L26 & ((B2_disparity[0] & (!B2L34)) # (!B2_disparity[0] & ((B2L34) # (GND)))));
+--B2L34 is tmdsenc:hdmitmds[1].enc|disparity[0]~6
+B2L34 = (B2L25 & ((B2_disparity[0] & (B2L33 & VCC)) # (!B2_disparity[0] & (!B2L33)))) # (!B2L25 & ((B2_disparity[0] & (!B2L33)) # (!B2_disparity[0] & ((B2L33) # (GND)))));
 
---B2L36 is tmdsenc:hdmitmds[1].enc|disparity[0]~7
-B2L36 = CARRY((B2L26 & (!B2_disparity[0] & !B2L34)) # (!B2L26 & ((!B2L34) # (!B2_disparity[0]))));
+--B2L35 is tmdsenc:hdmitmds[1].enc|disparity[0]~7
+B2L35 = CARRY((B2L25 & (!B2_disparity[0] & !B2L33)) # (!B2L25 & ((!B2L33) # (!B2_disparity[0]))));
 
 
---B2L38 is tmdsenc:hdmitmds[1].enc|disparity[1]~8
-B2L38 = ((B2L25 $ (B2_disparity[1] $ (!B2L36)))) # (GND);
+--B2L37 is tmdsenc:hdmitmds[1].enc|disparity[1]~8
+B2L37 = ((B2L24 $ (B2_disparity[1] $ (!B2L35)))) # (GND);
 
---B2L39 is tmdsenc:hdmitmds[1].enc|disparity[1]~9
-B2L39 = CARRY((B2L25 & ((B2_disparity[1]) # (!B2L36))) # (!B2L25 & (B2_disparity[1] & !B2L36)));
+--B2L38 is tmdsenc:hdmitmds[1].enc|disparity[1]~9
+B2L38 = CARRY((B2L24 & ((B2_disparity[1]) # (!B2L35))) # (!B2L24 & (B2_disparity[1] & !B2L35)));
 
 
---B2L41 is tmdsenc:hdmitmds[1].enc|disparity[2]~10
-B2L41 = (B2L23 & ((B2_disparity[2] & (B2L39 & VCC)) # (!B2_disparity[2] & (!B2L39)))) # (!B2L23 & ((B2_disparity[2] & (!B2L39)) # (!B2_disparity[2] & ((B2L39) # (GND)))));
+--B2L40 is tmdsenc:hdmitmds[1].enc|disparity[2]~10
+B2L40 = (B2L22 & ((B2_disparity[2] & (B2L38 & VCC)) # (!B2_disparity[2] & (!B2L38)))) # (!B2L22 & ((B2_disparity[2] & (!B2L38)) # (!B2_disparity[2] & ((B2L38) # (GND)))));
 
---B2L42 is tmdsenc:hdmitmds[1].enc|disparity[2]~11
-B2L42 = CARRY((B2L23 & (!B2_disparity[2] & !B2L39)) # (!B2L23 & ((!B2L39) # (!B2_disparity[2]))));
+--B2L41 is tmdsenc:hdmitmds[1].enc|disparity[2]~11
+B2L41 = CARRY((B2L22 & (!B2_disparity[2] & !B2L38)) # (!B2L22 & ((!B2L38) # (!B2_disparity[2]))));
 
 
---B2L44 is tmdsenc:hdmitmds[1].enc|disparity[3]~12
-B2L44 = B2L21 $ (B2_disparity[3] $ (!B2L42));
+--B2L43 is tmdsenc:hdmitmds[1].enc|disparity[3]~12
+B2L43 = B2L19 $ (B2_disparity[3] $ (!B2L41));
 
 
 --B1_qreg[4] is tmdsenc:hdmitmds[0].enc|qreg[4]
 --register power-up is low
 
-B1_qreg[4] = DFFEAS(B1L67, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
+B1_qreg[4] = DFFEAS(B1L63, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
 
 
 --B1_qreg[1] is tmdsenc:hdmitmds[0].enc|qreg[1]
 --register power-up is low
 
-B1_qreg[1] = DFFEAS(B1L68, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B1_qreg[1] = DFFEAS(B1L64, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
 
 
 --B2_qreg[1] is tmdsenc:hdmitmds[1].enc|qreg[1]
 --register power-up is low
 
-B2_qreg[1] = DFFEAS(B2L65, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+B2_qreg[1] = DFFEAS(B2L64, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  , !B1_denreg,  );
+
 
+--L1_wire_counter_comb_bita_0combout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_0combout[0]
+L1_wire_counter_comb_bita_0combout[0] = L1_counter_reg_bit[0] $ (((VCC) # (!J1_sync_dffe12a)));
 
 --L1_wire_counter_comb_bita_0cout[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|wire_counter_comb_bita_0cout[0]
 L1_wire_counter_comb_bita_0cout[0] = CARRY(L1_counter_reg_bit[0] $ (!J1_sync_dffe12a));
@@ -1076,7 +1076,7 @@ L1L24 = L1_wire_counter_comb_bita_2cout[0];
 --B2_qreg[2] is tmdsenc:hdmitmds[1].enc|qreg[2]
 --register power-up is low
 
-B2_qreg[2] = DFFEAS(B2L68, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
+B2_qreg[2] = DFFEAS(B2L67, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
 
 
 --B3_qreg[2] is tmdsenc:hdmitmds[2].enc|qreg[2]
@@ -1088,7 +1088,7 @@ B3_qreg[2] = DFFEAS(B3L66, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_
 --B2_qreg[6] is tmdsenc:hdmitmds[1].enc|qreg[6]
 --register power-up is low
 
-B2_qreg[6] = DFFEAS(B2L70, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
+B2_qreg[6] = DFFEAS(B2L69, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
 
 
 --B3_qreg[6] is tmdsenc:hdmitmds[2].enc|qreg[6]
@@ -1100,3508 +1100,3446 @@ B3_qreg[6] = DFFEAS(B3L67, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_
 --B1_qreg[2] is tmdsenc:hdmitmds[0].enc|qreg[2]
 --register power-up is low
 
-B1_qreg[2] = DFFEAS(B1L73, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
+B1_qreg[2] = DFFEAS(B1L69, T1_wire_pll1_clk[2], vid_rst_n,  ,  , VCC,  ,  , !B1_denreg);
 
 
---A1L92 is abc_rdy_x~output
-A1L92 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
-
+--abc_clk is abc_clk
+abc_clk = INPUT();
 
---A1L94 is abc_resin_x~output
-A1L94 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--abc_d_oe is abc_d_oe
+abc_d_oe = OUTPUT(A1L107);
 
---A1L79 is abc_int80_x~output
-A1L79 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--abc_rst_n is abc_rst_n
+abc_rst_n = INPUT();
 
---A1L81 is abc_int800_x~output
-A1L81 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--abc_cs_n is abc_cs_n
+abc_cs_n = INPUT();
 
---A1L84 is abc_nmi_x~output
-A1L84 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--abc_out_n[0] is abc_out_n[0]
+abc_out_n[0] = INPUT();
 
---A1L102 is abc_xm_x~output
-A1L102 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--abc_out_n[1] is abc_out_n[1]
+abc_out_n[1] = INPUT();
 
---A1L194 is hdmi_sda~output
-A1L194 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--abc_out_n[2] is abc_out_n[2]
+abc_out_n[2] = INPUT();
 
---A1L48 is abc_d[0]~output
-A1L48 = OUTPUT_BUFFER.O(.I(abc_do[0]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
+--abc_out_n[3] is abc_out_n[3]
+abc_out_n[3] = INPUT();
 
---A1L50 is abc_d[1]~output
-A1L50 = OUTPUT_BUFFER.O(.I(abc_do[1]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
+--abc_out_n[4] is abc_out_n[4]
+abc_out_n[4] = INPUT();
 
---A1L52 is abc_d[2]~output
-A1L52 = OUTPUT_BUFFER.O(.I(abc_do[2]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
+--abc_inp_n[0] is abc_inp_n[0]
+abc_inp_n[0] = INPUT();
 
---A1L54 is abc_d[3]~output
-A1L54 = OUTPUT_BUFFER.O(.I(abc_do[3]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
+--abc_inp_n[1] is abc_inp_n[1]
+abc_inp_n[1] = INPUT();
 
---A1L56 is abc_d[4]~output
-A1L56 = OUTPUT_BUFFER.O(.I(abc_do[4]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
+--abc_rdy_x is abc_rdy_x
+abc_rdy_x = OUTPUT(A1L92);
 
---A1L58 is abc_d[5]~output
-A1L58 = OUTPUT_BUFFER.O(.I(abc_do[5]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
+--A1L92 is abc_rdy_x~output
+A1L92 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---A1L60 is abc_d[6]~output
-A1L60 = OUTPUT_BUFFER.O(.I(abc_do[6]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
+--abc_resin_x is abc_resin_x
+abc_resin_x = OUTPUT(A1L94);
 
---A1L62 is abc_d[7]~output
-A1L62 = OUTPUT_BUFFER.O(.I(abc_do[7]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
+--A1L94 is abc_resin_x~output
+A1L94 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---A1L154 is exth_ha~output
-A1L154 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--abc_int80_x is abc_int80_x
+abc_int80_x = OUTPUT(A1L79);
 
---A1L156 is exth_hb~output
-A1L156 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--A1L79 is abc_int80_x~output
+A1L79 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---A1L159 is exth_hd~output
-A1L159 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--abc_int800_x is abc_int800_x
+abc_int800_x = OUTPUT(A1L81);
 
---A1L161 is exth_he~output
-A1L161 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--A1L81 is abc_int800_x~output
+A1L81 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---A1L163 is exth_hf~output
-A1L163 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--abc_nmi_x is abc_nmi_x
+abc_nmi_x = OUTPUT(A1L84);
 
---A1L165 is exth_hg~output
-A1L165 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--A1L84 is abc_nmi_x~output
+A1L84 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---A1L352 is sr_dq[0]~output
-A1L352 = OUTPUT_BUFFER.O(.I(F1_dram_d[0]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--abc_xm_x is abc_xm_x
+abc_xm_x = OUTPUT(A1L102);
 
---A1L354 is sr_dq[1]~output
-A1L354 = OUTPUT_BUFFER.O(.I(F1_dram_d[1]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--A1L102 is abc_xm_x~output
+A1L102 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---A1L356 is sr_dq[2]~output
-A1L356 = OUTPUT_BUFFER.O(.I(F1_dram_d[2]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--abc_master is abc_master
+abc_master = OUTPUT(A1L394);
 
---A1L358 is sr_dq[3]~output
-A1L358 = OUTPUT_BUFFER.O(.I(F1_dram_d[3]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--abc_a_oe is abc_a_oe
+abc_a_oe = OUTPUT(A1L394);
 
---A1L360 is sr_dq[4]~output
-A1L360 = OUTPUT_BUFFER.O(.I(F1_dram_d[4]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--abc_d_ce_n is abc_d_ce_n
+abc_d_ce_n = OUTPUT(A1L394);
 
---A1L362 is sr_dq[5]~output
-A1L362 = OUTPUT_BUFFER.O(.I(F1_dram_d[5]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--exth_hc is exth_hc
+exth_hc = INPUT();
 
---A1L364 is sr_dq[6]~output
-A1L364 = OUTPUT_BUFFER.O(.I(F1_dram_d[6]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--exth_hh is exth_hh
+exth_hh = INPUT();
 
---A1L366 is sr_dq[7]~output
-A1L366 = OUTPUT_BUFFER.O(.I(F1_dram_d[7]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--sr_clk is sr_clk
+sr_clk = OUTPUT(DB1_dataout[0]);
 
---A1L368 is sr_dq[8]~output
-A1L368 = OUTPUT_BUFFER.O(.I(F1_dram_d[8]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--sr_cke is sr_cke
+sr_cke = OUTPUT(F1_dram_cke);
 
---A1L370 is sr_dq[9]~output
-A1L370 = OUTPUT_BUFFER.O(.I(F1_dram_d[9]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--sr_ba[0] is sr_ba[0]
+sr_ba[0] = OUTPUT(F1_dram_ba[0]);
 
---A1L372 is sr_dq[10]~output
-A1L372 = OUTPUT_BUFFER.O(.I(F1_dram_d[10]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--sr_ba[1] is sr_ba[1]
+sr_ba[1] = OUTPUT(F1_dram_ba[1]);
 
---A1L374 is sr_dq[11]~output
-A1L374 = OUTPUT_BUFFER.O(.I(F1_dram_d[11]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--sr_a[0] is sr_a[0]
+sr_a[0] = OUTPUT(F1_dram_a[0]);
 
---A1L376 is sr_dq[12]~output
-A1L376 = OUTPUT_BUFFER.O(.I(F1_dram_d[12]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--sr_a[1] is sr_a[1]
+sr_a[1] = OUTPUT(F1_dram_a[1]);
 
---A1L378 is sr_dq[13]~output
-A1L378 = OUTPUT_BUFFER.O(.I(F1_dram_d[13]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--sr_a[2] is sr_a[2]
+sr_a[2] = OUTPUT(F1_dram_a[2]);
 
---A1L380 is sr_dq[14]~output
-A1L380 = OUTPUT_BUFFER.O(.I(F1_dram_d[14]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--sr_a[3] is sr_a[3]
+sr_a[3] = OUTPUT(F1_dram_a[3]);
 
---A1L382 is sr_dq[15]~output
-A1L382 = OUTPUT_BUFFER.O(.I(F1_dram_d[15]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
+--sr_a[4] is sr_a[4]
+sr_a[4] = OUTPUT(F1_dram_a[4]);
 
---A1L312 is sd_dat[0]~output
-A1L312 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_a[5] is sr_a[5]
+sr_a[5] = OUTPUT(F1_dram_a[5]);
 
---A1L314 is sd_dat[1]~output
-A1L314 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_a[6] is sr_a[6]
+sr_a[6] = OUTPUT(F1_dram_a[6]);
 
---A1L316 is sd_dat[2]~output
-A1L316 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_a[7] is sr_a[7]
+sr_a[7] = OUTPUT(F1_dram_a[7]);
 
---A1L318 is sd_dat[3]~output
-A1L318 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_a[8] is sr_a[8]
+sr_a[8] = OUTPUT(F1_dram_a[8]);
 
---A1L320 is spi_clk~output
-A1L320 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_a[9] is sr_a[9]
+sr_a[9] = OUTPUT(A1L394);
 
---A1L326 is spi_miso~output
-A1L326 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_a[10] is sr_a[10]
+sr_a[10] = OUTPUT(F1_dram_a[10]);
 
---A1L328 is spi_mosi~output
-A1L328 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_a[11] is sr_a[11]
+sr_a[11] = OUTPUT(A1L394);
 
---A1L322 is spi_cs_esp_n~output
-A1L322 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_a[12] is sr_a[12]
+sr_a[12] = OUTPUT(A1L394);
 
---A1L324 is spi_cs_flash_n~output
-A1L324 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_dqm[0] is sr_dqm[0]
+sr_dqm[0] = OUTPUT(F1_dram_dqm[0]);
 
---A1L152 is esp_io0~output
-A1L152 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_dqm[1] is sr_dqm[1]
+sr_dqm[1] = OUTPUT(F1_dram_dqm[1]);
 
---A1L150 is esp_int~output
-A1L150 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_cs_n is sr_cs_n
+sr_cs_n = OUTPUT(F1L84);
 
---A1L196 is i2c_scl~output
-A1L196 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_we_n is sr_we_n
+sr_we_n = OUTPUT(F1L75);
 
---A1L198 is i2c_sda~output
-A1L198 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_cas_n is sr_cas_n
+sr_cas_n = OUTPUT(F1L77);
 
---A1L173 is gpio[0]~output
-A1L173 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sr_ras_n is sr_ras_n
+sr_ras_n = OUTPUT(F1L79);
 
---A1L175 is gpio[1]~output
-A1L175 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sd_clk is sd_clk
+sd_clk = OUTPUT(A1L395);
 
---A1L177 is gpio[2]~output
-A1L177 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--sd_cmd is sd_cmd
+sd_cmd = OUTPUT(A1L395);
 
---A1L179 is gpio[3]~output
-A1L179 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--tty_txd is tty_txd
+tty_txd = INPUT();
 
---A1L181 is gpio[4]~output
-A1L181 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--tty_rxd is tty_rxd
+tty_rxd = OUTPUT(A1L395);
 
---A1L183 is gpio[5]~output
-A1L183 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--tty_rts is tty_rts
+tty_rts = INPUT();
 
---A1L192 is hdmi_scl~output
-A1L192 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--tty_cts is tty_cts
+tty_cts = OUTPUT(A1L395);
 
---A1L190 is hdmi_hpd~output
-A1L190 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
+--tty_dtr is tty_dtr
+tty_dtr = INPUT();
 
---F1_dram_cke is sdram:sdram|dram_cke
---register power-up is low
 
-F1_dram_cke = DFFEAS(VCC, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--flash_cs_n is flash_cs_n
+flash_cs_n = OUTPUT(A1L394);
 
 
---F1_dram_ba[0] is sdram:sdram|dram_ba[0]
---register power-up is low
+--flash_clk is flash_clk
+flash_clk = OUTPUT(A1L394);
 
-F1_dram_ba[0] = DFFEAS(F1L46, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--flash_mosi is flash_mosi
+flash_mosi = OUTPUT(A1L394);
 
---F1_dram_ba[1] is sdram:sdram|dram_ba[1]
---register power-up is low
 
-F1_dram_ba[1] = DFFEAS(F1L44, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--flash_miso is flash_miso
+flash_miso = INPUT();
 
 
---F1_dram_a[2] is sdram:sdram|dram_a[2]
---register power-up is low
-
-F1_dram_a[2] = DFFEAS(F1L34, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--rtc_32khz is rtc_32khz
+rtc_32khz = INPUT();
 
 
---F1_dram_a[3] is sdram:sdram|dram_a[3]
---register power-up is low
+--rtc_int_n is rtc_int_n
+rtc_int_n = INPUT();
 
-F1_dram_a[3] = DFFEAS(F1L33, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--led[1] is led[1]
+led[1] = OUTPUT(led_ctr[26]);
 
---F1_dram_a[4] is sdram:sdram|dram_a[4]
---register power-up is low
 
-F1_dram_a[4] = DFFEAS(F1L32, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--led[2] is led[2]
+led[2] = OUTPUT(led_ctr[27]);
 
 
---F1_dram_a[5] is sdram:sdram|dram_a[5]
---register power-up is low
+--led[3] is led[3]
+led[3] = OUTPUT(led_ctr[28]);
 
-F1_dram_a[5] = DFFEAS(F1L31, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--hdmi_d[0] is hdmi_d[0]
+hdmi_d[0] = OUTPUT(M1_wire_ddio_outa_dataout[0]);
 
---F1_dram_a[6] is sdram:sdram|dram_a[6]
---register power-up is low
 
-F1_dram_a[6] = DFFEAS(F1L30, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--hdmi_d[1] is hdmi_d[1]
+hdmi_d[1] = OUTPUT(M1_wire_ddio_outa_dataout[1]);
 
 
---F1_dram_a[7] is sdram:sdram|dram_a[7]
---register power-up is low
+--hdmi_d[2] is hdmi_d[2]
+hdmi_d[2] = OUTPUT(M1_wire_ddio_outa_dataout[2]);
 
-F1_dram_a[7] = DFFEAS(F1L29, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--hdmi_clk is hdmi_clk
+hdmi_clk = OUTPUT(P1_wire_ddio_outa_dataout[0]);
 
---F1_dram_a[8] is sdram:sdram|dram_a[8]
---register power-up is low
 
-F1_dram_a[8] = DFFEAS(F1L28, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--hdmi_sda is hdmi_sda
+hdmi_sda = BIDIR(A1L194);
 
 
---F1_dram_a[10] is sdram:sdram|dram_a[10]
---register power-up is low
+--A1L194 is hdmi_sda~output
+A1L194 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
-F1_dram_a[10] = DFFEAS(F1L27, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--abc_d[0] is abc_d[0]
+abc_d[0] = BIDIR(A1L48);
 
---F1_dram_cmd[3] is sdram:sdram|dram_cmd[3]
---register power-up is low
 
-F1_dram_cmd[3] = DFFEAS(F1_dram_cmd[3]_OTERM11, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--A1L48 is abc_d[0]~output
+A1L48 = OUTPUT_BUFFER.O(.I(abc_do[0]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
 
---F1_dram_cmd[0] is sdram:sdram|dram_cmd[0]
---register power-up is low
+--abc_d[1] is abc_d[1]
+abc_d[1] = BIDIR(A1L50);
 
-F1_dram_cmd[0] = DFFEAS(F1L20, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--A1L50 is abc_d[1]~output
+A1L50 = OUTPUT_BUFFER.O(.I(abc_do[1]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
---F1_dram_cmd[2] is sdram:sdram|dram_cmd[2]
---register power-up is low
 
-F1_dram_cmd[2] = DFFEAS(F1_dram_cmd[2]_OTERM9, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--abc_d[2] is abc_d[2]
+abc_d[2] = BIDIR(A1L52);
 
 
---rst_n is rst_n
---register power-up is low
+--A1L52 is abc_d[2]~output
+A1L52 = OUTPUT_BUFFER.O(.I(abc_do[2]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
-rst_n = DFFEAS(A1L305, T1_wire_pll1_clk[1], !A1L25,  ,  ,  ,  ,  ,  );
 
+--abc_d[3] is abc_d[3]
+abc_d[3] = BIDIR(A1L54);
 
---F1_state.st_idle is sdram:sdram|state.st_idle
---register power-up is low
 
-F1_state.st_idle = DFFEAS(F1L240, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--A1L54 is abc_d[3]~output
+A1L54 = OUTPUT_BUFFER.O(.I(abc_do[3]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
 
---abc_rrq is abc_rrq
---register power-up is low
+--abc_d[4] is abc_d[4]
+abc_d[4] = BIDIR(A1L56);
 
-abc_rrq = DFFEAS(A1L96, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--A1L56 is abc_d[4]~output
+A1L56 = OUTPUT_BUFFER.O(.I(abc_do[4]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
---abc_wrq is abc_wrq
---register power-up is low
 
-abc_wrq = DFFEAS(A1L99, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--abc_d[5] is abc_d[5]
+abc_d[5] = BIDIR(A1L58);
 
 
---F1L45 is sdram:sdram|Selector40~2
-F1L45 = (F1_state.st_idle & ((abc_rrq) # (abc_wrq)));
+--A1L58 is abc_d[5]~output
+A1L58 = OUTPUT_BUFFER.O(.I(abc_do[5]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
 
---F1_state.st_p0_rd is sdram:sdram|state.st_p0_rd
---register power-up is low
+--abc_d[6] is abc_d[6]
+abc_d[6] = BIDIR(A1L60);
 
-F1_state.st_p0_rd = DFFEAS(F1L242, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--A1L60 is abc_d[6]~output
+A1L60 = OUTPUT_BUFFER.O(.I(abc_do[6]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
---F1_state.st_p0_wr is sdram:sdram|state.st_p0_wr
---register power-up is low
 
-F1_state.st_p0_wr = DFFEAS(F1L243, T1_wire_pll1_clk[0], rst_n,  , F1L244,  ,  ,  ,  );
+--abc_d[7] is abc_d[7]
+abc_d[7] = BIDIR(A1L62);
 
 
---F1L232 is sdram:sdram|state.st_reset~0
-F1L232 = (F1_state.st_p0_rd) # (F1_state.st_p0_wr);
+--A1L62 is abc_d[7]~output
+A1L62 = OUTPUT_BUFFER.O(.I(abc_do[7]), .OE(!abc_xmemfl_n), , , , , , , , , , , , , , , , );
 
 
---F1L59 is sdram:sdram|always1~2
-F1L59 = (F1_op_cycle[0] & !F1_op_cycle[3]);
+--exth_ha is exth_ha
+exth_ha = BIDIR(A1L154);
 
 
---F1L60 is sdram:sdram|always1~3
-F1L60 = (F1_op_cycle[2] & !F1_op_cycle[1]);
+--A1L154 is exth_ha~output
+A1L154 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
 
---F1_state.st_init is sdram:sdram|state.st_init
---register power-up is low
+--exth_hb is exth_hb
+exth_hb = BIDIR(A1L156);
 
-F1_state.st_init = DFFEAS(F1L246, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--A1L156 is exth_hb~output
+A1L156 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L35 is sdram:sdram|Selector29~6
-F1L35 = (F1_state.st_init & F1_op_cycle[4]);
 
+--exth_hd is exth_hd
+exth_hd = BIDIR(A1L159);
 
---F1L10 is sdram:sdram|Selector11~0
-F1L10 = (abc_a[12] & ((abc_rrq) # (abc_wrq)));
 
+--A1L159 is exth_hd~output
+A1L159 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L9 is sdram:sdram|Selector10~0
-F1L9 = (abc_a[13] & ((abc_rrq) # (abc_wrq)));
 
+--exth_he is exth_he
+exth_he = BIDIR(A1L161);
 
---F1L34 is sdram:sdram|Selector27~0
-F1L34 = (F1L232 & (((abc_a[3])))) # (!F1L232 & (F1L45 & (abc_a[14])));
 
+--A1L161 is exth_he~output
+A1L161 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L33 is sdram:sdram|Selector26~0
-F1L33 = (F1L232 & (((abc_a[4])))) # (!F1L232 & (F1L45 & (abc_a[15])));
 
+--exth_hf is exth_hf
+exth_hf = BIDIR(A1L163);
 
---F1L30 is sdram:sdram|Selector23~0
-F1L30 = (abc_a[7] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
 
+--A1L163 is exth_hf~output
+A1L163 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L29 is sdram:sdram|Selector22~0
-F1L29 = (abc_a[8] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
 
+--exth_hg is exth_hg
+exth_hg = BIDIR(A1L165);
 
---F1L28 is sdram:sdram|Selector21~0
-F1L28 = (abc_a[9] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
 
+--A1L165 is exth_hg~output
+A1L165 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1_state.st_reset is sdram:sdram|state.st_reset
---register power-up is low
 
-F1_state.st_reset = DFFEAS(F1L248, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--sr_dq[0] is sr_dq[0]
+sr_dq[0] = BIDIR(A1L352);
 
 
---F1L27 is sdram:sdram|Selector19~0
-F1L27 = (F1_init_ctr[15] & !F1_state.st_reset);
+--A1L352 is sr_dq[0]~output
+A1L352 = OUTPUT_BUFFER.O(.I(F1_dram_d[0]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---F1L1 is sdram:sdram|Equal3~0
-F1L1 = (F1_op_cycle[3] & (F1_op_cycle[1] & (!F1_op_cycle[0] & !F1_op_cycle[4])));
+--sr_dq[1] is sr_dq[1]
+sr_dq[1] = BIDIR(A1L354);
 
 
---F1L48 is sdram:sdram|Selector42~0
-F1L48 = (F1_op_cycle[2]) # ((abc_a[0]) # ((!F1L1) # (!F1_state.st_p0_wr)));
+--A1L354 is sr_dq[1]~output
+A1L354 = OUTPUT_BUFFER.O(.I(F1_dram_d[1]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---F1L47 is sdram:sdram|Selector41~0
-F1L47 = (F1_op_cycle[2]) # (((!abc_a[0]) # (!F1L1)) # (!F1_state.st_p0_wr));
+--sr_dq[2] is sr_dq[2]
+sr_dq[2] = BIDIR(A1L356);
 
 
---F1L11 is sdram:sdram|Selector14~2
-F1L11 = (!abc_rrq & (!abc_wrq & (!F1_rfsh_ctr[8] & !F1_rfsh_ctr[9])));
+--A1L356 is sr_dq[2]~output
+A1L356 = OUTPUT_BUFFER.O(.I(F1_dram_d[2]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---F1L12 is sdram:sdram|Selector14~3
-F1L12 = (!F1_state.st_reset & !F1_init_ctr[15]);
+--sr_dq[3] is sr_dq[3]
+sr_dq[3] = BIDIR(A1L358);
 
 
---F1L2 is sdram:sdram|Equal3~1
-F1L2 = (F1L1 & !F1_op_cycle[2]);
+--A1L358 is sr_dq[3]~output
+A1L358 = OUTPUT_BUFFER.O(.I(F1_dram_d[3]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---F1L3 is sdram:sdram|Equal4~0
-F1L3 = (!F1_op_cycle[4] & (F1_op_cycle[0] & (!F1_op_cycle[3] & F1L5)));
+--sr_dq[4] is sr_dq[4]
+sr_dq[4] = BIDIR(A1L360);
 
 
---F1L61 is sdram:sdram|always1~4
-F1L61 = (F1_op_cycle[0] & (!F1_op_cycle[3] & (!F1_op_cycle[2] & F1_op_cycle[1]))) # (!F1_op_cycle[0] & (F1_op_cycle[3] & (F1_op_cycle[2] & !F1_op_cycle[1])));
+--A1L360 is sr_dq[4]~output
+A1L360 = OUTPUT_BUFFER.O(.I(F1_dram_d[4]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---F1L99 is sdram:sdram|dram_cmd[3]~0
-F1L99 = (F1_state.st_init & (((!F1_op_cycle[4]) # (!F1L60)) # (!F1L59)));
+--sr_dq[5] is sr_dq[5]
+sr_dq[5] = BIDIR(A1L362);
 
 
---F1L100 is sdram:sdram|dram_cmd[3]~1
-F1L100 = (!F1_state.st_rfsh & (((F1L61 & !F1_op_cycle[4])) # (!F1L99)));
+--A1L362 is sr_dq[5]~output
+A1L362 = OUTPUT_BUFFER.O(.I(F1_dram_d[5]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---F1L101 is sdram:sdram|dram_cmd[3]~2
-F1L101 = (F1L100 & (((F1L2) # (F1L3)) # (!F1L232)));
+--sr_dq[6] is sr_dq[6]
+sr_dq[6] = BIDIR(A1L364);
 
 
---F1L20 is sdram:sdram|Selector17~4
-F1L20 = (F1L24 & (F1L26 & ((F1L3) # (F1L22))));
+--A1L364 is sr_dq[6]~output
+A1L364 = OUTPUT_BUFFER.O(.I(F1_dram_d[6]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---F1L17 is sdram:sdram|Selector16~0
-F1L17 = (F1L232 & (!F1L2 & ((F1L3) # (!F1L19))));
+--sr_dq[7] is sr_dq[7]
+sr_dq[7] = BIDIR(A1L366);
 
 
---F1L57 is sdram:sdram|WideOr5~0
-F1L57 = (abc_rrq) # ((abc_wrq) # ((!F1_rfsh_ctr[8] & !F1_rfsh_ctr[9])));
+--A1L366 is sr_dq[7]~output
+A1L366 = OUTPUT_BUFFER.O(.I(F1_dram_d[7]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---F1L18 is sdram:sdram|Selector16~1
-F1L18 = (F1L17) # (((F1_state.st_idle & F1L57)) # (!F1_state.st_reset));
+--sr_dq[8] is sr_dq[8]
+sr_dq[8] = BIDIR(A1L368);
 
 
---F1L19 is sdram:sdram|Selector16~2
-F1L19 = (!F1_dram_cmd[1]_OTERM17 & ((F1_dram_cmd[1]_OTERM13) # (F1_dram_cmd[1]_OTERM15)));
+--A1L368 is sr_dq[8]~output
+A1L368 = OUTPUT_BUFFER.O(.I(F1_dram_d[8]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---F1L13 is sdram:sdram|Selector14~4
-F1L13 = (F1_state.st_idle & F1L11);
+--sr_dq[9] is sr_dq[9]
+sr_dq[9] = BIDIR(A1L370);
 
 
---F1L15 is sdram:sdram|Selector15~2
-F1L15 = (F1_state.st_reset & (F1L232 & (!F1_state.st_init & !F1L3)));
+--A1L370 is sr_dq[9]~output
+A1L370 = OUTPUT_BUFFER.O(.I(F1_dram_d[9]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---led_ctr[0] is led_ctr[0]
---register power-up is low
+--sr_dq[10] is sr_dq[10]
+sr_dq[10] = BIDIR(A1L372);
 
-led_ctr[0] = DFFEAS(A1L205, T1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );
 
+--A1L372 is sr_dq[10]~output
+A1L372 = OUTPUT_BUFFER.O(.I(F1_dram_d[10]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
---Q2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]
---register power-up is low
 
-Q2_shift_reg[0] = DFFEAS(Q2L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--sr_dq[11] is sr_dq[11]
+sr_dq[11] = BIDIR(A1L374);
 
 
---Q1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]
---register power-up is low
+--A1L374 is sr_dq[11]~output
+A1L374 = OUTPUT_BUFFER.O(.I(F1_dram_d[11]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
-Q1_shift_reg[0] = DFFEAS(Q1L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--sr_dq[12] is sr_dq[12]
+sr_dq[12] = BIDIR(A1L376);
 
---Q4_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]
---register power-up is low
 
-Q4_shift_reg[0] = DFFEAS(Q4L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--A1L376 is sr_dq[12]~output
+A1L376 = OUTPUT_BUFFER.O(.I(F1_dram_d[12]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---Q3_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]
---register power-up is low
+--sr_dq[13] is sr_dq[13]
+sr_dq[13] = BIDIR(A1L378);
 
-Q3_shift_reg[0] = DFFEAS(Q3L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--A1L378 is sr_dq[13]~output
+A1L378 = OUTPUT_BUFFER.O(.I(F1_dram_d[13]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
---Q6_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]
---register power-up is low
 
-Q6_shift_reg[0] = DFFEAS(Q6L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--sr_dq[14] is sr_dq[14]
+sr_dq[14] = BIDIR(A1L380);
 
 
---Q5_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]
---register power-up is low
+--A1L380 is sr_dq[14]~output
+A1L380 = OUTPUT_BUFFER.O(.I(F1_dram_d[14]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
-Q5_shift_reg[0] = DFFEAS(Q5L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--sr_dq[15] is sr_dq[15]
+sr_dq[15] = BIDIR(A1L382);
 
---N2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]
---register power-up is low
 
-N2_shift_reg[0] = DFFEAS(N2L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--A1L382 is sr_dq[15]~output
+A1L382 = OUTPUT_BUFFER.O(.I(F1_dram_d[15]), .OE(!F1_dram_d_en), , , , , , , , , , , , , , , , );
 
 
---N1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]
---register power-up is low
+--sd_dat[0] is sd_dat[0]
+sd_dat[0] = BIDIR(A1L312);
 
-N1_shift_reg[0] = DFFEAS(N1L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--A1L312 is sd_dat[0]~output
+A1L312 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---rst_ctr[11] is rst_ctr[11]
---register power-up is low
 
-rst_ctr[11] = DFFEAS(A1L21, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
+--sd_dat[1] is sd_dat[1]
+sd_dat[1] = BIDIR(A1L314);
 
 
---rst_ctr[10] is rst_ctr[10]
---register power-up is low
+--A1L314 is sd_dat[1]~output
+A1L314 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
-rst_ctr[10] = DFFEAS(A1L19, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
+--sd_dat[2] is sd_dat[2]
+sd_dat[2] = BIDIR(A1L316);
 
---rst_ctr[9] is rst_ctr[9]
---register power-up is low
 
-rst_ctr[9] = DFFEAS(A1L17, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
+--A1L316 is sd_dat[2]~output
+A1L316 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
 
---rst_ctr[8] is rst_ctr[8]
---register power-up is low
+--sd_dat[3] is sd_dat[3]
+sd_dat[3] = BIDIR(A1L318);
 
-rst_ctr[8] = DFFEAS(A1L15, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
+--A1L318 is sd_dat[3]~output
+A1L318 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---rst_ctr[7] is rst_ctr[7]
---register power-up is low
 
-rst_ctr[7] = DFFEAS(A1L13, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
+--spi_clk is spi_clk
+spi_clk = BIDIR(A1L320);
 
 
---rst_ctr[6] is rst_ctr[6]
---register power-up is low
+--A1L320 is spi_clk~output
+A1L320 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
-rst_ctr[6] = DFFEAS(A1L11, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
+--spi_miso is spi_miso
+spi_miso = BIDIR(A1L326);
 
---rst_ctr[5] is rst_ctr[5]
---register power-up is low
 
-rst_ctr[5] = DFFEAS(A1L9, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
+--A1L326 is spi_miso~output
+A1L326 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
 
---rst_ctr[4] is rst_ctr[4]
---register power-up is low
-
-rst_ctr[4] = DFFEAS(A1L7, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
+--spi_mosi is spi_mosi
+spi_mosi = BIDIR(A1L328);
 
 
---rst_ctr[3] is rst_ctr[3]
---register power-up is low
+--A1L328 is spi_mosi~output
+A1L328 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
-rst_ctr[3] = DFFEAS(A1L5, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
+--spi_cs_esp_n is spi_cs_esp_n
+spi_cs_esp_n = BIDIR(A1L322);
 
---rst_ctr[2] is rst_ctr[2]
---register power-up is low
 
-rst_ctr[2] = DFFEAS(A1L3, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
+--A1L322 is spi_cs_esp_n~output
+A1L322 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
 
---rst_ctr[0] is rst_ctr[0]
---register power-up is low
+--spi_cs_flash_n is spi_cs_flash_n
+spi_cs_flash_n = BIDIR(A1L324);
 
-rst_ctr[0] = DFFEAS(A1L292, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
+--A1L324 is spi_cs_flash_n~output
+A1L324 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---rst_ctr[1] is rst_ctr[1]
---register power-up is low
 
-rst_ctr[1] = DFFEAS(A1L1, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
+--esp_io0 is esp_io0
+esp_io0 = BIDIR(A1L152);
 
 
---A1L305 is rst_n~0
-A1L305 = (rst_n) # (A1L23);
+--A1L152 is esp_io0~output
+A1L152 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
 
---J1_pll_lock_sync is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|pll_lock_sync
---register power-up is low
+--esp_int is esp_int
+esp_int = BIDIR(A1L150);
 
-J1_pll_lock_sync = DFFEAS(VCC, J1_wire_lvds_tx_pll_locked, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--A1L150 is esp_int~output
+A1L150 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---A1L25 is WideAnd0~0
-A1L25 = ((!J1_pll_lock_sync) # (!J1_wire_lvds_tx_pll_locked)) # (!T1_wire_pll1_locked);
 
+--i2c_scl is i2c_scl
+i2c_scl = BIDIR(A1L196);
 
---F1L233 is sdram:sdram|state.st_reset~2
-F1L233 = (!F1_state.st_rfsh & (F1_state.st_reset & (!F1_state.st_p0_rd & F1L235)));
 
+--A1L196 is i2c_scl~output
+A1L196 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L236 is sdram:sdram|state.st_reset~3
-F1L236 = (F1_state.st_reset & ((F1_state.st_p0_rd & (!F1_state.st_p0_wr & !F1_state.st_rfsh)) # (!F1_state.st_p0_rd & (F1_state.st_p0_wr $ (F1_state.st_rfsh))))) # (!F1_state.st_reset & (!F1_state.st_p0_rd & (!F1_state.st_p0_wr & !F1_state.st_rfsh)));
 
+--i2c_sda is i2c_sda
+i2c_sda = BIDIR(A1L198);
 
---F1L237 is sdram:sdram|state.st_reset~4
-F1L237 = (F1L233) # ((F1L236 & (!F1_state.st_idle & !F1_state.st_init)));
 
+--A1L198 is i2c_sda~output
+A1L198 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L37 is sdram:sdram|Selector37~0
-F1L37 = (F1_state.st_idle) # (!F1_state.st_reset);
 
+--gpio[0] is gpio[0]
+gpio[0] = BIDIR(A1L173);
 
---F1L38 is sdram:sdram|Selector37~1
-F1L38 = (F1_state.st_init & (F1_op_cycle[4] & ((F1_op_cycle[3]) # (F1L40))));
 
+--A1L173 is gpio[0]~output
+A1L173 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L6 is sdram:sdram|Equal6~0
-F1L6 = (!F1_op_cycle[1] & !F1_op_cycle[2]);
 
+--gpio[1] is gpio[1]
+gpio[1] = BIDIR(A1L175);
 
---F1L8 is sdram:sdram|LessThan4~0
-F1L8 = (!F1_op_cycle[4] & (((F1L6 & !F1_op_cycle[0])) # (!F1_op_cycle[3])));
 
+--A1L175 is gpio[1]~output
+A1L175 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L41 is sdram:sdram|Selector37~2
-F1L41 = (!F1_state.st_p0_rd & (!F1_state.st_p0_wr & !F1_state.st_rfsh));
 
+--gpio[2] is gpio[2]
+gpio[2] = BIDIR(A1L177);
 
---F1L42 is sdram:sdram|Selector37~3
-F1L42 = (!F1L37 & ((F1L38) # ((!F1L8 & !F1L41))));
 
+--A1L177 is gpio[2]~output
+A1L177 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L239 is sdram:sdram|state~24
-F1L239 = (!F1_state.st_idle & ((F1_state.st_reset) # (!F1_init_ctr[15])));
 
+--gpio[3] is gpio[3]
+gpio[3] = BIDIR(A1L179);
 
---F1L240 is sdram:sdram|state~25
-F1L240 = (F1L237 & ((F1L13) # ((F1L42 & F1L239))));
 
+--A1L179 is gpio[3]~output
+A1L179 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---abc_xmemrd_q is abc_xmemrd_q
---register power-up is low
 
-abc_xmemrd_q = DFFEAS(A1L109, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--gpio[4] is gpio[4]
+gpio[4] = BIDIR(A1L181);
 
 
---abc_xmem_done is abc_xmem_done
---register power-up is low
+--A1L181 is gpio[4]~output
+A1L181 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
-abc_xmem_done = DFFEAS(A1L105, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--gpio[5] is gpio[5]
+gpio[5] = BIDIR(A1L183);
 
---F1_rack0_q is sdram:sdram|rack0_q
---register power-up is low
 
-F1_rack0_q = DFFEAS(F1L187, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--A1L183 is gpio[5]~output
+A1L183 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
 
---A1L96 is abc_rrq~0
-A1L96 = (abc_xmemrd_q & (!abc_xmem_done & !F1_rack0_q));
+--hdmi_scl is hdmi_scl
+hdmi_scl = BIDIR(A1L192);
 
 
---abc_xmemwr_q is abc_xmemwr_q
---register power-up is low
+--A1L192 is hdmi_scl~output
+A1L192 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
-abc_xmemwr_q = DFFEAS(A1L113, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--hdmi_hpd is hdmi_hpd
+hdmi_hpd = BIDIR(A1L190);
 
---A1L99 is abc_wrq~0
-A1L99 = (abc_xmemwr_q & (!abc_xmem_done & !F1_wack0_q));
 
+--A1L190 is hdmi_hpd~output
+A1L190 = OUTPUT_BUFFER.O(.I(VCC), , , , , , , , , , , , , , , , , );
 
---F1L241 is sdram:sdram|state~26
-F1L241 = (abc_rrq & (F1_state.st_idle & !abc_wrq));
 
+--abc_xmemfl_n is abc_xmemfl_n
+abc_xmemfl_n = INPUT();
 
---F1L242 is sdram:sdram|state~27
-F1L242 = (F1L237 & ((F1L241) # ((F1_state.st_p0_rd & F1L8))));
 
+--F1_dram_cke is sdram:sdram|dram_cke
+--register power-up is low
 
---F1L243 is sdram:sdram|state~28
-F1L243 = (abc_wrq & (F1_state.st_idle & F1L233));
+F1_dram_cke = DFFEAS(VCC, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---F1L244 is sdram:sdram|state~29
-F1L244 = (F1L42) # ((!F1L239) # (!F1L237));
+--F1_dram_ba[0] is sdram:sdram|dram_ba[0]
+--register power-up is low
 
+F1_dram_ba[0] = DFFEAS(F1L41, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
---F1L245 is sdram:sdram|state~30
-F1L245 = (F1_state.st_init & (((F1_init_ctr[15] & !F1_state.st_reset)) # (!F1L42))) # (!F1_state.st_init & (F1_init_ctr[15] & ((!F1_state.st_reset))));
 
+--F1_dram_ba[1] is sdram:sdram|dram_ba[1]
+--register power-up is low
 
---F1L246 is sdram:sdram|state~31
-F1L246 = (F1L237 & (F1L245 & !F1_state.st_idle));
+F1_dram_ba[1] = DFFEAS(F1L39, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---F1_init_ctr[10] is sdram:sdram|init_ctr[10]
+--F1_dram_a[2] is sdram:sdram|dram_a[2]
 --register power-up is low
 
-F1_init_ctr[10] = DFFEAS(F1L145, T1_wire_pll1_clk[0], rst_n,  , F1L58,  ,  ,  ,  );
+F1_dram_a[2] = DFFEAS(F1L33, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---F1_init_ctr[9] is sdram:sdram|init_ctr[9]
+--F1_dram_a[3] is sdram:sdram|dram_a[3]
 --register power-up is low
 
-F1_init_ctr[9] = DFFEAS(F1_rfsh_ctr[9], T1_wire_pll1_clk[0], rst_n,  , F1L58,  ,  ,  ,  );
+F1_dram_a[3] = DFFEAS(F1L32, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---F1L58 is sdram:sdram|always0~0
-F1L58 = F1_rfsh_ctr[9] $ (F1_init_ctr[9]);
+--F1_dram_a[4] is sdram:sdram|dram_a[4]
+--register power-up is low
 
+F1_dram_a[4] = DFFEAS(F1L31, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
---F1_is_rfsh is sdram:sdram|is_rfsh
+
+--F1_dram_a[5] is sdram:sdram|dram_a[5]
 --register power-up is low
 
-F1_is_rfsh = DFFEAS(F1L43, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+F1_dram_a[5] = DFFEAS(F1L30, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---F1L247 is sdram:sdram|state~32
-F1L247 = (F1L237 & !F1L57);
+--F1_dram_a[6] is sdram:sdram|dram_a[6]
+--register power-up is low
 
+F1_dram_a[6] = DFFEAS(F1L29, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
---J1_tx_reg[8] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]
+
+--F1_dram_a[7] is sdram:sdram|dram_a[7]
 --register power-up is low
 
-J1_tx_reg[8] = DFFEAS(J1L79, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_dram_a[7] = DFFEAS(F1L28, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]
+--F1_dram_a[8] is sdram:sdram|dram_a[8]
 --register power-up is low
 
-Q2_shift_reg[1] = DFFEAS(Q2L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_dram_a[8] = DFFEAS(F1L27, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---J1_dffe11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11
+--F1_dram_a[10] is sdram:sdram|dram_a[10]
 --register power-up is low
 
-J1_dffe11 = DFFEAS(J1L30, J1_fast_clock,  ,  ,  ,  ,  ,  ,  );
+F1_dram_a[10] = DFFEAS(F1L26, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q2L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~0
-Q2L7 = (J1_dffe11 & (J1_tx_reg[8])) # (!J1_dffe11 & ((Q2_shift_reg[1])));
+--F1_dram_cmd[3] is sdram:sdram|dram_cmd[3]
+--register power-up is low
 
+F1_dram_cmd[3] = DFFEAS(F1L15, T1_wire_pll1_clk[0], rst_n,  , F1L83,  ,  ,  ,  );
 
---J1_tx_reg[9] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]
+
+--F1_dram_cmd[0] is sdram:sdram|dram_cmd[0]
 --register power-up is low
 
-J1_tx_reg[9] = DFFEAS(B1_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_dram_cmd[0] = DFFEAS(F1L25, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]
+--F1_dram_cmd[1] is sdram:sdram|dram_cmd[1]
 --register power-up is low
 
-Q1_shift_reg[1] = DFFEAS(Q1L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_dram_cmd[1] = DFFEAS(F1L20, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q1L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~0
-Q1L7 = (J1_dffe11 & (J1_tx_reg[9])) # (!J1_dffe11 & ((Q1_shift_reg[1])));
+--F1_dram_cmd[2] is sdram:sdram|dram_cmd[2]
+--register power-up is low
 
+F1_dram_cmd[2] = DFFEAS(F1L17, T1_wire_pll1_clk[0], rst_n,  , F1L83,  ,  ,  ,  );
 
---J1_tx_reg[18] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]
+
+--rst_n is rst_n
 --register power-up is low
 
-J1_tx_reg[18] = DFFEAS(J1L93, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+rst_n = DFFEAS(A1L305, T1_wire_pll1_clk[1], !A1L25,  ,  ,  ,  ,  ,  );
 
 
---Q4_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]
---register power-up is low
+--abc_a[10] is abc_a[10]
+abc_a[10] = INPUT();
 
-Q4_shift_reg[1] = DFFEAS(Q4L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--F1_state.st_idle is sdram:sdram|state.st_idle
+--register power-up is low
 
---Q4L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~0
-Q4L7 = (J1_dffe11 & (J1_tx_reg[18])) # (!J1_dffe11 & ((Q4_shift_reg[1])));
+F1_state.st_idle = DFFEAS(F1L213, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---J1_tx_reg[19] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]
+--abc_rrq is abc_rrq
 --register power-up is low
 
-J1_tx_reg[19] = DFFEAS(J1L95, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+abc_rrq = DFFEAS(A1L96, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q3_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]
+--abc_wrq is abc_wrq
 --register power-up is low
 
-Q3_shift_reg[1] = DFFEAS(Q3L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+abc_wrq = DFFEAS(A1L99, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q3L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~0
-Q3L7 = (J1_dffe11 & (J1_tx_reg[19])) # (!J1_dffe11 & ((Q3_shift_reg[1])));
+--F1L40 is sdram:sdram|Selector42~2
+F1L40 = (F1_state.st_idle & ((abc_rrq) # (abc_wrq)));
 
 
---J1_tx_reg[28] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]
+--F1_state.st_p0_rd is sdram:sdram|state.st_p0_rd
 --register power-up is low
 
-J1_tx_reg[28] = DFFEAS(B2_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_state.st_p0_rd = DFFEAS(F1L215, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q6_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]
+--F1_state.st_p0_wr is sdram:sdram|state.st_p0_wr
 --register power-up is low
 
-Q6_shift_reg[1] = DFFEAS(Q6L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
-
+F1_state.st_p0_wr = DFFEAS(F1L217, T1_wire_pll1_clk[0], rst_n,  , F1L218,  ,  ,  ,  );
 
---Q6L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~0
-Q6L7 = (J1_dffe11 & (J1_tx_reg[28])) # (!J1_dffe11 & ((Q6_shift_reg[1])));
 
+--F1L207 is sdram:sdram|state.st_reset~0
+F1L207 = (F1_state.st_p0_rd) # (F1_state.st_p0_wr);
 
---J1_tx_reg[29] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]
---register power-up is low
 
-J1_tx_reg[29] = DFFEAS(B3_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--abc_a[11] is abc_a[11]
+abc_a[11] = INPUT();
 
 
---Q5_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]
+--F1_state.st_init is sdram:sdram|state.st_init
 --register power-up is low
 
-Q5_shift_reg[1] = DFFEAS(Q5L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
-
+F1_state.st_init = DFFEAS(F1L220, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
---Q5L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~0
-Q5L7 = (J1_dffe11 & (J1_tx_reg[29])) # (!J1_dffe11 & ((Q5_shift_reg[1])));
 
+--F1L1 is sdram:sdram|Equal0~0
+F1L1 = (F1_op_cycle[0] & (F1_op_cycle[1] & !F1_op_cycle[3]));
 
---J1_dffe22 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22
---register power-up is low
 
-J1_dffe22 = DFFEAS(J1L45, J1_fast_clock,  ,  ,  ,  ,  ,  ,  );
+--F1L34 is sdram:sdram|Selector32~0
+F1L34 = (F1_state.st_init & (F1L1 & (F1_op_cycle[2] & F1_op_cycle[4])));
 
 
---N2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]
---register power-up is low
+--abc_a[12] is abc_a[12]
+abc_a[12] = INPUT();
 
-N2_shift_reg[1] = DFFEAS(N2L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--F1L8 is sdram:sdram|Selector12~0
+F1L8 = (abc_a[12] & ((abc_rrq) # (abc_wrq)));
 
---N2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~0
-N2L8 = (J1_dffe22) # (N2_shift_reg[1]);
 
+--abc_a[1] is abc_a[1]
+abc_a[1] = INPUT();
 
---N1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]
---register power-up is low
 
-N1_shift_reg[1] = DFFEAS(N1L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--abc_a[13] is abc_a[13]
+abc_a[13] = INPUT();
 
 
---N1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~0
-N1L9 = (J1_dffe22) # (N1_shift_reg[1]);
+--F1L7 is sdram:sdram|Selector11~0
+F1L7 = (abc_a[13] & ((abc_rrq) # (abc_wrq)));
 
 
---abc_do[0] is abc_do[0]
---register power-up is low
+--abc_a[2] is abc_a[2]
+abc_a[2] = INPUT();
 
-abc_do[0] = DFFEAS(F1L188, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
+--abc_a[14] is abc_a[14]
+abc_a[14] = INPUT();
 
---abc_do[1] is abc_do[1]
---register power-up is low
 
-abc_do[1] = DFFEAS(F1L189, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
+--abc_a[3] is abc_a[3]
+abc_a[3] = INPUT();
 
 
---abc_do[2] is abc_do[2]
---register power-up is low
+--F1L33 is sdram:sdram|Selector30~0
+F1L33 = (F1L207 & (((abc_a[3])))) # (!F1L207 & (F1L40 & (abc_a[14])));
 
-abc_do[2] = DFFEAS(F1L190, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
+--abc_a[15] is abc_a[15]
+abc_a[15] = INPUT();
 
---abc_do[3] is abc_do[3]
---register power-up is low
 
-abc_do[3] = DFFEAS(F1L191, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
+--abc_a[4] is abc_a[4]
+abc_a[4] = INPUT();
 
 
---abc_do[4] is abc_do[4]
---register power-up is low
+--F1L32 is sdram:sdram|Selector29~0
+F1L32 = (F1L207 & (((abc_a[4])))) # (!F1L207 & (F1L40 & (abc_a[15])));
 
-abc_do[4] = DFFEAS(F1L192, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
+--abc_a[5] is abc_a[5]
+abc_a[5] = INPUT();
 
---abc_do[5] is abc_do[5]
---register power-up is low
 
-abc_do[5] = DFFEAS(F1L193, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
+--abc_a[6] is abc_a[6]
+abc_a[6] = INPUT();
 
 
---abc_do[6] is abc_do[6]
---register power-up is low
+--abc_a[7] is abc_a[7]
+abc_a[7] = INPUT();
 
-abc_do[6] = DFFEAS(F1L194, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
+--F1L29 is sdram:sdram|Selector26~0
+F1L29 = (abc_a[7] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
 
---abc_do[7] is abc_do[7]
---register power-up is low
 
-abc_do[7] = DFFEAS(F1L195, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
+--abc_a[8] is abc_a[8]
+abc_a[8] = INPUT();
 
 
---F1_dram_d[0] is sdram:sdram|dram_d[0]
---register power-up is low
+--F1L28 is sdram:sdram|Selector25~0
+F1L28 = (abc_a[8] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
 
-F1_dram_d[0] = DFFEAS(F1L56, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--abc_a[9] is abc_a[9]
+abc_a[9] = INPUT();
 
---F1_dram_d_en is sdram:sdram|dram_d_en
---register power-up is low
 
-F1_dram_d_en = DFFEAS(F1_state.st_p0_rd, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--F1L27 is sdram:sdram|Selector24~0
+F1L27 = (abc_a[9] & ((F1_state.st_p0_rd) # (F1_state.st_p0_wr)));
 
 
---F1_dram_d[1] is sdram:sdram|dram_d[1]
+--F1_state.st_reset is sdram:sdram|state.st_reset
 --register power-up is low
 
-F1_dram_d[1] = DFFEAS(F1L55, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+F1_state.st_reset = DFFEAS(F1L222, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_d[2] is sdram:sdram|dram_d[2]
---register power-up is low
+--F1L26 is sdram:sdram|Selector22~0
+F1L26 = (F1_init_ctr[15] & !F1_state.st_reset);
 
-F1_dram_d[2] = DFFEAS(F1L54, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--abc_a[0] is abc_a[0]
+abc_a[0] = INPUT();
 
---F1_dram_d[3] is sdram:sdram|dram_d[3]
---register power-up is low
 
-F1_dram_d[3] = DFFEAS(F1L53, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--F1L225 is sdram:sdram|wack0_q~0
+F1L225 = (F1_state.st_p0_wr & (F1L1 & (!F1_op_cycle[2] & !F1_op_cycle[4])));
 
 
---F1_dram_d[4] is sdram:sdram|dram_d[4]
---register power-up is low
+--F1L43 is sdram:sdram|Selector46~0
+F1L43 = (abc_a[0]) # (!F1L225);
 
-F1_dram_d[4] = DFFEAS(F1L52, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--F1L42 is sdram:sdram|Selector45~0
+F1L42 = (!F1L225) # (!abc_a[0]);
 
---F1_dram_d[5] is sdram:sdram|dram_d[5]
---register power-up is low
 
-F1_dram_d[5] = DFFEAS(F1L51, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--F1L12 is sdram:sdram|Selector16~2
+F1L12 = (!abc_rrq & (!abc_wrq & (!F1_rfsh_ctr[8] & !F1_rfsh_ctr[9])));
 
 
---F1_dram_d[6] is sdram:sdram|dram_d[6]
---register power-up is low
+--F1L13 is sdram:sdram|Selector16~3
+F1L13 = (!F1_state.st_reset & !F1_init_ctr[15]);
 
-F1_dram_d[6] = DFFEAS(F1L50, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--F1L81 is sdram:sdram|dram_cmd[3]~0
+F1L81 = (F1_state.st_init & (((!F1_op_cycle[4]) # (!F1_op_cycle[2])) # (!F1L1)));
 
---F1_dram_d[7] is sdram:sdram|dram_d[7]
---register power-up is low
 
-F1_dram_d[7] = DFFEAS(F1L49, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--F1L3 is sdram:sdram|Equal1~0
+F1L3 = (F1_op_cycle[0] & (F1_op_cycle[2] & (!F1_op_cycle[1] & !F1_op_cycle[4])));
 
 
---F1_dram_d[8] is sdram:sdram|dram_d[8]
---register power-up is low
+--F1L2 is sdram:sdram|Equal0~1
+F1L2 = (F1L1 & (!F1_op_cycle[2] & !F1_op_cycle[4]));
 
-F1_dram_d[8] = DFFEAS(F1L56, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--F1L82 is sdram:sdram|dram_cmd[3]~1
+F1L82 = (F1L81 & (!F1L2 & ((!F1L3) # (!F1_op_cycle[3]))));
 
---F1_dram_d[9] is sdram:sdram|dram_d[9]
---register power-up is low
 
-F1_dram_d[9] = DFFEAS(F1L55, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--F1L9 is sdram:sdram|Selector15~0
+F1L9 = (F1_state.st_rfsh) # ((F1L207 & ((F1_op_cycle[4]) # (!F1L1))));
 
 
---F1_dram_d[10] is sdram:sdram|dram_d[10]
---register power-up is low
+--F1L83 is sdram:sdram|dram_cmd[3]~2
+F1L83 = (!F1L82 & !F1L9);
 
-F1_dram_d[10] = DFFEAS(F1L54, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--F1L4 is sdram:sdram|Equal3~0
+F1L4 = (F1L1 & (F1_op_cycle[2] & !F1_op_cycle[4]));
 
---F1_dram_d[11] is sdram:sdram|dram_d[11]
---register power-up is low
 
-F1_dram_d[11] = DFFEAS(F1L53, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--F1L21 is sdram:sdram|Selector19~0
+F1L21 = (F1_state.st_p0_rd & (!F1L4 & ((F1L2) # (!F1_dram_cmd[0]))));
 
 
---F1_dram_d[12] is sdram:sdram|dram_d[12]
---register power-up is low
+--F1L22 is sdram:sdram|Selector19~1
+F1L22 = (F1L81 & ((F1L2) # ((F1_op_cycle[3] & F1L3))));
 
-F1_dram_d[12] = DFFEAS(F1L52, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--F1L23 is sdram:sdram|Selector19~2
+F1L23 = (F1_state.st_idle) # ((F1L13) # ((F1L21) # (F1L22)));
 
---F1_dram_d[13] is sdram:sdram|dram_d[13]
---register power-up is low
 
-F1_dram_d[13] = DFFEAS(F1L51, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--F1L24 is sdram:sdram|Selector19~3
+F1L24 = (F1L81) # ((F1_state.st_p0_wr & ((F1_op_cycle[4]) # (!F1L1))));
 
 
---F1_dram_d[14] is sdram:sdram|dram_d[14]
---register power-up is low
+--F1L25 is sdram:sdram|Selector19~4
+F1L25 = (!F1L23 & ((F1_dram_cmd[0]) # ((!F1_state.st_rfsh & !F1L24))));
 
-F1_dram_d[14] = DFFEAS(F1L50, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
+--F1L18 is sdram:sdram|Selector18~0
+F1L18 = (F1L207 & ((F1L4) # ((!F1_dram_cmd[1] & !F1L2))));
 
---F1_dram_d[15] is sdram:sdram|dram_d[15]
---register power-up is low
 
-F1_dram_d[15] = DFFEAS(F1L49, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--F1L52 is sdram:sdram|WideOr0~0
+F1L52 = (abc_rrq) # ((abc_wrq) # ((!F1_rfsh_ctr[8] & !F1_rfsh_ctr[9])));
 
 
---A1L104 is abc_xmem_done~0
-A1L104 = (abc_xmemrd_q & ((abc_xmem_done) # (F1_rack0_q)));
+--F1L19 is sdram:sdram|Selector18~1
+F1L19 = (F1L18) # (((F1_state.st_idle & F1L52)) # (!F1_state.st_reset));
 
 
---A1L105 is abc_xmem_done~1
-A1L105 = (A1L104) # ((abc_xmemwr_q & ((abc_xmem_done) # (F1_wack0_q))));
+--F1L20 is sdram:sdram|Selector18~2
+F1L20 = (!F1L19 & ((F1_dram_cmd[1]) # ((!F1L82 & !F1_state.st_rfsh))));
 
 
---F1L187 is sdram:sdram|rack0_q~0
-F1L187 = (F1_state.st_p0_rd & (F1_op_cycle[2] & F1L1));
+--F1L14 is sdram:sdram|Selector16~4
+F1L14 = (F1_state.st_idle & F1L12);
 
 
---A1L113 is abc_xmemwr~0
-A1L113 = (abc_xinpstb_n & (!abc_xmemw800_n)) # (!abc_xinpstb_n & ((abc_xoutpstb_n & (!abc_xmemw800_n)) # (!abc_xoutpstb_n & ((!abc_xmemw80_n)))));
+--F1L16 is sdram:sdram|Selector17~2
+F1L16 = (F1_state.st_reset & (F1L207 & (!F1_state.st_init & !F1L4)));
 
 
---F1L7 is sdram:sdram|Equal6~1
-F1L7 = (F1_op_cycle[0] & (F1_op_cycle[3] & (F1L6 & !F1_op_cycle[4])));
+--led_ctr[0] is led_ctr[0]
+--register power-up is low
 
+led_ctr[0] = DFFEAS(A1L205, T1_wire_pll1_clk[1], rst_n,  ,  ,  ,  ,  ,  );
 
---F1L62 is sdram:sdram|always1~5
-F1L62 = (F1L61 & !F1_op_cycle[4]);
 
+--Q2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[0]
+--register power-up is low
 
---F1L43 is sdram:sdram|Selector38~0
-F1L43 = (F1_state.st_init & ((F1L62) # ((F1_state.st_idle & !F1L57)))) # (!F1_state.st_init & (((F1_state.st_idle & !F1L57))));
+Q2_shift_reg[0] = DFFEAS(Q2L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B3_qreg[7] is tmdsenc:hdmitmds[2].enc|qreg[7]
+--Q1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[0]
 --register power-up is low
 
-B3_qreg[7] = DFFEAS(B3L58, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+Q1_shift_reg[0] = DFFEAS(Q1L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---J1_tx_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]
+--Q4_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[0]
 --register power-up is low
 
-J1_tx_reg[6] = DFFEAS(J1L75, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+Q4_shift_reg[0] = DFFEAS(Q4L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---Q2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]
+--Q3_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[0]
 --register power-up is low
 
-Q2_shift_reg[2] = DFFEAS(Q2L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
-
-
---Q2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~1
-Q2L8 = (J1_dffe11 & (J1_tx_reg[6])) # (!J1_dffe11 & ((Q2_shift_reg[2])));
+Q3_shift_reg[0] = DFFEAS(Q3L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---J1_dffe7a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]
+--Q6_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[0]
 --register power-up is low
 
-J1_dffe7a[2] = DFFEAS(J1_dffe5a[2], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+Q6_shift_reg[0] = DFFEAS(Q6L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---J1_dffe3a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]
+--Q5_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[0]
 --register power-up is low
 
-J1_dffe3a[0] = DFFEAS(L2_counter_reg_bit[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+Q5_shift_reg[0] = DFFEAS(Q5L7, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---J1_dffe7a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]
+--N2_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[0]
 --register power-up is low
 
-J1_dffe7a[0] = DFFEAS(J1_dffe5a[0], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+N2_shift_reg[0] = DFFEAS(N2L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---J1_dffe3a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]
+--N1_shift_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[0]
 --register power-up is low
 
-J1_dffe3a[2] = DFFEAS(L2_counter_reg_bit[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+N1_shift_reg[0] = DFFEAS(N1L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---J1L26 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~0
-J1L26 = (J1_dffe7a[2] & (J1_dffe3a[2] & (J1_dffe3a[0] $ (!J1_dffe7a[0])))) # (!J1_dffe7a[2] & (!J1_dffe3a[2] & (J1_dffe3a[0] $ (!J1_dffe7a[0]))));
+--clock_48 is clock_48
+clock_48 = INPUT();
 
 
---J1_dffe8a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]
+--rst_ctr[11] is rst_ctr[11]
 --register power-up is low
 
-J1_dffe8a[2] = DFFEAS(J1_dffe6a[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+rst_ctr[11] = DFFEAS(A1L21, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
 
---J1_dffe8a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]
+--rst_ctr[10] is rst_ctr[10]
 --register power-up is low
 
-J1_dffe8a[0] = DFFEAS(J1_dffe6a[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+rst_ctr[10] = DFFEAS(A1L19, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
 
---J1_dffe4a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]
+--rst_ctr[9] is rst_ctr[9]
 --register power-up is low
 
-J1_dffe4a[0] = DFFEAS(L2_counter_reg_bit[0], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+rst_ctr[9] = DFFEAS(A1L17, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
 
---J1_dffe4a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]
+--rst_ctr[8] is rst_ctr[8]
 --register power-up is low
 
-J1_dffe4a[2] = DFFEAS(L2_counter_reg_bit[2], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+rst_ctr[8] = DFFEAS(A1L15, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
 
---J1L27 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~1
-J1L27 = (J1_dffe8a[2] & (J1_dffe4a[2] & (J1_dffe8a[0] $ (!J1_dffe4a[0])))) # (!J1_dffe8a[2] & (!J1_dffe4a[2] & (J1_dffe8a[0] $ (!J1_dffe4a[0]))));
+--rst_ctr[7] is rst_ctr[7]
+--register power-up is low
 
+rst_ctr[7] = DFFEAS(A1L13, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
---J1_dffe8a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]
+
+--rst_ctr[6] is rst_ctr[6]
 --register power-up is low
 
-J1_dffe8a[1] = DFFEAS(J1_dffe6a[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+rst_ctr[6] = DFFEAS(A1L11, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
 
---J1_dffe4a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]
+--rst_ctr[5] is rst_ctr[5]
 --register power-up is low
 
-J1_dffe4a[1] = DFFEAS(L2_counter_reg_bit[1], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+rst_ctr[5] = DFFEAS(A1L9, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
 
---J1_sync_dffe12a is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a
+--rst_ctr[4] is rst_ctr[4]
 --register power-up is low
 
-J1_sync_dffe12a = DFFEAS(J1L62, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+rst_ctr[4] = DFFEAS(A1L7, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
 
---J1L28 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~2
-J1L28 = (!J1_sync_dffe12a & (J1_dffe8a[1] $ (!J1_dffe4a[1])));
+--rst_ctr[3] is rst_ctr[3]
+--register power-up is low
 
+rst_ctr[3] = DFFEAS(A1L5, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
---J1_dffe7a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]
+
+--rst_ctr[2] is rst_ctr[2]
 --register power-up is low
 
-J1_dffe7a[1] = DFFEAS(J1_dffe5a[1], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+rst_ctr[2] = DFFEAS(A1L3, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
 
---J1_dffe3a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]
+--rst_ctr[0] is rst_ctr[0]
 --register power-up is low
 
-J1_dffe3a[1] = DFFEAS(L2_counter_reg_bit[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+rst_ctr[0] = DFFEAS(A1L292, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
 
---J1L29 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~3
-J1L29 = (J1_sync_dffe12a & (J1_dffe7a[1] $ (!J1_dffe3a[1])));
+--rst_ctr[1] is rst_ctr[1]
+--register power-up is low
 
+rst_ctr[1] = DFFEAS(A1L1, T1_wire_pll1_clk[1], !A1L25,  , !rst_n,  ,  ,  ,  );
 
---J1L30 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~4
-J1L30 = (J1L26 & ((J1L29) # ((J1L27 & J1L28)))) # (!J1L26 & (J1L27 & (J1L28)));
+
+--A1L305 is rst_n~0
+A1L305 = (rst_n) # (A1L23);
 
 
---J1_tx_reg[7] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]
+--J1_pll_lock_sync is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|pll_lock_sync
 --register power-up is low
 
-J1_tx_reg[7] = DFFEAS(J1L77, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+J1_pll_lock_sync = DFFEAS(VCC, J1_wire_lvds_tx_pll_locked, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---Q1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]
---register power-up is low
+--A1L25 is WideAnd0~0
+A1L25 = ((!J1_pll_lock_sync) # (!J1_wire_lvds_tx_pll_locked)) # (!T1_wire_pll1_locked);
 
-Q1_shift_reg[2] = DFFEAS(Q1L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--F1L208 is sdram:sdram|state.st_reset~1
+F1L208 = (F1_state.st_reset & (!F1_state.st_rfsh & (!F1_state.st_idle & !F1_state.st_init)));
 
---Q1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~1
-Q1L8 = (J1_dffe11 & (J1_tx_reg[7])) # (!J1_dffe11 & ((Q1_shift_reg[2])));
 
+--F1L209 is sdram:sdram|state.st_reset~2
+F1L209 = (F1_state.st_reset & ((F1_state.st_rfsh & ((F1_state.st_idle) # (F1_state.st_init))) # (!F1_state.st_rfsh & (F1_state.st_idle & F1_state.st_init)))) # (!F1_state.st_reset & ((F1_state.st_rfsh) # ((F1_state.st_idle) # (F1_state.st_init))));
 
---B1_qreg[3] is tmdsenc:hdmitmds[0].enc|qreg[3]
---register power-up is low
 
-B1_qreg[3] = DFFEAS(B1L63, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+--F1L210 is sdram:sdram|state.st_reset~3
+F1L210 = (F1_state.st_p0_rd & (!F1_state.st_p0_wr & (F1L208 & !F1L209))) # (!F1_state.st_p0_rd & ((F1_state.st_p0_wr & (F1L208 & !F1L209)) # (!F1_state.st_p0_wr & (F1L208 $ (!F1L209)))));
 
 
---J1_tx_reg[16] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]
---register power-up is low
+--F1L35 is sdram:sdram|Selector40~0
+F1L35 = (F1_state.st_idle) # (!F1_state.st_reset);
 
-J1_tx_reg[16] = DFFEAS(B2_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--F1L36 is sdram:sdram|Selector40~1
+F1L36 = (F1_state.st_init & (F1_op_cycle[3] & F1_op_cycle[4]));
 
---Q4_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]
---register power-up is low
 
-Q4_shift_reg[2] = DFFEAS(Q4L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--F1L37 is sdram:sdram|Selector40~2
+F1L37 = (!F1_state.st_init & ((F1_state.st_p0_rd) # ((F1_state.st_p0_wr) # (F1_state.st_rfsh))));
 
 
---Q4L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~1
-Q4L8 = (J1_dffe11 & (J1_tx_reg[16])) # (!J1_dffe11 & ((Q4_shift_reg[2])));
+--F1L5 is sdram:sdram|LessThan1~0
+F1L5 = ((!F1_op_cycle[0] & (!F1_op_cycle[1] & !F1_op_cycle[2]))) # (!F1_op_cycle[3]);
 
 
---B2_qreg[3] is tmdsenc:hdmitmds[1].enc|qreg[3]
---register power-up is low
+--F1L6 is sdram:sdram|LessThan1~1
+F1L6 = (F1L5 & !F1_op_cycle[4]);
 
-B2_qreg[3] = DFFEAS(B2L59, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
+--F1L38 is sdram:sdram|Selector40~3
+F1L38 = (!F1L35 & ((F1L36) # ((F1L37 & !F1L6))));
 
---J1_tx_reg[17] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]
---register power-up is low
 
-J1_tx_reg[17] = DFFEAS(B3_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--F1L212 is sdram:sdram|state~23
+F1L212 = (!F1_state.st_idle & ((F1_state.st_reset) # (!F1_init_ctr[15])));
 
 
---Q3_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]
---register power-up is low
+--F1L213 is sdram:sdram|state~24
+F1L213 = (F1L210 & ((F1L14) # ((F1L38 & F1L212))));
 
-Q3_shift_reg[2] = DFFEAS(Q3L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--abc_xmemrd_q is abc_xmemrd_q
+--register power-up is low
 
---Q3L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~1
-Q3L8 = (J1_dffe11 & (J1_tx_reg[17])) # (!J1_dffe11 & ((Q3_shift_reg[2])));
+abc_xmemrd_q = DFFEAS(A1L109, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---J1_tx_reg[26] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]
+--abc_xmem_done is abc_xmem_done
 --register power-up is low
 
-J1_tx_reg[26] = DFFEAS(B3_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+abc_xmem_done = DFFEAS(A1L105, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q6_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]
+--F1_rack0_q[0] is sdram:sdram|rack0_q[0]
 --register power-up is low
 
-Q6_shift_reg[2] = DFFEAS(Q6L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_rack0_q[0] = DFFEAS(F1L162, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q6L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~1
-Q6L8 = (J1_dffe11 & (J1_tx_reg[26])) # (!J1_dffe11 & ((Q6_shift_reg[2])));
+--A1L96 is abc_rrq~0
+A1L96 = (abc_xmemrd_q & (!abc_xmem_done & !F1_rack0_q[0]));
 
 
---J1_tx_reg[27] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]
+--abc_xmemwr_q is abc_xmemwr_q
 --register power-up is low
 
-J1_tx_reg[27] = DFFEAS(B1_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+abc_xmemwr_q = DFFEAS(A1L113, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q5_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]
+--F1_wack0_q[0] is sdram:sdram|wack0_q[0]
 --register power-up is low
 
-Q5_shift_reg[2] = DFFEAS(Q5L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_wack0_q[0] = DFFEAS(F1L225, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q5L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~1
-Q5L8 = (J1_dffe11 & (J1_tx_reg[27])) # (!J1_dffe11 & ((Q5_shift_reg[2])));
+--A1L99 is abc_wrq~0
+A1L99 = (abc_xmemwr_q & (!abc_xmem_done & !F1_wack0_q[0]));
 
 
---J1_dffe18a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]
---register power-up is low
+--F1L214 is sdram:sdram|state~25
+F1L214 = (abc_rrq & (F1_state.st_idle & !abc_wrq));
 
-J1_dffe18a[2] = DFFEAS(J1_dffe16a[2], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
+--F1L215 is sdram:sdram|state~26
+F1L215 = (F1L210 & ((F1L214) # ((F1_state.st_p0_rd & F1L6))));
 
---J1_dffe14a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]
---register power-up is low
 
-J1_dffe14a[0] = DFFEAS(L1_counter_reg_bit[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+--F1L216 is sdram:sdram|state~27
+F1L216 = (abc_wrq & (F1_state.st_idle & (F1_state.st_reset & !F1_state.st_rfsh)));
 
 
---J1_dffe18a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]
---register power-up is low
+--F1L217 is sdram:sdram|state~28
+F1L217 = (!F1L207 & (F1L216 & (F1_state.st_idle $ (F1_state.st_init))));
 
-J1_dffe18a[0] = DFFEAS(J1_dffe16a[0], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
+--F1L218 is sdram:sdram|state~29
+F1L218 = (F1L38) # ((!F1L212) # (!F1L210));
 
---J1_dffe14a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]
---register power-up is low
 
-J1_dffe14a[2] = DFFEAS(L1_counter_reg_bit[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+--F1L219 is sdram:sdram|state~30
+F1L219 = (F1_state.st_init & (((F1L35) # (!F1_op_cycle[4])) # (!F1_op_cycle[3])));
 
 
---J1L44 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~0
-J1L44 = (J1_dffe18a[2] & (J1_dffe14a[2] & (J1_dffe14a[0] $ (!J1_dffe18a[0])))) # (!J1_dffe18a[2] & (!J1_dffe14a[2] & (J1_dffe14a[0] $ (!J1_dffe18a[0]))));
+--F1L220 is sdram:sdram|state~31
+F1L220 = (F1L210 & (!F1_state.st_idle & ((F1L26) # (F1L219))));
 
 
---J1_dffe18a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]
+--F1_init_ctr[10] is sdram:sdram|init_ctr[10]
 --register power-up is low
 
-J1_dffe18a[1] = DFFEAS(J1_dffe16a[1], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+F1_init_ctr[10] = DFFEAS(F1L128, T1_wire_pll1_clk[0], rst_n,  , F1L53,  ,  ,  ,  );
 
 
---J1_dffe14a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]
+--F1_init_ctr[9] is sdram:sdram|init_ctr[9]
 --register power-up is low
 
-J1_dffe14a[1] = DFFEAS(L1_counter_reg_bit[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+F1_init_ctr[9] = DFFEAS(F1_rfsh_ctr[9], T1_wire_pll1_clk[0], rst_n,  , F1L53,  ,  ,  ,  );
 
 
---J1L45 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~1
-J1L45 = (J1_sync_dffe12a & (J1L44 & (J1_dffe18a[1] $ (!J1_dffe14a[1]))));
+--F1L53 is sdram:sdram|always0~0
+F1L53 = F1_rfsh_ctr[9] $ (F1_init_ctr[9]);
 
 
---N2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]
+--F1_dram_cmd[4] is sdram:sdram|dram_cmd[4]
 --register power-up is low
 
-N2_shift_reg[2] = DFFEAS(N2L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_dram_cmd[4] = DFFEAS(F1L11, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---N2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~1
-N2L9 = (J1_dffe22) # (N2_shift_reg[2]);
+--F1L221 is sdram:sdram|state~32
+F1L221 = (F1L210 & !F1L52);
 
 
---N1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]
+--J1_tx_reg[8] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]
 --register power-up is low
 
-N1_shift_reg[2] = DFFEAS(N1L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
-
-
---N1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~1
-N1L10 = (J1_dffe22) # (N1_shift_reg[2]);
+J1_tx_reg[8] = DFFEAS(J1L79, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_q[8] is sdram:sdram|dram_q[8]
+--Q2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[1]
 --register power-up is low
 
-F1_dram_q[8] = DFFEAS(sr_dq[8], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+Q2_shift_reg[1] = DFFEAS(Q2L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_q[0] is sdram:sdram|dram_q[0]
+--J1_dffe11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11
 --register power-up is low
 
-F1_dram_q[0] = DFFEAS(sr_dq[0], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
-
-
---F1L188 is sdram:sdram|rd0[0]~0
-F1L188 = (abc_a[0] & (F1_dram_q[8])) # (!abc_a[0] & ((F1_dram_q[0])));
+J1_dffe11 = DFFEAS(J1L30, J1_fast_clock,  ,  ,  ,  ,  ,  ,  );
 
 
---A1L67 is abc_do[0]~0
-A1L67 = (rst_n & F1_rack0_q);
+--Q2L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~0
+Q2L7 = (J1_dffe11 & (J1_tx_reg[8])) # (!J1_dffe11 & ((Q2_shift_reg[1])));
 
 
---F1_dram_q[9] is sdram:sdram|dram_q[9]
+--J1_tx_reg[9] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[9]
 --register power-up is low
 
-F1_dram_q[9] = DFFEAS(sr_dq[9], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+J1_tx_reg[9] = DFFEAS(B1_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_q[1] is sdram:sdram|dram_q[1]
+--Q1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[1]
 --register power-up is low
 
-F1_dram_q[1] = DFFEAS(sr_dq[1], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+Q1_shift_reg[1] = DFFEAS(Q1L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1L189 is sdram:sdram|rd0[1]~1
-F1L189 = (abc_a[0] & (F1_dram_q[9])) # (!abc_a[0] & ((F1_dram_q[1])));
+--Q1L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~0
+Q1L7 = (J1_dffe11 & (J1_tx_reg[9])) # (!J1_dffe11 & ((Q1_shift_reg[1])));
 
 
---F1_dram_q[10] is sdram:sdram|dram_q[10]
+--J1_tx_reg[18] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]
 --register power-up is low
 
-F1_dram_q[10] = DFFEAS(sr_dq[10], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+J1_tx_reg[18] = DFFEAS(J1L93, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_q[2] is sdram:sdram|dram_q[2]
+--Q4_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[1]
 --register power-up is low
 
-F1_dram_q[2] = DFFEAS(sr_dq[2], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+Q4_shift_reg[1] = DFFEAS(Q4L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1L190 is sdram:sdram|rd0[2]~2
-F1L190 = (abc_a[0] & (F1_dram_q[10])) # (!abc_a[0] & ((F1_dram_q[2])));
+--Q4L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~0
+Q4L7 = (J1_dffe11 & (J1_tx_reg[18])) # (!J1_dffe11 & ((Q4_shift_reg[1])));
 
 
---F1_dram_q[11] is sdram:sdram|dram_q[11]
+--J1_tx_reg[19] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]
 --register power-up is low
 
-F1_dram_q[11] = DFFEAS(sr_dq[11], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+J1_tx_reg[19] = DFFEAS(J1L95, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_q[3] is sdram:sdram|dram_q[3]
+--Q3_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[1]
 --register power-up is low
 
-F1_dram_q[3] = DFFEAS(sr_dq[3], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+Q3_shift_reg[1] = DFFEAS(Q3L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1L191 is sdram:sdram|rd0[3]~3
-F1L191 = (abc_a[0] & (F1_dram_q[11])) # (!abc_a[0] & ((F1_dram_q[3])));
+--Q3L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~0
+Q3L7 = (J1_dffe11 & (J1_tx_reg[19])) # (!J1_dffe11 & ((Q3_shift_reg[1])));
 
 
---F1_dram_q[12] is sdram:sdram|dram_q[12]
+--J1_tx_reg[28] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[28]
 --register power-up is low
 
-F1_dram_q[12] = DFFEAS(sr_dq[12], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+J1_tx_reg[28] = DFFEAS(B2_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_q[4] is sdram:sdram|dram_q[4]
+--Q6_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[1]
 --register power-up is low
 
-F1_dram_q[4] = DFFEAS(sr_dq[4], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+Q6_shift_reg[1] = DFFEAS(Q6L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1L192 is sdram:sdram|rd0[4]~4
-F1L192 = (abc_a[0] & (F1_dram_q[12])) # (!abc_a[0] & ((F1_dram_q[4])));
+--Q6L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~0
+Q6L7 = (J1_dffe11 & (J1_tx_reg[28])) # (!J1_dffe11 & ((Q6_shift_reg[1])));
 
 
---F1_dram_q[13] is sdram:sdram|dram_q[13]
+--J1_tx_reg[29] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[29]
 --register power-up is low
 
-F1_dram_q[13] = DFFEAS(sr_dq[13], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+J1_tx_reg[29] = DFFEAS(B3_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_q[5] is sdram:sdram|dram_q[5]
+--Q5_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[1]
 --register power-up is low
 
-F1_dram_q[5] = DFFEAS(sr_dq[5], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+Q5_shift_reg[1] = DFFEAS(Q5L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1L193 is sdram:sdram|rd0[5]~5
-F1L193 = (abc_a[0] & (F1_dram_q[13])) # (!abc_a[0] & ((F1_dram_q[5])));
+--Q5L7 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~0
+Q5L7 = (J1_dffe11 & (J1_tx_reg[29])) # (!J1_dffe11 & ((Q5_shift_reg[1])));
 
 
---F1_dram_q[14] is sdram:sdram|dram_q[14]
+--J1_dffe22 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22
 --register power-up is low
 
-F1_dram_q[14] = DFFEAS(sr_dq[14], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+J1_dffe22 = DFFEAS(J1L45, J1_fast_clock,  ,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_q[6] is sdram:sdram|dram_q[6]
+--N2_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[1]
 --register power-up is low
 
-F1_dram_q[6] = DFFEAS(sr_dq[6], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+N2_shift_reg[1] = DFFEAS(N2L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1L194 is sdram:sdram|rd0[6]~6
-F1L194 = (abc_a[0] & (F1_dram_q[14])) # (!abc_a[0] & ((F1_dram_q[6])));
+--N2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~0
+N2L8 = (J1_dffe22) # (N2_shift_reg[1]);
 
 
---F1_dram_q[15] is sdram:sdram|dram_q[15]
+--N1_shift_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[1]
 --register power-up is low
 
-F1_dram_q[15] = DFFEAS(sr_dq[15], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+N1_shift_reg[1] = DFFEAS(N1L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_q[7] is sdram:sdram|dram_q[7]
+--N1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~0
+N1L9 = (J1_dffe22) # (N1_shift_reg[1]);
+
+
+--abc_do[0] is abc_do[0]
 --register power-up is low
 
-F1_dram_q[7] = DFFEAS(sr_dq[7], T1_wire_pll1_clk[0],  ,  , F1L126,  ,  ,  ,  );
+abc_do[0] = DFFEAS(F1L163, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
 
---F1L195 is sdram:sdram|rd0[7]~7
-F1L195 = (abc_a[0] & (F1_dram_q[15])) # (!abc_a[0] & ((F1_dram_q[7])));
+--abc_do[1] is abc_do[1]
+--register power-up is low
 
+abc_do[1] = DFFEAS(F1L164, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
---F1L56 is sdram:sdram|Selector74~0
-F1L56 = (abc_d[0] & F1_state.st_p0_wr);
 
+--abc_do[2] is abc_do[2]
+--register power-up is low
 
---F1L55 is sdram:sdram|Selector73~0
-F1L55 = (abc_d[1] & F1_state.st_p0_wr);
+abc_do[2] = DFFEAS(F1L165, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
 
---F1L54 is sdram:sdram|Selector72~0
-F1L54 = (abc_d[2] & F1_state.st_p0_wr);
+--abc_do[3] is abc_do[3]
+--register power-up is low
 
+abc_do[3] = DFFEAS(F1L166, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
---F1L53 is sdram:sdram|Selector71~0
-F1L53 = (abc_d[3] & F1_state.st_p0_wr);
 
+--abc_do[4] is abc_do[4]
+--register power-up is low
 
---F1L52 is sdram:sdram|Selector70~0
-F1L52 = (abc_d[4] & F1_state.st_p0_wr);
+abc_do[4] = DFFEAS(F1L167, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
 
---F1L51 is sdram:sdram|Selector69~0
-F1L51 = (abc_d[5] & F1_state.st_p0_wr);
+--abc_do[5] is abc_do[5]
+--register power-up is low
 
+abc_do[5] = DFFEAS(F1L168, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
---F1L50 is sdram:sdram|Selector68~0
-F1L50 = (abc_d[6] & F1_state.st_p0_wr);
 
+--abc_do[6] is abc_do[6]
+--register power-up is low
 
---F1L49 is sdram:sdram|Selector67~0
-F1L49 = (abc_d[7] & F1_state.st_p0_wr);
+abc_do[6] = DFFEAS(F1L169, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
 
---B1_denreg is tmdsenc:hdmitmds[0].enc|denreg
+--abc_do[7] is abc_do[7]
 --register power-up is low
 
-B1_denreg = DFFEAS(VCC, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+abc_do[7] = DFFEAS(F1L170, T1_wire_pll1_clk[0],  ,  , A1L67,  ,  ,  ,  );
 
 
---dummydata[0] is dummydata[0]
+--F1_dram_d[0] is sdram:sdram|dram_d[0]
 --register power-up is low
 
-dummydata[0] = DFFEAS(dummydata[23], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_d[0] = DFFEAS(F1L51, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---dummydata[23] is dummydata[23]
+--F1_dram_d_en is sdram:sdram|dram_d_en
 --register power-up is low
 
-dummydata[23] = DFFEAS(dummydata[22], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_d_en = DFFEAS(F1_state.st_p0_rd, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---dummydata[21] is dummydata[21]
+--F1_dram_d[1] is sdram:sdram|dram_d[1]
 --register power-up is low
 
-dummydata[21] = DFFEAS(dummydata[20], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_d[1] = DFFEAS(F1L50, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---dummydata[22] is dummydata[22]
+--F1_dram_d[2] is sdram:sdram|dram_d[2]
 --register power-up is low
 
-dummydata[22] = DFFEAS(A1L147, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_d[2] = DFFEAS(F1L49, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---dummydata[19] is dummydata[19]
+--F1_dram_d[3] is sdram:sdram|dram_d[3]
 --register power-up is low
 
-dummydata[19] = DFFEAS(A1L142, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_d[3] = DFFEAS(F1L48, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---dummydata[20] is dummydata[20]
+--F1_dram_d[4] is sdram:sdram|dram_d[4]
 --register power-up is low
 
-dummydata[20] = DFFEAS(A1L144, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_d[4] = DFFEAS(F1L47, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---dummydata[17] is dummydata[17]
+--F1_dram_d[5] is sdram:sdram|dram_d[5]
 --register power-up is low
 
-dummydata[17] = DFFEAS(dummydata[16], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_d[5] = DFFEAS(F1L46, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---dummydata[18] is dummydata[18]
+--F1_dram_d[6] is sdram:sdram|dram_d[6]
 --register power-up is low
 
-dummydata[18] = DFFEAS(dummydata[17], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_d[6] = DFFEAS(F1L45, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---B3L4 is tmdsenc:hdmitmds[2].enc|Add4~2
-B3L4 = dummydata[19] $ (dummydata[20] $ (dummydata[17] $ (!dummydata[18])));
+--F1_dram_d[7] is sdram:sdram|dram_d[7]
+--register power-up is low
 
+F1_dram_d[7] = DFFEAS(F1L44, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
---B3L5 is tmdsenc:hdmitmds[2].enc|Add4~3
-B3L5 = dummydata[23] $ (dummydata[21] $ (dummydata[22] $ (B3L4)));
 
+--F1_dram_d[8] is sdram:sdram|dram_d[8]
+--register power-up is low
 
---B3L27 is tmdsenc:hdmitmds[2].enc|Equal0~0
-B3L27 = (!B3_disparity[3] & (!B3_disparity[0] & (!B3_disparity[1] & !B3_disparity[2])));
+F1_dram_d[8] = DFFEAS(F1L51, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---B3L10 is tmdsenc:hdmitmds[2].enc|Add5~0
-B3L10 = (dummydata[19] & ((dummydata[20] & ((dummydata[17]) # (dummydata[18]))) # (!dummydata[20] & (dummydata[17] & dummydata[18])))) # (!dummydata[19] & ((dummydata[20] & ((!dummydata[18]) # (!dummydata[17]))) # (!dummydata[20] & ((dummydata[17]) # (dummydata[18])))));
+--F1_dram_d[9] is sdram:sdram|dram_d[9]
+--register power-up is low
 
+F1_dram_d[9] = DFFEAS(F1L50, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
---B3L1 is tmdsenc:hdmitmds[2].enc|Add2~0
-B3L1 = dummydata[0] $ (dummydata[23] $ (dummydata[21] $ (!dummydata[22])));
 
+--F1_dram_d[10] is sdram:sdram|dram_d[10]
+--register power-up is low
 
---B3L6 is tmdsenc:hdmitmds[2].enc|Add4~4
-B3L6 = dummydata[17] $ (dummydata[18]);
+F1_dram_d[10] = DFFEAS(F1L49, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---B3L12 is tmdsenc:hdmitmds[2].enc|Add6~0
-B3L12 = (B3L1 & (dummydata[19] $ (dummydata[20] $ (!B3L6))));
+--F1_dram_d[11] is sdram:sdram|dram_d[11]
+--register power-up is low
 
+F1_dram_d[11] = DFFEAS(F1L48, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
---B3L2 is tmdsenc:hdmitmds[2].enc|Add2~1
-B3L2 = (dummydata[21] & ((dummydata[0] & ((!dummydata[22]) # (!dummydata[23]))) # (!dummydata[0] & ((dummydata[23]) # (dummydata[22]))))) # (!dummydata[21] & ((dummydata[0] & (!dummydata[23] & !dummydata[22])) # (!dummydata[0] & ((!dummydata[22]) # (!dummydata[23])))));
 
+--F1_dram_d[12] is sdram:sdram|dram_d[12]
+--register power-up is low
 
---B3L11 is tmdsenc:hdmitmds[2].enc|Add5~1
-B3L11 = (dummydata[20] & (dummydata[17] & (dummydata[18] & !dummydata[19])));
+F1_dram_d[12] = DFFEAS(F1L47, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---B3L3 is tmdsenc:hdmitmds[2].enc|Add2~2
-B3L3 = (dummydata[21] & (!dummydata[0] & (!dummydata[23] & !dummydata[22])));
+--F1_dram_d[13] is sdram:sdram|dram_d[13]
+--register power-up is low
 
+F1_dram_d[13] = DFFEAS(F1L46, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
---B3L13 is tmdsenc:hdmitmds[2].enc|Add6~1
-B3L13 = B3L11 $ (B3L3);
 
+--F1_dram_d[14] is sdram:sdram|dram_d[14]
+--register power-up is low
 
---B3L14 is tmdsenc:hdmitmds[2].enc|Add6~2
-B3L14 = B3L13 $ (((B3L10 & ((B3L12) # (B3L2))) # (!B3L10 & (B3L12 & B3L2))));
+F1_dram_d[14] = DFFEAS(F1L45, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
 
---B3L15 is tmdsenc:hdmitmds[2].enc|Add6~3
-B3L15 = dummydata[19] $ (dummydata[20] $ (B3L6 $ (!B3L1)));
+--F1_dram_d[15] is sdram:sdram|dram_d[15]
+--register power-up is low
 
+F1_dram_d[15] = DFFEAS(F1L44, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
 
---B3L16 is tmdsenc:hdmitmds[2].enc|Add6~4
-B3L16 = B3L10 $ (B3L12 $ (B3L2));
 
+--A1L104 is abc_xmem_done~0
+A1L104 = (abc_xmemrd_q & ((abc_xmem_done) # (F1_rack0_q[0])));
 
---B3L28 is tmdsenc:hdmitmds[2].enc|always1~0
-B3L28 = (B3L27) # ((B3L14 & (!B3L15 & !B3L16)));
 
+--A1L105 is abc_xmem_done~1
+A1L105 = (A1L104) # ((abc_xmemwr_q & ((abc_xmem_done) # (F1_wack0_q[0]))));
 
---B3L44 is tmdsenc:hdmitmds[2].enc|dx[8]~0
-B3L44 = (B3L14 & ((B3L15) # ((B3L16) # (!dummydata[17])))) # (!B3L14 & (!dummydata[17] & ((!B3L16) # (!B3L15))));
 
+--F1L162 is sdram:sdram|rack0_q~0
+F1L162 = (F1_state.st_p0_rd & (F1L1 & (F1_op_cycle[2] & !F1_op_cycle[4])));
 
---B3L7 is tmdsenc:hdmitmds[2].enc|Add4~5
-B3L7 = B3L14 $ (B3_disparity[3]);
 
+--abc_xmemw800_n is abc_xmemw800_n
+abc_xmemw800_n = INPUT();
 
---B3L57 is tmdsenc:hdmitmds[2].enc|qreg~0
-B3L57 = B3L5 $ (((!B3L28 & (B3L44 $ (!B3L7)))));
 
+--abc_xmemw80_n is abc_xmemw80_n
+abc_xmemw80_n = INPUT();
 
---B3L58 is tmdsenc:hdmitmds[2].enc|qreg~1
-B3L58 = (dummydata[0] $ (B3L57)) # (!B1_denreg);
 
+--abc_xinpstb_n is abc_xinpstb_n
+abc_xinpstb_n = INPUT();
 
---vid_rst_n is vid_rst_n
---register power-up is low
 
-vid_rst_n = DFFEAS(rst_n, T1_wire_pll1_clk[2], !A1L25,  ,  ,  ,  ,  ,  );
+--abc_xoutpstb_n is abc_xoutpstb_n
+abc_xoutpstb_n = INPUT();
 
 
---B1_qreg[7] is tmdsenc:hdmitmds[0].enc|qreg[7]
---register power-up is low
+--A1L113 is abc_xmemwr~0
+A1L113 = (abc_xinpstb_n & (!abc_xmemw800_n)) # (!abc_xinpstb_n & ((abc_xoutpstb_n & (!abc_xmemw800_n)) # (!abc_xoutpstb_n & ((!abc_xmemw80_n)))));
 
-B1_qreg[7] = DFFEAS(B1L65, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
+--F1L10 is sdram:sdram|Selector15~1
+F1L10 = (F1L81 & (((F1L22) # (F1_dram_cmd[4])))) # (!F1L81 & (F1L9 & ((F1L22) # (F1_dram_cmd[4]))));
 
---J1_tx_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]
---register power-up is low
 
-J1_tx_reg[4] = DFFEAS(B2_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--F1L11 is sdram:sdram|Selector15~2
+F1L11 = (F1L10) # ((F1_state.st_idle & !F1L52));
 
 
---Q2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]
+--B3_qreg[7] is tmdsenc:hdmitmds[2].enc|qreg[7]
 --register power-up is low
 
-Q2_shift_reg[3] = DFFEAS(Q2L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
-
-
---Q2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~2
-Q2L9 = (J1_dffe11 & (J1_tx_reg[4])) # (!J1_dffe11 & ((Q2_shift_reg[3])));
+B3_qreg[7] = DFFEAS(B3L58, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
 
---J1_dffe5a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]
+--J1_tx_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]
 --register power-up is low
 
-J1_dffe5a[2] = DFFEAS(J1_dffe3a[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+J1_tx_reg[6] = DFFEAS(J1L75, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---L2_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]
+--Q2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[2]
 --register power-up is low
 
-L2_counter_reg_bit[0] = DFFEAS(L2L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+Q2_shift_reg[2] = DFFEAS(Q2L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---J1_dffe5a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]
+--Q2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~1
+Q2L8 = (J1_dffe11 & (J1_tx_reg[6])) # (!J1_dffe11 & ((Q2_shift_reg[2])));
+
+
+--J1_dffe7a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[2]
 --register power-up is low
 
-J1_dffe5a[0] = DFFEAS(J1_dffe3a[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+J1_dffe7a[2] = DFFEAS(J1_dffe5a[2], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---L2_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]
+--J1_dffe3a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[0]
 --register power-up is low
 
-L2_counter_reg_bit[2] = DFFEAS(L2L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+J1_dffe3a[0] = DFFEAS(L2_counter_reg_bit[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---J1_dffe6a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]
+--J1_dffe7a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[0]
 --register power-up is low
 
-J1_dffe6a[2] = DFFEAS(J1_dffe4a[2], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+J1_dffe7a[0] = DFFEAS(J1_dffe5a[0], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---J1_dffe6a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]
+--J1_dffe3a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[2]
 --register power-up is low
 
-J1_dffe6a[0] = DFFEAS(J1_dffe4a[0], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+J1_dffe3a[2] = DFFEAS(L2_counter_reg_bit[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---J1_dffe6a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]
+--J1L26 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~0
+J1L26 = (J1_dffe7a[2] & (J1_dffe3a[2] & (J1_dffe3a[0] $ (!J1_dffe7a[0])))) # (!J1_dffe7a[2] & (!J1_dffe3a[2] & (J1_dffe3a[0] $ (!J1_dffe7a[0]))));
+
+
+--J1_dffe8a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[2]
 --register power-up is low
 
-J1_dffe6a[1] = DFFEAS(J1_dffe4a[1], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
+J1_dffe8a[2] = DFFEAS(J1_dffe6a[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---L2_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]
+--J1_dffe8a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[0]
 --register power-up is low
 
-L2_counter_reg_bit[1] = DFFEAS(L2L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+J1_dffe8a[0] = DFFEAS(J1_dffe6a[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---J1_dffe5a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]
+--J1_dffe4a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[0]
 --register power-up is low
 
-J1_dffe5a[1] = DFFEAS(J1_dffe3a[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+J1_dffe4a[0] = DFFEAS(L2_counter_reg_bit[0], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---dummydata[3] is dummydata[3]
+--J1_dffe4a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[2]
 --register power-up is low
 
-dummydata[3] = DFFEAS(A1L121, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+J1_dffe4a[2] = DFFEAS(L2_counter_reg_bit[2], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---dummydata[4] is dummydata[4]
+--J1L27 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~1
+J1L27 = (J1_dffe8a[2] & (J1_dffe4a[2] & (J1_dffe8a[0] $ (!J1_dffe4a[0])))) # (!J1_dffe8a[2] & (!J1_dffe4a[2] & (J1_dffe8a[0] $ (!J1_dffe4a[0]))));
+
+
+--J1_dffe8a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe8a[1]
 --register power-up is low
 
-dummydata[4] = DFFEAS(dummydata[3], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+J1_dffe8a[1] = DFFEAS(J1_dffe6a[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---dummydata[1] is dummydata[1]
+--J1_dffe4a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe4a[1]
 --register power-up is low
 
-dummydata[1] = DFFEAS(dummydata[0], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+J1_dffe4a[1] = DFFEAS(L2_counter_reg_bit[1], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---dummydata[2] is dummydata[2]
+--J1_sync_dffe12a is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a
 --register power-up is low
 
-dummydata[2] = DFFEAS(dummydata[1], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+J1_sync_dffe12a = DFFEAS(J1L62, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B1L10 is tmdsenc:hdmitmds[0].enc|Add5~0
-B1L10 = (dummydata[3] & ((dummydata[4] & ((dummydata[1]) # (dummydata[2]))) # (!dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))))) # (!dummydata[3] & ((dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))) # (!dummydata[4] & (!dummydata[1] & !dummydata[2]))));
+--J1L28 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~2
+J1L28 = (!J1_sync_dffe12a & (J1_dffe8a[1] $ (!J1_dffe4a[1])));
 
 
---dummydata[7] is dummydata[7]
+--J1_dffe7a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe7a[1]
 --register power-up is low
 
-dummydata[7] = DFFEAS(A1L126, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+J1_dffe7a[1] = DFFEAS(J1_dffe5a[1], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---dummydata[8] is dummydata[8]
+--J1_dffe3a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe3a[1]
 --register power-up is low
 
-dummydata[8] = DFFEAS(dummydata[7], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+J1_dffe3a[1] = DFFEAS(L2_counter_reg_bit[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---dummydata[5] is dummydata[5]
---register power-up is low
+--J1L29 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~3
+J1L29 = (J1_sync_dffe12a & (J1_dffe7a[1] $ (!J1_dffe3a[1])));
 
-dummydata[5] = DFFEAS(dummydata[4], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
+--J1L30 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe11~4
+J1L30 = (J1L26 & ((J1L29) # ((J1L27 & J1L28)))) # (!J1L26 & (J1L27 & (J1L28)));
 
---dummydata[6] is dummydata[6]
+
+--J1_tx_reg[7] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]
 --register power-up is low
 
-dummydata[6] = DFFEAS(dummydata[5], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+J1_tx_reg[7] = DFFEAS(J1L77, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B1L1 is tmdsenc:hdmitmds[0].enc|Add2~0
-B1L1 = dummydata[7] $ (dummydata[8] $ (dummydata[5] $ (dummydata[6])));
+--Q1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[2]
+--register power-up is low
 
+Q1_shift_reg[2] = DFFEAS(Q1L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B1L4 is tmdsenc:hdmitmds[0].enc|Add4~2
-B1L4 = dummydata[1] $ (dummydata[2]);
 
+--Q1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~1
+Q1L8 = (J1_dffe11 & (J1_tx_reg[7])) # (!J1_dffe11 & ((Q1_shift_reg[2])));
 
---B1L12 is tmdsenc:hdmitmds[0].enc|Add6~0
-B1L12 = (B1L1 & (dummydata[3] $ (dummydata[4] $ (B1L4))));
 
+--B1_qreg[3] is tmdsenc:hdmitmds[0].enc|qreg[3]
+--register power-up is low
 
---B1L2 is tmdsenc:hdmitmds[0].enc|Add2~1
-B1L2 = (dummydata[5] & ((dummydata[6] & ((dummydata[7]) # (dummydata[8]))) # (!dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))))) # (!dummydata[5] & ((dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))) # (!dummydata[6] & (!dummydata[7] & !dummydata[8]))));
+B1_qreg[3] = DFFEAS(B1L59, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
 
---B1L11 is tmdsenc:hdmitmds[0].enc|Add5~1
-B1L11 = (dummydata[3] & (dummydata[4] & (!dummydata[1] & !dummydata[2])));
+--J1_tx_reg[16] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[16]
+--register power-up is low
 
+J1_tx_reg[16] = DFFEAS(B2_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B1L3 is tmdsenc:hdmitmds[0].enc|Add2~2
-B1L3 = (dummydata[5] & (dummydata[6] & (!dummydata[7] & !dummydata[8])));
 
+--Q4_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[2]
+--register power-up is low
 
---B1L13 is tmdsenc:hdmitmds[0].enc|Add6~1
-B1L13 = B1L11 $ (B1L3);
+Q4_shift_reg[2] = DFFEAS(Q4L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B1L14 is tmdsenc:hdmitmds[0].enc|Add6~2
-B1L14 = B1L13 $ (((B1L10 & ((B1L12) # (B1L2))) # (!B1L10 & (B1L12 & B1L2))));
+--Q4L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~1
+Q4L8 = (J1_dffe11 & (J1_tx_reg[16])) # (!J1_dffe11 & ((Q4_shift_reg[2])));
 
 
---B1L15 is tmdsenc:hdmitmds[0].enc|Add6~3
-B1L15 = dummydata[3] $ (dummydata[4] $ (B1L4 $ (B1L1)));
+--B2_qreg[3] is tmdsenc:hdmitmds[1].enc|qreg[3]
+--register power-up is low
 
+B2_qreg[3] = DFFEAS(B2L58, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
---B1L16 is tmdsenc:hdmitmds[0].enc|Add6~4
-B1L16 = B1L10 $ (B1L12 $ (B1L2));
 
+--J1_tx_reg[17] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[17]
+--register power-up is low
 
---B1L49 is tmdsenc:hdmitmds[0].enc|dx[8]~0
-B1L49 = (B1L14 & ((dummydata[1]) # ((B1L15) # (B1L16)))) # (!B1L14 & (dummydata[1] & ((!B1L16) # (!B1L15))));
+J1_tx_reg[17] = DFFEAS(B3_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B1L31 is tmdsenc:hdmitmds[0].enc|Equal0~0
-B1L31 = (!B1_disparity[3] & (!B1_disparity[0] & (!B1_disparity[1] & !B1_disparity[2])));
+--Q3_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[2]
+--register power-up is low
 
+Q3_shift_reg[2] = DFFEAS(Q3L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B1L32 is tmdsenc:hdmitmds[0].enc|always1~0
-B1L32 = (B1L31) # ((B1L14 & (!B1L15 & !B1L16)));
 
+--Q3L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~1
+Q3L8 = (J1_dffe11 & (J1_tx_reg[17])) # (!J1_dffe11 & ((Q3_shift_reg[2])));
 
---B1L5 is tmdsenc:hdmitmds[0].enc|Add4~3
-B1L5 = dummydata[3] $ (dummydata[4] $ (dummydata[1] $ (dummydata[2])));
 
+--J1_tx_reg[26] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[26]
+--register power-up is low
 
---B1L6 is tmdsenc:hdmitmds[0].enc|Add4~4
-B1L6 = dummydata[7] $ (dummydata[5] $ (dummydata[6] $ (!B1L5)));
+J1_tx_reg[26] = DFFEAS(B3_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B1L7 is tmdsenc:hdmitmds[0].enc|Add4~5
-B1L7 = B1L14 $ (B1_disparity[3]);
+--Q6_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[2]
+--register power-up is low
 
+Q6_shift_reg[2] = DFFEAS(Q6L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B1L62 is tmdsenc:hdmitmds[0].enc|qreg~0
-B1L62 = B1L6 $ (((B1L32 & (!B1L49)) # (!B1L32 & ((B1L7)))));
 
+--Q6L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~1
+Q6L8 = (J1_dffe11 & (J1_tx_reg[26])) # (!J1_dffe11 & ((Q6_shift_reg[2])));
 
---B2_qreg[7] is tmdsenc:hdmitmds[1].enc|qreg[7]
+
+--J1_tx_reg[27] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[27]
 --register power-up is low
 
-B2_qreg[7] = DFFEAS(B2L62, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+J1_tx_reg[27] = DFFEAS(B1_qreg[0], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---J1_tx_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]
+--Q5_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[2]
 --register power-up is low
 
-J1_tx_reg[5] = DFFEAS(B3_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+Q5_shift_reg[2] = DFFEAS(Q5L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---Q1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]
---register power-up is low
+--Q5L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~1
+Q5L8 = (J1_dffe11 & (J1_tx_reg[27])) # (!J1_dffe11 & ((Q5_shift_reg[2])));
 
-Q1_shift_reg[3] = DFFEAS(Q1L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--J1_dffe18a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[2]
+--register power-up is low
+
+J1_dffe18a[2] = DFFEAS(J1_dffe16a[2], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
---Q1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~2
-Q1L9 = (J1_dffe11 & (J1_tx_reg[5])) # (!J1_dffe11 & ((Q1_shift_reg[3])));
 
+--J1_dffe14a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[0]
+--register power-up is low
 
---B1L63 is tmdsenc:hdmitmds[0].enc|qreg~1
-B1L63 = (B1L5 $ (((B1L32) # (B1L9)))) # (!B1_denreg);
+J1_dffe14a[0] = DFFEAS(L1_counter_reg_bit[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---J1_tx_reg[14] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]
+--J1_dffe18a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[0]
 --register power-up is low
 
-J1_tx_reg[14] = DFFEAS(J1L88, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+J1_dffe18a[0] = DFFEAS(J1_dffe16a[0], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---Q4_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]
+--J1_dffe14a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[2]
 --register power-up is low
 
-Q4_shift_reg[3] = DFFEAS(Q4L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+J1_dffe14a[2] = DFFEAS(L1_counter_reg_bit[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---Q4L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~2
-Q4L9 = (J1_dffe11 & (J1_tx_reg[14])) # (!J1_dffe11 & ((Q4_shift_reg[3])));
+--J1L44 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~0
+J1L44 = (J1_dffe18a[2] & (J1_dffe14a[2] & (J1_dffe14a[0] $ (!J1_dffe18a[0])))) # (!J1_dffe18a[2] & (!J1_dffe14a[2] & (J1_dffe14a[0] $ (!J1_dffe18a[0]))));
 
 
---dummydata[11] is dummydata[11]
+--J1_dffe18a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe18a[1]
 --register power-up is low
 
-dummydata[11] = DFFEAS(A1L132, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+J1_dffe18a[1] = DFFEAS(J1_dffe16a[1], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---dummydata[12] is dummydata[12]
+--J1_dffe14a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe14a[1]
 --register power-up is low
 
-dummydata[12] = DFFEAS(dummydata[11], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
-
+J1_dffe14a[1] = DFFEAS(L1_counter_reg_bit[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
---dummydata[9] is dummydata[9]
---register power-up is low
 
-dummydata[9] = DFFEAS(dummydata[8], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+--J1L45 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe22~1
+J1L45 = (J1_sync_dffe12a & (J1L44 & (J1_dffe18a[1] $ (!J1_dffe14a[1]))));
 
 
---dummydata[10] is dummydata[10]
+--N2_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[2]
 --register power-up is low
 
-dummydata[10] = DFFEAS(A1L130, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+N2_shift_reg[2] = DFFEAS(N2L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B2L4 is tmdsenc:hdmitmds[1].enc|Add4~2
-B2L4 = dummydata[11] $ (dummydata[12] $ (dummydata[9] $ (!dummydata[10])));
+--N2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~1
+N2L9 = (J1_dffe22) # (N2_shift_reg[2]);
 
 
---B2L29 is tmdsenc:hdmitmds[1].enc|Equal0~0
-B2L29 = (!B2_disparity[3] & (!B2_disparity[0] & (!B2_disparity[1] & !B2_disparity[2])));
+--N1_shift_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[2]
+--register power-up is low
 
+N1_shift_reg[2] = DFFEAS(N1L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B2L10 is tmdsenc:hdmitmds[1].enc|Add5~0
-B2L10 = (dummydata[10] & ((dummydata[11] & ((!dummydata[9]) # (!dummydata[12]))) # (!dummydata[11] & ((dummydata[12]) # (dummydata[9]))))) # (!dummydata[10] & ((dummydata[11] & (!dummydata[12] & !dummydata[9])) # (!dummydata[11] & ((!dummydata[9]) # (!dummydata[12])))));
 
+--N1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~1
+N1L10 = (J1_dffe22) # (N1_shift_reg[2]);
 
---dummydata[15] is dummydata[15]
+
+--F1_dram_q[8] is sdram:sdram|dram_q[8]
 --register power-up is low
 
-dummydata[15] = DFFEAS(dummydata[14], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_q[8] = DFFEAS(sr_dq[8], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---dummydata[16] is dummydata[16]
+--F1_dram_q[0] is sdram:sdram|dram_q[0]
 --register power-up is low
 
-dummydata[16] = DFFEAS(A1L138, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_q[0] = DFFEAS(sr_dq[0], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---dummydata[13] is dummydata[13]
+--F1L163 is sdram:sdram|rd0[0]~0
+F1L163 = (abc_a[0] & (F1_dram_q[8])) # (!abc_a[0] & ((F1_dram_q[0])));
+
+
+--A1L67 is abc_do[0]~0
+A1L67 = (rst_n & F1_rack0_q[0]);
+
+
+--F1_dram_q[9] is sdram:sdram|dram_q[9]
 --register power-up is low
 
-dummydata[13] = DFFEAS(dummydata[12], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_q[9] = DFFEAS(sr_dq[9], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---dummydata[14] is dummydata[14]
+--F1_dram_q[1] is sdram:sdram|dram_q[1]
 --register power-up is low
 
-dummydata[14] = DFFEAS(dummydata[13], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
+F1_dram_q[1] = DFFEAS(sr_dq[1], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---B2L1 is tmdsenc:hdmitmds[1].enc|Add2~0
-B2L1 = dummydata[15] $ (dummydata[16] $ (dummydata[13] $ (!dummydata[14])));
+--F1L164 is sdram:sdram|rd0[1]~1
+F1L164 = (abc_a[0] & (F1_dram_q[9])) # (!abc_a[0] & ((F1_dram_q[1])));
 
 
---B2L5 is tmdsenc:hdmitmds[1].enc|Add4~3
-B2L5 = dummydata[9] $ (!dummydata[10]);
+--F1_dram_q[10] is sdram:sdram|dram_q[10]
+--register power-up is low
 
+F1_dram_q[10] = DFFEAS(sr_dq[10], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
---B2L12 is tmdsenc:hdmitmds[1].enc|Add6~0
-B2L12 = (B2L1 & (dummydata[11] $ (dummydata[12] $ (B2L5))));
 
+--F1_dram_q[2] is sdram:sdram|dram_q[2]
+--register power-up is low
 
---B2L2 is tmdsenc:hdmitmds[1].enc|Add2~1
-B2L2 = (dummydata[16] & ((dummydata[15] & ((!dummydata[14]) # (!dummydata[13]))) # (!dummydata[15] & ((dummydata[13]) # (dummydata[14]))))) # (!dummydata[16] & ((dummydata[15] & (!dummydata[13] & !dummydata[14])) # (!dummydata[15] & ((!dummydata[14]) # (!dummydata[13])))));
+F1_dram_q[2] = DFFEAS(sr_dq[2], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---B2L11 is tmdsenc:hdmitmds[1].enc|Add5~1
-B2L11 = (dummydata[10] & (!dummydata[11] & (!dummydata[12] & !dummydata[9])));
+--F1L165 is sdram:sdram|rd0[2]~2
+F1L165 = (abc_a[0] & (F1_dram_q[10])) # (!abc_a[0] & ((F1_dram_q[2])));
 
 
---B2L3 is tmdsenc:hdmitmds[1].enc|Add2~2
-B2L3 = (dummydata[16] & (!dummydata[15] & (!dummydata[13] & !dummydata[14])));
+--F1_dram_q[11] is sdram:sdram|dram_q[11]
+--register power-up is low
 
+F1_dram_q[11] = DFFEAS(sr_dq[11], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
---B2L13 is tmdsenc:hdmitmds[1].enc|Add6~1
-B2L13 = B2L11 $ (B2L3);
 
+--F1_dram_q[3] is sdram:sdram|dram_q[3]
+--register power-up is low
 
---B2L14 is tmdsenc:hdmitmds[1].enc|Add6~2
-B2L14 = B2L13 $ (((B2L10 & ((B2L12) # (B2L2))) # (!B2L10 & (B2L12 & B2L2))));
+F1_dram_q[3] = DFFEAS(sr_dq[3], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---B2L15 is tmdsenc:hdmitmds[1].enc|Add6~3
-B2L15 = dummydata[11] $ (dummydata[12] $ (B2L5 $ (B2L1)));
+--F1L166 is sdram:sdram|rd0[3]~3
+F1L166 = (abc_a[0] & (F1_dram_q[11])) # (!abc_a[0] & ((F1_dram_q[3])));
 
 
---B2L16 is tmdsenc:hdmitmds[1].enc|Add6~4
-B2L16 = B2L10 $ (B2L12 $ (B2L2));
+--F1_dram_q[12] is sdram:sdram|dram_q[12]
+--register power-up is low
 
+F1_dram_q[12] = DFFEAS(sr_dq[12], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
---B2L30 is tmdsenc:hdmitmds[1].enc|always1~0
-B2L30 = (B2L29) # ((B2L14 & (!B2L15 & !B2L16)));
 
+--F1_dram_q[4] is sdram:sdram|dram_q[4]
+--register power-up is low
+
+F1_dram_q[4] = DFFEAS(sr_dq[4], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
---B2L46 is tmdsenc:hdmitmds[1].enc|dx[8]~0
-B2L46 = (B2L14 & ((dummydata[9]) # ((B2L15) # (B2L16)))) # (!B2L14 & (dummydata[9] & ((!B2L16) # (!B2L15))));
 
+--F1L167 is sdram:sdram|rd0[4]~4
+F1L167 = (abc_a[0] & (F1_dram_q[12])) # (!abc_a[0] & ((F1_dram_q[4])));
 
---B2L6 is tmdsenc:hdmitmds[1].enc|Add4~4
-B2L6 = B2L14 $ (B2_disparity[3]);
 
+--F1_dram_q[13] is sdram:sdram|dram_q[13]
+--register power-up is low
 
---B2L59 is tmdsenc:hdmitmds[1].enc|qreg~0
-B2L59 = (B2L4 $ (((B2L30) # (B2L9)))) # (!B1_denreg);
+F1_dram_q[13] = DFFEAS(sr_dq[13], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---J1_tx_reg[15] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]
+--F1_dram_q[5] is sdram:sdram|dram_q[5]
 --register power-up is low
 
-J1_tx_reg[15] = DFFEAS(B1_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_dram_q[5] = DFFEAS(sr_dq[5], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---Q3_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]
+--F1L168 is sdram:sdram|rd0[5]~5
+F1L168 = (abc_a[0] & (F1_dram_q[13])) # (!abc_a[0] & ((F1_dram_q[5])));
+
+
+--F1_dram_q[14] is sdram:sdram|dram_q[14]
 --register power-up is low
 
-Q3_shift_reg[3] = DFFEAS(Q3L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_dram_q[14] = DFFEAS(sr_dq[14], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---Q3L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~2
-Q3L9 = (J1_dffe11 & (J1_tx_reg[15])) # (!J1_dffe11 & ((Q3_shift_reg[3])));
+--F1_dram_q[6] is sdram:sdram|dram_q[6]
+--register power-up is low
 
+F1_dram_q[6] = DFFEAS(sr_dq[6], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
---B2L60 is tmdsenc:hdmitmds[1].enc|qreg~1
-B2L60 = dummydata[9] $ (((B2L30 & ((B2L46))) # (!B2L30 & (!B2L6))));
 
+--F1L169 is sdram:sdram|rd0[6]~6
+F1L169 = (abc_a[0] & (F1_dram_q[14])) # (!abc_a[0] & ((F1_dram_q[6])));
 
---J1_tx_reg[24] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]
+
+--F1_dram_q[15] is sdram:sdram|dram_q[15]
 --register power-up is low
 
-J1_tx_reg[24] = DFFEAS(B1_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_dram_q[15] = DFFEAS(sr_dq[15], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---Q6_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]
+--F1_dram_q[7] is sdram:sdram|dram_q[7]
 --register power-up is low
 
-Q6_shift_reg[3] = DFFEAS(Q6L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+F1_dram_q[7] = DFFEAS(sr_dq[7], T1_wire_pll1_clk[0],  ,  , F1L109,  ,  ,  ,  );
 
 
---Q6L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~2
-Q6L9 = (J1_dffe11 & (J1_tx_reg[24])) # (!J1_dffe11 & ((Q6_shift_reg[3])));
+--F1L170 is sdram:sdram|rd0[7]~7
+F1L170 = (abc_a[0] & (F1_dram_q[15])) # (!abc_a[0] & ((F1_dram_q[7])));
 
 
---B3L59 is tmdsenc:hdmitmds[2].enc|qreg~2
-B3L59 = dummydata[17] $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
+--F1L51 is sdram:sdram|Selector78~0
+F1L51 = (abc_d[0] & F1_state.st_p0_wr);
 
 
---J1_tx_reg[25] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]
---register power-up is low
+--F1L50 is sdram:sdram|Selector77~0
+F1L50 = (abc_d[1] & F1_state.st_p0_wr);
 
-J1_tx_reg[25] = DFFEAS(B2_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--F1L49 is sdram:sdram|Selector76~0
+F1L49 = (abc_d[2] & F1_state.st_p0_wr);
 
---Q5_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]
---register power-up is low
 
-Q5_shift_reg[3] = DFFEAS(Q5L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--F1L48 is sdram:sdram|Selector75~0
+F1L48 = (abc_d[3] & F1_state.st_p0_wr);
 
 
---Q5L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~2
-Q5L9 = (J1_dffe11 & (J1_tx_reg[25])) # (!J1_dffe11 & ((Q5_shift_reg[3])));
+--F1L47 is sdram:sdram|Selector74~0
+F1L47 = (abc_d[4] & F1_state.st_p0_wr);
 
 
---J1_dffe16a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]
---register power-up is low
+--F1L46 is sdram:sdram|Selector73~0
+F1L46 = (abc_d[5] & F1_state.st_p0_wr);
 
-J1_dffe16a[2] = DFFEAS(J1_dffe14a[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
+--F1L45 is sdram:sdram|Selector72~0
+F1L45 = (abc_d[6] & F1_state.st_p0_wr);
 
---L1_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]
---register power-up is low
 
-L1_counter_reg_bit[0] = DFFEAS(L1L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--F1L44 is sdram:sdram|Selector71~0
+F1L44 = (abc_d[7] & F1_state.st_p0_wr);
 
 
---J1_dffe16a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]
+--B1_denreg is tmdsenc:hdmitmds[0].enc|denreg
 --register power-up is low
 
-J1_dffe16a[0] = DFFEAS(J1_dffe14a[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+B1_denreg = DFFEAS(VCC, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
 
---L1_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]
+--dummydata[0] is dummydata[0]
 --register power-up is low
 
-L1_counter_reg_bit[2] = DFFEAS(L1L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+dummydata[0] = DFFEAS(dummydata[23], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---J1_dffe16a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]
+--dummydata[23] is dummydata[23]
 --register power-up is low
 
-J1_dffe16a[1] = DFFEAS(J1_dffe14a[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
+dummydata[23] = DFFEAS(dummydata[22], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---L1_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]
+--dummydata[21] is dummydata[21]
 --register power-up is low
 
-L1_counter_reg_bit[1] = DFFEAS(L1L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+dummydata[21] = DFFEAS(dummydata[20], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---N2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]
+--dummydata[22] is dummydata[22]
 --register power-up is low
 
-N2_shift_reg[3] = DFFEAS(N2L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+dummydata[22] = DFFEAS(A1L147, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---N2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~2
-N2L10 = (N2_shift_reg[3] & !J1_dffe22);
+--dummydata[19] is dummydata[19]
+--register power-up is low
 
+dummydata[19] = DFFEAS(A1L142, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---N1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]
---register power-up is low
 
-N1_shift_reg[3] = DFFEAS(N1L12, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--dummydata[20] is dummydata[20]
+--register power-up is low
 
+dummydata[20] = DFFEAS(A1L144, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---N1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~2
-N1L11 = (J1_dffe22) # (N1_shift_reg[3]);
 
+--dummydata[17] is dummydata[17]
+--register power-up is low
 
---F1L126 is sdram:sdram|dram_q[0]~0
-F1L126 = (rst_n & (F1_state.st_p0_rd & (F1_op_cycle[2] & F1L1)));
+dummydata[17] = DFFEAS(dummydata[16], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---B3L17 is tmdsenc:hdmitmds[2].enc|Add8~0
-B3L17 = (B3L16 & (!B3L14 & !B3L27));
+--dummydata[18] is dummydata[18]
+--register power-up is low
 
+dummydata[18] = DFFEAS(dummydata[17], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---B3L18 is tmdsenc:hdmitmds[2].enc|Add8~1
-B3L18 = B3L14 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((!B3_disparity[3])))));
 
+--B3L4 is tmdsenc:hdmitmds[2].enc|Add4~2
+B3L4 = dummydata[19] $ (dummydata[20] $ (dummydata[17] $ (!dummydata[18])));
 
---B3L19 is tmdsenc:hdmitmds[2].enc|Add8~2
-B3L19 = ((B3L17 & ((B3L15) # (B3L44)))) # (!B3L18);
 
+--B3L5 is tmdsenc:hdmitmds[2].enc|Add4~3
+B3L5 = dummydata[23] $ (dummydata[21] $ (dummydata[22] $ (B3L4)));
 
---B3L20 is tmdsenc:hdmitmds[2].enc|Add8~3
-B3L20 = (B3L28 & (((!B3L44)))) # (!B3L28 & (B3L14 $ ((B3_disparity[3]))));
 
+--B3L27 is tmdsenc:hdmitmds[2].enc|Equal0~0
+B3L27 = (!B3_disparity[3] & (!B3_disparity[0] & (!B3_disparity[1] & !B3_disparity[2])));
 
---B3L21 is tmdsenc:hdmitmds[2].enc|Add8~4
-B3L21 = (!dummydata[17] & (!B3L15 & (!B3L16 & !B3L27)));
 
+--B3L10 is tmdsenc:hdmitmds[2].enc|Add5~0
+B3L10 = (dummydata[19] & ((dummydata[20] & ((dummydata[17]) # (dummydata[18]))) # (!dummydata[20] & (dummydata[17] & dummydata[18])))) # (!dummydata[19] & ((dummydata[20] & ((!dummydata[18]) # (!dummydata[17]))) # (!dummydata[20] & ((dummydata[17]) # (dummydata[18])))));
 
---B3L22 is tmdsenc:hdmitmds[2].enc|Add8~5
-B3L22 = (B3L16 & ((B3L44 & ((!B3L28))) # (!B3L44 & (B3L15))));
 
+--B3L1 is tmdsenc:hdmitmds[2].enc|Add2~0
+B3L1 = dummydata[0] $ (dummydata[23] $ (dummydata[21] $ (!dummydata[22])));
 
---B3L23 is tmdsenc:hdmitmds[2].enc|Add8~6
-B3L23 = (B3L14 & ((B3L20) # ((B3L22)))) # (!B3L14 & (!B3L22 & ((B3L21) # (!B3L20))));
 
+--B3L6 is tmdsenc:hdmitmds[2].enc|Add4~4
+B3L6 = dummydata[17] $ (dummydata[18]);
 
---B3L24 is tmdsenc:hdmitmds[2].enc|Add8~7
-B3L24 = (B3L28) # ((!B3L15 & (B3L14 $ (B3_disparity[3]))));
 
+--B3L12 is tmdsenc:hdmitmds[2].enc|Add6~0
+B3L12 = (B3L1 & (dummydata[19] $ (dummydata[20] $ (!B3L6))));
 
---B3L25 is tmdsenc:hdmitmds[2].enc|Add8~8
-B3L25 = B3L16 $ (((B3L44 & ((!B3L24))) # (!B3L44 & ((B3L15) # (B3L24)))));
 
+--B3L2 is tmdsenc:hdmitmds[2].enc|Add2~1
+B3L2 = (dummydata[21] & ((dummydata[0] & ((!dummydata[22]) # (!dummydata[23]))) # (!dummydata[0] & ((dummydata[23]) # (dummydata[22]))))) # (!dummydata[21] & ((dummydata[0] & (!dummydata[23] & !dummydata[22])) # (!dummydata[0] & ((!dummydata[22]) # (!dummydata[23])))));
 
---B3L26 is tmdsenc:hdmitmds[2].enc|Add8~9
-B3L26 = (B3L15 & ((B3L14) # ((!dummydata[17] & !B3L16)))) # (!B3L15 & (dummydata[17] & ((!B3L16) # (!B3L14))));
 
+--B3L11 is tmdsenc:hdmitmds[2].enc|Add5~1
+B3L11 = (dummydata[20] & (dummydata[17] & (dummydata[18] & !dummydata[19])));
 
---B1L64 is tmdsenc:hdmitmds[0].enc|qreg~2
-B1L64 = B1L6 $ (((!B1L32 & (B1L49 $ (!B1L7)))));
 
+--B3L3 is tmdsenc:hdmitmds[2].enc|Add2~2
+B3L3 = (dummydata[21] & (!dummydata[0] & (!dummydata[23] & !dummydata[22])));
 
---B1L65 is tmdsenc:hdmitmds[0].enc|qreg~3
-B1L65 = (dummydata[8] $ (B1L64)) # (!B1_denreg);
 
+--B3L13 is tmdsenc:hdmitmds[2].enc|Add6~1
+B3L13 = B3L11 $ (B3L3);
 
---B2_qreg[8] is tmdsenc:hdmitmds[1].enc|qreg[8]
---register power-up is low
 
-B2_qreg[8] = DFFEAS(B2L64, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+--B3L14 is tmdsenc:hdmitmds[2].enc|Add6~2
+B3L14 = B3L13 $ (((B3L10 & ((B3L12) # (B3L2))) # (!B3L10 & (B3L12 & B3L2))));
 
 
---J1_tx_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]
---register power-up is low
+--B3L15 is tmdsenc:hdmitmds[2].enc|Add6~3
+B3L15 = dummydata[19] $ (dummydata[20] $ (B3L6 $ (!B3L1)));
 
-J1_tx_reg[2] = DFFEAS(J1L70, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--B3L16 is tmdsenc:hdmitmds[2].enc|Add6~4
+B3L16 = B3L10 $ (B3L12 $ (B3L2));
 
---Q2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]
---register power-up is low
 
-Q2_shift_reg[4] = DFFEAS(Q2L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--B3L28 is tmdsenc:hdmitmds[2].enc|always1~0
+B3L28 = (B3L27) # ((B3L14 & (!B3L15 & !B3L16)));
 
 
---Q2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~3
-Q2L10 = (J1_dffe11 & (J1_tx_reg[2])) # (!J1_dffe11 & ((Q2_shift_reg[4])));
+--B3L44 is tmdsenc:hdmitmds[2].enc|dx[8]~0
+B3L44 = (B3L14 & ((B3L15) # ((B3L16) # (!dummydata[17])))) # (!B3L14 & (!dummydata[17] & ((!B3L16) # (!B3L15))));
 
 
---L2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|cout_actual~0
-L2L11 = (J1_sync_dffe12a & (L2_counter_reg_bit[2] & (!L2_counter_reg_bit[0] & !L2_counter_reg_bit[1])));
+--B3L7 is tmdsenc:hdmitmds[2].enc|Add4~5
+B3L7 = B3L14 $ (B3_disparity[3]);
 
 
---L2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~0
-L2L8 = (!L2_counter_reg_bit[0] & (!L2L24 & !L2L11));
+--B3L57 is tmdsenc:hdmitmds[2].enc|qreg~0
+B3L57 = B3L5 $ (((!B3L28 & (B3L44 $ (!B3L7)))));
 
 
---L2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~1
-L2L9 = (L2L24 & (((!J1_sync_dffe12a)))) # (!L2L24 & (L2_wire_counter_comb_bita_2combout[0] & (!L2L11)));
+--B3L58 is tmdsenc:hdmitmds[2].enc|qreg~1
+B3L58 = (dummydata[0] $ (B3L57)) # (!B1_denreg);
 
 
---L2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~2
-L2L10 = (L2_wire_counter_comb_bita_1combout[0] & (!L2L24 & !L2L11));
+--vid_rst_n is vid_rst_n
+--register power-up is low
 
+vid_rst_n = DFFEAS(rst_n, T1_wire_pll1_clk[2], !A1L25,  ,  ,  ,  ,  ,  );
 
---B1L17 is tmdsenc:hdmitmds[0].enc|Add8~4
-B1L17 = (B1L15 & (!B1L14)) # (!B1L15 & ((dummydata[1])));
 
+--B1_qreg[7] is tmdsenc:hdmitmds[0].enc|qreg[7]
+--register power-up is low
 
---B1L18 is tmdsenc:hdmitmds[0].enc|Add8~5
-B1L18 = (B1L17 & ((B1L16 & (!B1L31 & !B1L14)) # (!B1L16 & ((B1L14)))));
+B1_qreg[7] = DFFEAS(B1L61, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
 
---B1L19 is tmdsenc:hdmitmds[0].enc|Add8~6
-B1L19 = (B1L14 & ((B1L32 & ((!B1L27))) # (!B1L32 & (!B1L18 & B1L27)))) # (!B1L14 & ((B1L18) # ((B1L27))));
+--J1_tx_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[4]
+--register power-up is low
 
+J1_tx_reg[4] = DFFEAS(B2_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B1L30 is tmdsenc:hdmitmds[0].enc|Add12~0
-B1L30 = (dummydata[1]) # ((B1L15) # ((B1L16 & B1L14)));
 
+--Q2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[3]
+--register power-up is low
 
---B1L20 is tmdsenc:hdmitmds[0].enc|Add8~7
-B1L20 = (B1L7 & ((B1L15) # ((B1L16) # (!dummydata[1]))));
+Q2_shift_reg[3] = DFFEAS(Q2L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B1L21 is tmdsenc:hdmitmds[0].enc|Add8~8
-B1L21 = (!B1L32 & (!B1L20 & ((!B1L30) # (!B1L16))));
+--Q2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~2
+Q2L9 = (J1_dffe11 & (J1_tx_reg[4])) # (!J1_dffe11 & ((Q2_shift_reg[3])));
 
 
---B1L22 is tmdsenc:hdmitmds[0].enc|Add8~9
-B1L22 = B1L14 $ (((B1L21) # ((B1L32 & B1L49))));
+--J1_dffe5a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[2]
+--register power-up is low
 
+J1_dffe5a[2] = DFFEAS(J1_dffe3a[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
---B1L23 is tmdsenc:hdmitmds[0].enc|Add8~10
-B1L23 = (B1L32 & (B1L49)) # (!B1L32 & ((B1L14 $ (B1_disparity[3]))));
 
+--L2_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[0]
+--register power-up is low
 
---B1L29 is tmdsenc:hdmitmds[0].enc|Add10~0
-B1L29 = (dummydata[1] & ((B1L15 $ (B1L16)))) # (!dummydata[1] & (((B1L14 & !B1L15)) # (!B1L16)));
+L2_counter_reg_bit[0] = DFFEAS(L2L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B1L24 is tmdsenc:hdmitmds[0].enc|Add8~11
-B1L24 = (B1L23 & (B1L29)) # (!B1L23 & ((B1L16 $ (B1L30))));
+--J1_dffe5a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[0]
+--register power-up is low
 
+J1_dffe5a[0] = DFFEAS(J1_dffe3a[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
---B1L25 is tmdsenc:hdmitmds[0].enc|Add8~12
-B1L25 = (B1L32 & (B1L16 $ ((!B1L23)))) # (!B1L32 & (((B1L24))));
 
+--L2_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[2]
+--register power-up is low
 
---B1L26 is tmdsenc:hdmitmds[0].enc|Add8~13
-B1L26 = (B1L15 & ((B1L14) # ((dummydata[1] & !B1L16)))) # (!B1L15 & (!dummydata[1] & ((!B1L16) # (!B1L14))));
+L2_counter_reg_bit[2] = DFFEAS(L2L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B2L7 is tmdsenc:hdmitmds[1].enc|Add4~5
-B2L7 = dummydata[15] $ (dummydata[13] $ (dummydata[14] $ (!B2L4)));
+--J1_dffe6a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[2]
+--register power-up is low
 
+J1_dffe6a[2] = DFFEAS(J1_dffe4a[2], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
---B2L61 is tmdsenc:hdmitmds[1].enc|qreg~2
-B2L61 = B2L7 $ (((!B2L30 & (B2L46 $ (!B2L6)))));
 
+--J1_dffe6a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[0]
+--register power-up is low
 
---B2L62 is tmdsenc:hdmitmds[1].enc|qreg~3
-B2L62 = (dummydata[16] $ (!B2L61)) # (!B1_denreg);
+J1_dffe6a[0] = DFFEAS(J1_dffe4a[0], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---B3_qreg[8] is tmdsenc:hdmitmds[2].enc|qreg[8]
+--J1_dffe6a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe6a[1]
 --register power-up is low
 
-B3_qreg[8] = DFFEAS(B3L62, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+J1_dffe6a[1] = DFFEAS(J1_dffe4a[1], J1_fast_clock,  ,  , !J1_sync_dffe12a,  ,  ,  ,  );
 
 
---J1_tx_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]
+--L2_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit[1]
 --register power-up is low
 
-J1_tx_reg[3] = DFFEAS(B1_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+L2_counter_reg_bit[1] = DFFEAS(L2L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---Q1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]
+--J1_dffe5a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe5a[1]
 --register power-up is low
 
-Q1_shift_reg[4] = DFFEAS(Q1L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+J1_dffe5a[1] = DFFEAS(J1_dffe3a[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---Q1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~3
-Q1L10 = (J1_dffe11 & (J1_tx_reg[3])) # (!J1_dffe11 & ((Q1_shift_reg[4])));
+--dummydata[3] is dummydata[3]
+--register power-up is low
 
+dummydata[3] = DFFEAS(A1L121, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---B2L47 is tmdsenc:hdmitmds[1].enc|dx~1
-B2L47 = dummydata[13] $ (!B2L4);
 
+--dummydata[4] is dummydata[4]
+--register power-up is low
 
---B2L63 is tmdsenc:hdmitmds[1].enc|qreg~4
-B2L63 = B2L47 $ (((B2L30 & (!B2L46)) # (!B2L30 & ((B2L6)))));
+dummydata[4] = DFFEAS(dummydata[3], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---B3_qreg[5] is tmdsenc:hdmitmds[2].enc|qreg[5]
+--dummydata[1] is dummydata[1]
 --register power-up is low
 
-B3_qreg[5] = DFFEAS(B3L64, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+dummydata[1] = DFFEAS(dummydata[0], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---J1_tx_reg[12] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]
+--dummydata[2] is dummydata[2]
 --register power-up is low
 
-J1_tx_reg[12] = DFFEAS(J1L84, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
-
+dummydata[2] = DFFEAS(dummydata[1], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---Q4_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]
---register power-up is low
 
-Q4_shift_reg[4] = DFFEAS(Q4L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--B1L10 is tmdsenc:hdmitmds[0].enc|Add5~0
+B1L10 = (dummydata[3] & ((dummydata[4] & ((dummydata[1]) # (dummydata[2]))) # (!dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))))) # (!dummydata[3] & ((dummydata[4] & ((!dummydata[2]) # (!dummydata[1]))) # (!dummydata[4] & (!dummydata[1] & !dummydata[2]))));
 
 
---Q4L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~3
-Q4L10 = (J1_dffe11 & (J1_tx_reg[12])) # (!J1_dffe11 & ((Q4_shift_reg[4])));
+--dummydata[7] is dummydata[7]
+--register power-up is low
 
+dummydata[7] = DFFEAS(A1L126, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---B2L17 is tmdsenc:hdmitmds[1].enc|Add8~4
-B2L17 = (B2L30 & (B2L14 $ (B2L46)));
 
+--dummydata[8] is dummydata[8]
+--register power-up is low
 
---B2L18 is tmdsenc:hdmitmds[1].enc|Add8~5
-B2L18 = (B2L16 & (!B2L14 & !B2L29));
+dummydata[8] = DFFEAS(dummydata[7], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---B2L19 is tmdsenc:hdmitmds[1].enc|Add8~6
-B2L19 = (B2L17) # ((B2L18 & ((B2L15) # (B2L46))));
+--dummydata[5] is dummydata[5]
+--register power-up is low
 
+dummydata[5] = DFFEAS(dummydata[4], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---B2L20 is tmdsenc:hdmitmds[1].enc|Add8~7
-B2L20 = (B2L15) # ((B2L16) # ((!B2L14) # (!dummydata[9])));
 
+--dummydata[6] is dummydata[6]
+--register power-up is low
 
---B2L21 is tmdsenc:hdmitmds[1].enc|Add8~8
-B2L21 = (B2L19) # ((B2L6 & (B2L20 & !B2L30)));
+dummydata[6] = DFFEAS(dummydata[5], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---B2L22 is tmdsenc:hdmitmds[1].enc|Add8~9
-B2L22 = (B2L15 & (B2L16)) # (!B2L15 & ((dummydata[9])));
+--B1L1 is tmdsenc:hdmitmds[0].enc|Add2~0
+B1L1 = dummydata[7] $ (dummydata[8] $ (dummydata[5] $ (dummydata[6])));
 
 
---B2L23 is tmdsenc:hdmitmds[1].enc|Add8~10
-B2L23 = B2L14 $ (((B2L30 & (B2L46)) # (!B2L30 & ((!B2L27)))));
+--B1L4 is tmdsenc:hdmitmds[0].enc|Add4~2
+B1L4 = dummydata[1] $ (dummydata[2]);
 
 
---B2L24 is tmdsenc:hdmitmds[1].enc|Add8~11
-B2L24 = (B2L30) # ((!B2L15 & (B2L14 $ (B2_disparity[3]))));
+--B1L12 is tmdsenc:hdmitmds[0].enc|Add6~0
+B1L12 = (B1L1 & (dummydata[3] $ (dummydata[4] $ (B1L4))));
 
 
---B2L25 is tmdsenc:hdmitmds[1].enc|Add8~12
-B2L25 = B2L16 $ (((B2L46 & ((!B2L24))) # (!B2L46 & ((B2L15) # (B2L24)))));
+--B1L2 is tmdsenc:hdmitmds[0].enc|Add2~1
+B1L2 = (dummydata[5] & ((dummydata[6] & ((dummydata[7]) # (dummydata[8]))) # (!dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))))) # (!dummydata[5] & ((dummydata[6] & ((!dummydata[8]) # (!dummydata[7]))) # (!dummydata[6] & (!dummydata[7] & !dummydata[8]))));
 
 
---B2L26 is tmdsenc:hdmitmds[1].enc|Add8~13
-B2L26 = (B2L15 & ((B2L14) # ((dummydata[9] & !B2L16)))) # (!B2L15 & (!dummydata[9] & ((!B2L16) # (!B2L14))));
+--B1L11 is tmdsenc:hdmitmds[0].enc|Add5~1
+B1L11 = (dummydata[3] & (dummydata[4] & (!dummydata[1] & !dummydata[2])));
 
 
---B3L45 is tmdsenc:hdmitmds[2].enc|dx~1
-B3L45 = dummydata[21] $ (B3L4);
+--B1L3 is tmdsenc:hdmitmds[0].enc|Add2~2
+B1L3 = (dummydata[5] & (dummydata[6] & (!dummydata[7] & !dummydata[8])));
 
 
---B3L60 is tmdsenc:hdmitmds[2].enc|qreg~3
-B3L60 = B3L45 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
+--B1L13 is tmdsenc:hdmitmds[0].enc|Add6~1
+B1L13 = B1L11 $ (B1L3);
 
 
---J1_tx_reg[13] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]
---register power-up is low
+--B1L14 is tmdsenc:hdmitmds[0].enc|Add6~2
+B1L14 = B1L13 $ (((B1L10 & ((B1L12) # (B1L2))) # (!B1L10 & (B1L12 & B1L2))));
 
-J1_tx_reg[13] = DFFEAS(J1L86, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--B1L15 is tmdsenc:hdmitmds[0].enc|Add6~3
+B1L15 = dummydata[3] $ (dummydata[4] $ (B1L4 $ (B1L1)));
 
---Q3_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]
---register power-up is low
 
-Q3_shift_reg[4] = DFFEAS(Q3L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--B1L16 is tmdsenc:hdmitmds[0].enc|Add6~4
+B1L16 = B1L10 $ (B1L12 $ (B1L2));
 
 
---Q3L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~3
-Q3L10 = (J1_dffe11 & (J1_tx_reg[13])) # (!J1_dffe11 & ((Q3_shift_reg[4])));
+--B1L45 is tmdsenc:hdmitmds[0].enc|dx[8]~0
+B1L45 = (B1L14 & ((dummydata[1]) # ((B1L15) # (B1L16)))) # (!B1L14 & (dummydata[1] & ((!B1L16) # (!B1L15))));
 
 
---B3L61 is tmdsenc:hdmitmds[2].enc|qreg~4
-B3L61 = B3L6 $ (((!B3L28 & (B3L44 $ (!B3L7)))));
+--B1L27 is tmdsenc:hdmitmds[0].enc|Equal0~0
+B1L27 = (!B1_disparity[3] & (!B1_disparity[0] & (!B1_disparity[1] & !B1_disparity[2])));
 
 
---J1_tx_reg[22] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]
---register power-up is low
+--B1L28 is tmdsenc:hdmitmds[0].enc|always1~0
+B1L28 = (B1L27) # ((B1L14 & (!B1L15 & !B1L16)));
 
-J1_tx_reg[22] = DFFEAS(B2_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--B1L5 is tmdsenc:hdmitmds[0].enc|Add4~3
+B1L5 = dummydata[3] $ (dummydata[4] $ (dummydata[1] $ (dummydata[2])));
 
---Q6_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]
---register power-up is low
 
-Q6_shift_reg[4] = DFFEAS(Q6L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--B1L6 is tmdsenc:hdmitmds[0].enc|Add4~4
+B1L6 = dummydata[7] $ (dummydata[5] $ (dummydata[6] $ (!B1L5)));
 
 
---Q6L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~3
-Q6L10 = (J1_dffe11 & (J1_tx_reg[22])) # (!J1_dffe11 & ((Q6_shift_reg[4])));
+--B1L7 is tmdsenc:hdmitmds[0].enc|Add4~5
+B1L7 = B1L14 $ (B1_disparity[3]);
 
 
---B1L66 is tmdsenc:hdmitmds[0].enc|qreg~4
-B1L66 = dummydata[1] $ (((B1L32 & ((B1L49))) # (!B1L32 & (!B1L7))));
+--B1L58 is tmdsenc:hdmitmds[0].enc|qreg~0
+B1L58 = B1L6 $ (((B1L28 & (!B1L45)) # (!B1L28 & ((B1L7)))));
 
 
---J1_tx_reg[23] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]
+--B2_qreg[7] is tmdsenc:hdmitmds[1].enc|qreg[7]
 --register power-up is low
 
-J1_tx_reg[23] = DFFEAS(B3_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+B2_qreg[7] = DFFEAS(B2L61, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
 
---Q5_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]
+--J1_tx_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[5]
 --register power-up is low
 
-Q5_shift_reg[4] = DFFEAS(Q5L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+J1_tx_reg[5] = DFFEAS(B3_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---Q5L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~3
-Q5L10 = (J1_dffe11 & (J1_tx_reg[23])) # (!J1_dffe11 & ((Q5_shift_reg[4])));
+--Q1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[3]
+--register power-up is low
 
+Q1_shift_reg[3] = DFFEAS(Q1L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---L1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|cout_actual~0
-L1L11 = (J1_sync_dffe12a & (L1_counter_reg_bit[2] & (!L1_counter_reg_bit[0] & !L1_counter_reg_bit[1])));
 
+--Q1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~2
+Q1L9 = (J1_dffe11 & (J1_tx_reg[5])) # (!J1_dffe11 & ((Q1_shift_reg[3])));
 
---L1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~0
-L1L8 = (!L1_counter_reg_bit[0] & (!L1L24 & !L1L11));
 
+--B1L59 is tmdsenc:hdmitmds[0].enc|qreg~1
+B1L59 = (B1L5 $ (((B1L28) # (B1L9)))) # (!B1_denreg);
 
---L1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~1
-L1L9 = (L1L24 & (((!J1_sync_dffe12a)))) # (!L1L24 & (L1_wire_counter_comb_bita_2combout[0] & (!L1L11)));
 
+--J1_tx_reg[14] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]
+--register power-up is low
 
---L1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~2
-L1L10 = (L1_wire_counter_comb_bita_1combout[0] & (!L1L24 & !L1L11));
+J1_tx_reg[14] = DFFEAS(J1L88, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---N2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]
+--Q4_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[3]
 --register power-up is low
 
-N2_shift_reg[4] = DFFEAS(N2L12, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+Q4_shift_reg[3] = DFFEAS(Q4L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---N2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~3
-N2L11 = (N2_shift_reg[4] & !J1_dffe22);
+--Q4L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~2
+Q4L9 = (J1_dffe11 & (J1_tx_reg[14])) # (!J1_dffe11 & ((Q4_shift_reg[3])));
 
 
---N1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]
+--dummydata[11] is dummydata[11]
 --register power-up is low
 
-N1_shift_reg[4] = DFFEAS(N1L13, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
-
+dummydata[11] = DFFEAS(A1L132, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---N1L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~3
-N1L12 = (N1_shift_reg[4] & !J1_dffe22);
 
+--dummydata[12] is dummydata[12]
+--register power-up is low
 
---B2L64 is tmdsenc:hdmitmds[1].enc|qreg~5
-B2L64 = (B2L46) # (!B1_denreg);
+dummydata[12] = DFFEAS(dummydata[11], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---B3_qreg[9] is tmdsenc:hdmitmds[2].enc|qreg[9]
+--dummydata[9] is dummydata[9]
 --register power-up is low
 
-B3_qreg[9] = DFFEAS(B3L65, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+dummydata[9] = DFFEAS(dummydata[8], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---J1_tx_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]
+--dummydata[10] is dummydata[10]
 --register power-up is low
 
-J1_tx_reg[0] = DFFEAS(J1L66, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
-
+dummydata[10] = DFFEAS(A1L130, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---Q2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~4
-Q2L11 = (J1_dffe11 & J1_tx_reg[0]);
 
+--B2L4 is tmdsenc:hdmitmds[1].enc|Add4~2
+B2L4 = dummydata[11] $ (dummydata[12] $ (dummydata[9] $ (!dummydata[10])));
 
---B3L62 is tmdsenc:hdmitmds[2].enc|qreg~5
-B3L62 = (B3L44) # (!B1_denreg);
 
+--B2L28 is tmdsenc:hdmitmds[1].enc|Equal0~0
+B2L28 = (!B2_disparity[3] & (!B2_disparity[0] & (!B2_disparity[1] & !B2_disparity[2])));
 
---B1_qreg[8] is tmdsenc:hdmitmds[0].enc|qreg[8]
---register power-up is low
 
-B1_qreg[8] = DFFEAS(B1L69, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+--B2L10 is tmdsenc:hdmitmds[1].enc|Add5~0
+B2L10 = (dummydata[10] & ((dummydata[11] & ((!dummydata[9]) # (!dummydata[12]))) # (!dummydata[11] & ((dummydata[12]) # (dummydata[9]))))) # (!dummydata[10] & ((dummydata[11] & (!dummydata[12] & !dummydata[9])) # (!dummydata[11] & ((!dummydata[9]) # (!dummydata[12])))));
 
 
---J1_tx_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]
+--dummydata[15] is dummydata[15]
 --register power-up is low
 
-J1_tx_reg[1] = DFFEAS(J1L68, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+dummydata[15] = DFFEAS(dummydata[14], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---Q1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~4
-Q1L11 = (J1_dffe11 & J1_tx_reg[1]);
+--dummydata[16] is dummydata[16]
+--register power-up is low
 
+dummydata[16] = DFFEAS(A1L138, T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
---B3L63 is tmdsenc:hdmitmds[2].enc|qreg~6
-B3L63 = dummydata[21] $ (dummydata[22] $ (!B3L4));
 
+--dummydata[13] is dummydata[13]
+--register power-up is low
 
---B3L64 is tmdsenc:hdmitmds[2].enc|qreg~7
-B3L64 = (B3L63 $ (((B3L28) # (B3L9)))) # (!B1_denreg);
+dummydata[13] = DFFEAS(dummydata[12], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---B1_qreg[5] is tmdsenc:hdmitmds[0].enc|qreg[5]
+--dummydata[14] is dummydata[14]
 --register power-up is low
 
-B1_qreg[5] = DFFEAS(B1L71, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+dummydata[14] = DFFEAS(dummydata[13], T1_wire_pll1_clk[2],  ,  ,  ,  ,  ,  ,  );
 
 
---J1_tx_reg[10] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]
---register power-up is low
+--B2L1 is tmdsenc:hdmitmds[1].enc|Add2~0
+B2L1 = dummydata[15] $ (dummydata[16] $ (dummydata[13] $ (!dummydata[14])));
 
-J1_tx_reg[10] = DFFEAS(B2_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--B2L5 is tmdsenc:hdmitmds[1].enc|Add4~3
+B2L5 = dummydata[9] $ (!dummydata[10]);
 
---Q4L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~4
-Q4L11 = (J1_dffe11 & J1_tx_reg[10]);
 
+--B2L12 is tmdsenc:hdmitmds[1].enc|Add6~0
+B2L12 = (B2L1 & (dummydata[11] $ (dummydata[12] $ (B2L5))));
 
---B1L50 is tmdsenc:hdmitmds[0].enc|dx~1
-B1L50 = dummydata[5] $ (B1L5);
 
+--B2L2 is tmdsenc:hdmitmds[1].enc|Add2~1
+B2L2 = (dummydata[16] & ((dummydata[15] & ((!dummydata[14]) # (!dummydata[13]))) # (!dummydata[15] & ((dummydata[13]) # (dummydata[14]))))) # (!dummydata[16] & ((dummydata[15] & (!dummydata[13] & !dummydata[14])) # (!dummydata[15] & ((!dummydata[14]) # (!dummydata[13])))));
 
---B1L67 is tmdsenc:hdmitmds[0].enc|qreg~5
-B1L67 = B1L50 $ (((B1L32 & (!B1L49)) # (!B1L32 & ((B1L7)))));
 
+--B2L11 is tmdsenc:hdmitmds[1].enc|Add5~1
+B2L11 = (dummydata[10] & (!dummydata[11] & (!dummydata[12] & !dummydata[9])));
 
---B2_qreg[5] is tmdsenc:hdmitmds[1].enc|qreg[5]
---register power-up is low
 
-B2_qreg[5] = DFFEAS(B2L67, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+--B2L3 is tmdsenc:hdmitmds[1].enc|Add2~2
+B2L3 = (dummydata[16] & (!dummydata[15] & (!dummydata[13] & !dummydata[14])));
 
 
---J1_tx_reg[11] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]
---register power-up is low
+--B2L13 is tmdsenc:hdmitmds[1].enc|Add6~1
+B2L13 = B2L11 $ (B2L3);
 
-J1_tx_reg[11] = DFFEAS(B3_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--B2L14 is tmdsenc:hdmitmds[1].enc|Add6~2
+B2L14 = B2L13 $ (((B2L10 & ((B2L12) # (B2L2))) # (!B2L10 & (B2L12 & B2L2))));
 
---Q3L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~4
-Q3L11 = (J1_dffe11 & J1_tx_reg[11]);
 
+--B2L15 is tmdsenc:hdmitmds[1].enc|Add6~3
+B2L15 = dummydata[11] $ (dummydata[12] $ (B2L5 $ (B2L1)));
 
---B1L68 is tmdsenc:hdmitmds[0].enc|qreg~6
-B1L68 = B1L4 $ (((!B1L32 & (B1L49 $ (!B1L7)))));
 
+--B2L16 is tmdsenc:hdmitmds[1].enc|Add6~4
+B2L16 = B2L10 $ (B2L12 $ (B2L2));
 
---J1_tx_reg[20] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]
---register power-up is low
 
-J1_tx_reg[20] = DFFEAS(J1L97, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+--B2L29 is tmdsenc:hdmitmds[1].enc|always1~0
+B2L29 = (B2L28) # ((B2L14 & (!B2L15 & !B2L16)));
 
 
---Q6L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~4
-Q6L11 = (J1_dffe11 & J1_tx_reg[20]);
+--B2L45 is tmdsenc:hdmitmds[1].enc|dx[8]~0
+B2L45 = (B2L14 & ((dummydata[9]) # ((B2L15) # (B2L16)))) # (!B2L14 & (dummydata[9] & ((!B2L16) # (!B2L15))));
 
 
---B2L65 is tmdsenc:hdmitmds[1].enc|qreg~6
-B2L65 = B2L5 $ (((!B2L30 & (B2L46 $ (!B2L6)))));
+--B2L6 is tmdsenc:hdmitmds[1].enc|Add4~4
+B2L6 = B2L14 $ (B2_disparity[3]);
 
 
---J1_tx_reg[21] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]
---register power-up is low
+--B2L58 is tmdsenc:hdmitmds[1].enc|qreg~0
+B2L58 = (B2L4 $ (((B2L29) # (B2L9)))) # (!B1_denreg);
 
-J1_tx_reg[21] = DFFEAS(B1_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--J1_tx_reg[15] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[15]
+--register power-up is low
 
---Q5L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~4
-Q5L11 = (J1_dffe11 & J1_tx_reg[21]);
+J1_tx_reg[15] = DFFEAS(B1_qreg[4], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---N1_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]
+--Q3_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[3]
 --register power-up is low
 
-N1_shift_reg[6] = DFFEAS(N1L14, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+Q3_shift_reg[3] = DFFEAS(Q3L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---N2L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~4
-N2L12 = (N1_shift_reg[6] & !J1_dffe22);
+--Q3L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~2
+Q3L9 = (J1_dffe11 & (J1_tx_reg[15])) # (!J1_dffe11 & ((Q3_shift_reg[3])));
 
 
---N1_shift_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]
---register power-up is low
+--B2L59 is tmdsenc:hdmitmds[1].enc|qreg~1
+B2L59 = dummydata[9] $ (((B2L29 & ((B2L45))) # (!B2L29 & (!B2L6))));
 
-N1_shift_reg[5] = DFFEAS(N1L15, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
+--J1_tx_reg[24] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[24]
+--register power-up is low
 
---N1L13 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~4
-N1L13 = (N1_shift_reg[5] & !J1_dffe22);
+J1_tx_reg[24] = DFFEAS(B1_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B3L65 is tmdsenc:hdmitmds[2].enc|qreg~8
-B3L65 = (B1_denreg & ((B3L28 & ((B3L44))) # (!B3L28 & (!B3L7))));
+--Q6_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[3]
+--register power-up is low
 
+Q6_shift_reg[3] = DFFEAS(Q6L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B1_qreg[9] is tmdsenc:hdmitmds[0].enc|qreg[9]
---register power-up is low
 
-B1_qreg[9] = DFFEAS(B1L72, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
+--Q6L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~2
+Q6L9 = (J1_dffe11 & (J1_tx_reg[24])) # (!J1_dffe11 & ((Q6_shift_reg[3])));
 
 
---B1L69 is tmdsenc:hdmitmds[0].enc|qreg~7
-B1L69 = (B1L49) # (!B1_denreg);
+--B3L59 is tmdsenc:hdmitmds[2].enc|qreg~2
+B3L59 = dummydata[17] $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
 
 
---B2_qreg[9] is tmdsenc:hdmitmds[1].enc|qreg[9]
+--J1_tx_reg[25] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[25]
 --register power-up is low
 
-B2_qreg[9] = DFFEAS(B2L69, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
-
+J1_tx_reg[25] = DFFEAS(B2_qreg[1], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B1L70 is tmdsenc:hdmitmds[0].enc|qreg~8
-B1L70 = dummydata[5] $ (dummydata[6] $ (B1L5));
 
+--Q5_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[3]
+--register power-up is low
 
---B1L71 is tmdsenc:hdmitmds[0].enc|qreg~9
-B1L71 = (B1L70 $ (((B1L32) # (B1L9)))) # (!B1_denreg);
+Q5_shift_reg[3] = DFFEAS(Q5L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B2L66 is tmdsenc:hdmitmds[1].enc|qreg~7
-B2L66 = dummydata[13] $ (dummydata[14] $ (B2L4));
+--Q5L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~2
+Q5L9 = (J1_dffe11 & (J1_tx_reg[25])) # (!J1_dffe11 & ((Q5_shift_reg[3])));
 
 
---B2L67 is tmdsenc:hdmitmds[1].enc|qreg~8
-B2L67 = (B2L66 $ (((B2L30) # (B2L9)))) # (!B1_denreg);
+--J1_dffe16a[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[2]
+--register power-up is low
 
+J1_dffe16a[2] = DFFEAS(J1_dffe14a[2], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
---B2L8 is tmdsenc:hdmitmds[1].enc|Add4~6
-B2L8 = dummydata[11] $ (dummydata[9] $ (dummydata[10]));
 
+--L1_counter_reg_bit[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[0]
+--register power-up is low
 
---B2L68 is tmdsenc:hdmitmds[1].enc|qreg~9
-B2L68 = B2L8 $ (((B2L30 & (!B2L46)) # (!B2L30 & ((B2L6)))));
+L1_counter_reg_bit[0] = DFFEAS(L1L8, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B3_qreg[3] is tmdsenc:hdmitmds[2].enc|qreg[3]
+--J1_dffe16a[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[0]
 --register power-up is low
 
-B3_qreg[3] = DFFEAS(B3L68, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
-
+J1_dffe16a[0] = DFFEAS(J1_dffe14a[0], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
---B3L8 is tmdsenc:hdmitmds[2].enc|Add4~6
-B3L8 = dummydata[19] $ (dummydata[17] $ (!dummydata[18]));
 
+--L1_counter_reg_bit[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[2]
+--register power-up is low
 
---B3L66 is tmdsenc:hdmitmds[2].enc|qreg~9
-B3L66 = B3L8 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
+L1_counter_reg_bit[2] = DFFEAS(L1L9, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---N2_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]
+--J1_dffe16a[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|dffe16a[1]
 --register power-up is low
 
-N2_shift_reg[6] = DFFEAS(J1_dffe22, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
+J1_dffe16a[1] = DFFEAS(J1_dffe14a[1], J1_fast_clock,  ,  , J1_sync_dffe12a,  ,  ,  ,  );
 
 
---N1L14 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~5
-N1L14 = (J1_dffe22) # (N2_shift_reg[6]);
+--L1_counter_reg_bit[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit[1]
+--register power-up is low
 
+L1_counter_reg_bit[1] = DFFEAS(L1L10, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---N1L15 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~6
-N1L15 = (J1_dffe22) # (N1_shift_reg[6]);
 
+--N2_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[3]
+--register power-up is low
 
---B1L72 is tmdsenc:hdmitmds[0].enc|qreg~10
-B1L72 = (B1_denreg & ((B1L32 & ((B1L49))) # (!B1L32 & (!B1L7))));
+N2_shift_reg[3] = DFFEAS(N2L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B2L69 is tmdsenc:hdmitmds[1].enc|qreg~10
-B2L69 = (B1_denreg & ((B2L30 & ((B2L46))) # (!B2L30 & (!B2L6))));
+--N2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~2
+N2L10 = (N2_shift_reg[3] & !J1_dffe22);
 
 
---B2L70 is tmdsenc:hdmitmds[1].enc|qreg~11
-B2L70 = B2L7 $ (((B2L30 & (!B2L46)) # (!B2L30 & ((B2L6)))));
+--N1_shift_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[3]
+--register power-up is low
 
+N1_shift_reg[3] = DFFEAS(N1L12, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B3L67 is tmdsenc:hdmitmds[2].enc|qreg~10
-B3L67 = B3L5 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
 
+--N1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~2
+N1L11 = (J1_dffe22) # (N1_shift_reg[3]);
 
---B3L68 is tmdsenc:hdmitmds[2].enc|qreg~11
-B3L68 = (B3L4 $ (((B3L28) # (B3L9)))) # (!B1_denreg);
 
+--F1L109 is sdram:sdram|dram_q[0]~0
+F1L109 = (rst_n & (F1_state.st_p0_rd & F1L4));
 
---B1L8 is tmdsenc:hdmitmds[0].enc|Add4~6
-B1L8 = dummydata[3] $ (dummydata[1] $ (dummydata[2]));
 
+--B3L17 is tmdsenc:hdmitmds[2].enc|Add8~6
+B3L17 = (B3L16 & (!B3L14 & !B3L27));
 
---B1L73 is tmdsenc:hdmitmds[0].enc|qreg~11
-B1L73 = B1L8 $ (((B1L32 & (!B1L49)) # (!B1L32 & ((B1L7)))));
 
+--B3L18 is tmdsenc:hdmitmds[2].enc|Add8~7
+B3L18 = ((B3L17 & ((B3L15) # (B3L44)))) # (!B3L24);
 
---F1L46 is sdram:sdram|Selector40~3
-F1L46 = (abc_a[10] & ((F1_state.st_p0_rd) # ((F1_state.st_p0_wr) # (F1L45))));
 
+--B3L19 is tmdsenc:hdmitmds[2].enc|Add8~8
+B3L19 = (B3L15 & (!B3L16)) # (!B3L15 & ((dummydata[17])));
 
---F1L44 is sdram:sdram|Selector39~2
-F1L44 = (abc_a[11] & ((F1_state.st_p0_rd) # ((F1_state.st_p0_wr) # (F1L45))));
 
+--B3L20 is tmdsenc:hdmitmds[2].enc|Add8~9
+B3L20 = B3L14 $ (((B3L28 & (B3L44)) # (!B3L28 & ((!B3L25)))));
 
---F1L36 is sdram:sdram|Selector29~7
-F1L36 = (F1_op_cycle[0] & (!F1_op_cycle[3] & (F1L60 & F1L35)));
 
+--B3L21 is tmdsenc:hdmitmds[2].enc|Add8~10
+B3L21 = (B3L28) # ((!B3L15 & (B3L14 $ (B3_disparity[3]))));
 
---F1L32 is sdram:sdram|Selector25~2
-F1L32 = (F1_state.st_p0_rd & (((abc_a[5])))) # (!F1_state.st_p0_rd & ((F1_state.st_p0_wr & ((abc_a[5]))) # (!F1_state.st_p0_wr & (F1L36))));
 
+--B3L22 is tmdsenc:hdmitmds[2].enc|Add8~11
+B3L22 = B3L16 $ (((B3L44 & ((!B3L21))) # (!B3L44 & ((B3L15) # (B3L21)))));
 
---F1L31 is sdram:sdram|Selector24~2
-F1L31 = (F1_state.st_p0_rd & (((abc_a[6])))) # (!F1_state.st_p0_rd & ((F1_state.st_p0_wr & ((abc_a[6]))) # (!F1_state.st_p0_wr & (F1L36))));
 
+--B3L23 is tmdsenc:hdmitmds[2].enc|Add8~12
+B3L23 = (B3L15 & ((B3L14) # ((!dummydata[17] & !B3L16)))) # (!B3L15 & (dummydata[17] & ((!B3L16) # (!B3L14))));
 
---F1L14 is sdram:sdram|Selector14~5
-F1L14 = (F1_state.st_idle & (((!F1L11)))) # (!F1_state.st_idle & ((F1_state.st_reset) # ((F1_init_ctr[15]))));
 
+--B1L60 is tmdsenc:hdmitmds[0].enc|qreg~2
+B1L60 = B1L6 $ (((!B1L28 & (B1L45 $ (!B1L7)))));
 
---F1L16 is sdram:sdram|Selector15~3
-F1L16 = (F1_state.st_idle & (!F1L11)) # (!F1_state.st_idle & (((!F1L12 & !F1L15))));
 
+--B1L61 is tmdsenc:hdmitmds[0].enc|qreg~3
+B1L61 = (dummydata[8] $ (B1L60)) # (!B1_denreg);
 
---F1L248 is sdram:sdram|state~33
-F1L248 = (F1L237 & ((F1_state.st_reset) # ((F1_init_ctr[15]) # (F1_state.st_idle))));
 
+--B2_qreg[8] is tmdsenc:hdmitmds[1].enc|qreg[8]
+--register power-up is low
 
---B1L9 is tmdsenc:hdmitmds[0].enc|Add4~7
-B1L9 = B1L14 $ (B1_disparity[3] $ (B1L49));
+B2_qreg[8] = DFFEAS(B2L63, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
 
---B2L9 is tmdsenc:hdmitmds[1].enc|Add4~7
-B2L9 = B2L14 $ (B2_disparity[3] $ (B2L46));
+--J1_tx_reg[2] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]
+--register power-up is low
 
+J1_tx_reg[2] = DFFEAS(J1L70, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---B1L27 is tmdsenc:hdmitmds[0].enc|Add8~14
-B1L27 = (B1L32 & (((B1L49)))) # (!B1L32 & (B1L14 $ ((B1_disparity[3]))));
 
+--Q2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg[4]
+--register power-up is low
 
---B1L28 is tmdsenc:hdmitmds[0].enc|Add8~15
-B1L28 = (B1L32 & (((!B1L49)))) # (!B1L32 & (B1L14 $ ((B1_disparity[3]))));
+Q2_shift_reg[4] = DFFEAS(Q2L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---B2L27 is tmdsenc:hdmitmds[1].enc|Add8~14
-B2L27 = (B2L22 & (((B2L16)))) # (!B2L22 & ((B2L14 & ((B2L16) # (!B2_disparity[3]))) # (!B2L14 & (B2_disparity[3]))));
+--Q2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~3
+Q2L10 = (J1_dffe11 & (J1_tx_reg[2])) # (!J1_dffe11 & ((Q2_shift_reg[4])));
 
 
---B2L28 is tmdsenc:hdmitmds[1].enc|Add8~15
-B2L28 = (B2L30 & (((!B2L46)))) # (!B2L30 & (B2L14 $ ((B2_disparity[3]))));
+--L2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|cout_actual~0
+L2L11 = (J1_sync_dffe12a & (L2_counter_reg_bit[2] & (!L2_counter_reg_bit[0] & !L2_counter_reg_bit[1])));
 
 
---B3L9 is tmdsenc:hdmitmds[2].enc|Add4~7
-B3L9 = B3L14 $ (B3_disparity[3] $ (B3L44));
+--L2L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~0
+L2L8 = (L2_wire_counter_comb_bita_0combout[0] & (!L2L24 & !L2L11));
 
 
---A1L205 is led_ctr[0]~84
-A1L205 = !led_ctr[0];
+--L2L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~1
+L2L9 = (L2L24 & (((!J1_sync_dffe12a)))) # (!L2L24 & (L2_wire_counter_comb_bita_2combout[0] & (!L2L11)));
 
 
---A1L292 is rst_ctr[0]~0
-A1L292 = !rst_ctr[0];
+--L2L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr2|counter_reg_bit~2
+L2L10 = (L2_wire_counter_comb_bita_1combout[0] & (!L2L24 & !L2L11));
 
 
---A1L109 is abc_xmemrd_q~0
-A1L109 = !abc_xmemfl_n;
+--B1L26 is tmdsenc:hdmitmds[0].enc|Add12~0
+B1L26 = (dummydata[1]) # ((B1L15) # ((B1L16 & B1L14)));
 
 
---F1L145 is sdram:sdram|init_ctr[10]~15
-F1L145 = !F1_init_ctr[10];
+--B1L17 is tmdsenc:hdmitmds[0].enc|Add8~4
+B1L17 = (B1L28 & ((B1L14 $ (B1L45)))) # (!B1L28 & (B1L24));
 
 
---J1L79 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]~0
-J1L79 = !B3_qreg[7];
+--B1L18 is tmdsenc:hdmitmds[0].enc|Add8~5
+B1L18 = (B1L7 & ((B1L15) # ((B1L16) # (!dummydata[1]))));
 
 
---J1L93 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]~1
-J1L93 = !B1_qreg[3];
+--B1L19 is tmdsenc:hdmitmds[0].enc|Add8~6
+B1L19 = (!B1L28 & (!B1L18 & ((!B1L26) # (!B1L16))));
 
 
---J1L95 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]~2
-J1L95 = !B2_qreg[3];
+--B1L20 is tmdsenc:hdmitmds[0].enc|Add8~7
+B1L20 = B1L14 $ (((B1L19) # ((B1L28 & B1L45))));
 
 
---J1L75 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]~3
-J1L75 = !B1_qreg[7];
+--B1L21 is tmdsenc:hdmitmds[0].enc|Add8~8
+B1L21 = (B1L28) # ((!B1L15 & (B1L14 $ (B1_disparity[3]))));
 
 
---J1L62 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a~0
-J1L62 = !J1_sync_dffe12a;
+--B1L22 is tmdsenc:hdmitmds[0].enc|Add8~9
+B1L22 = B1L16 $ (((B1L45 & ((!B1L21))) # (!B1L45 & ((B1L15) # (B1L21)))));
 
 
---J1L77 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]~4
-J1L77 = !B2_qreg[7];
+--B1L23 is tmdsenc:hdmitmds[0].enc|Add8~10
+B1L23 = (B1L15 & ((B1L14) # ((dummydata[1] & !B1L16)))) # (!B1L15 & (!dummydata[1] & ((!B1L16) # (!B1L14))));
 
 
---A1L147 is dummydata[22]~0
-A1L147 = !dummydata[21];
+--B2L7 is tmdsenc:hdmitmds[1].enc|Add4~5
+B2L7 = dummydata[15] $ (dummydata[13] $ (dummydata[14] $ (!B2L4)));
 
 
---A1L142 is dummydata[19]~1
-A1L142 = !dummydata[18];
+--B2L60 is tmdsenc:hdmitmds[1].enc|qreg~2
+B2L60 = B2L7 $ (((!B2L29 & (B2L45 $ (!B2L6)))));
 
 
---A1L144 is dummydata[20]~2
-A1L144 = !dummydata[19];
+--B2L61 is tmdsenc:hdmitmds[1].enc|qreg~3
+B2L61 = (dummydata[16] $ (!B2L60)) # (!B1_denreg);
 
 
---A1L121 is dummydata[3]~3
-A1L121 = !dummydata[2];
+--B3_qreg[8] is tmdsenc:hdmitmds[2].enc|qreg[8]
+--register power-up is low
 
+B3_qreg[8] = DFFEAS(B3L62, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
---A1L126 is dummydata[7]~4
-A1L126 = !dummydata[6];
 
+--J1_tx_reg[3] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[3]
+--register power-up is low
 
---J1L88 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]~5
-J1L88 = !B3_qreg[5];
+J1_tx_reg[3] = DFFEAS(B1_qreg[8], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---A1L132 is dummydata[11]~5
-A1L132 = !dummydata[10];
+--Q1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg[4]
+--register power-up is low
 
+Q1_shift_reg[4] = DFFEAS(Q1L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---A1L130 is dummydata[10]~6
-A1L130 = !dummydata[9];
 
+--Q1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~3
+Q1L10 = (J1_dffe11 & (J1_tx_reg[3])) # (!J1_dffe11 & ((Q1_shift_reg[4])));
 
---A1L138 is dummydata[16]~7
-A1L138 = !dummydata[15];
 
+--B2L46 is tmdsenc:hdmitmds[1].enc|dx~1
+B2L46 = dummydata[13] $ (!B2L4);
 
---J1L70 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]~6
-J1L70 = !B3_qreg[9];
 
+--B2L62 is tmdsenc:hdmitmds[1].enc|qreg~4
+B2L62 = B2L46 $ (((B2L29 & (!B2L45)) # (!B2L29 & ((B2L6)))));
 
---J1L84 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]~7
-J1L84 = !B1_qreg[5];
 
+--B3_qreg[5] is tmdsenc:hdmitmds[2].enc|qreg[5]
+--register power-up is low
 
---J1L86 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]~8
-J1L86 = !B2_qreg[5];
+B3_qreg[5] = DFFEAS(B3L64, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
 
---J1L66 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]~9
-J1L66 = !B1_qreg[9];
+--J1_tx_reg[12] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]
+--register power-up is low
 
+J1_tx_reg[12] = DFFEAS(J1L84, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---J1L68 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]~10
-J1L68 = !B2_qreg[9];
 
+--Q4_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg[4]
+--register power-up is low
 
---J1L97 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]~11
-J1L97 = !B3_qreg[3];
+Q4_shift_reg[4] = DFFEAS(Q4L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---T1_remap_decoy_le3a_0 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_0
-T1_remap_decoy_le3a_0 = LCELL(GND);
+--Q4L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~3
+Q4L10 = (J1_dffe11 & (J1_tx_reg[12])) # (!J1_dffe11 & ((Q4_shift_reg[4])));
 
 
---T1_remap_decoy_le3a_1 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_1
-T1_remap_decoy_le3a_1 = LCELL(GND);
+--B2L17 is tmdsenc:hdmitmds[1].enc|Add8~2
+B2L17 = (B2L29 & (B2L14 $ (B2L45)));
 
 
---T1_remap_decoy_le3a_2 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_2
-T1_remap_decoy_le3a_2 = LCELL(GND);
+--B2L27 is tmdsenc:hdmitmds[1].enc|Add12~0
+B2L27 = (dummydata[9]) # ((B2L15) # ((B2L16 & B2L14)));
 
 
---A1L394 is ~GND
-A1L394 = GND;
+--B2L18 is tmdsenc:hdmitmds[1].enc|Add8~3
+B2L18 = (B2L16 & (B2L27 & (!B2L14 & !B2L28)));
 
 
---A1L395 is ~VCC
-A1L395 = VCC;
+--B2L19 is tmdsenc:hdmitmds[1].enc|Add8~4
+B2L19 = (B2L17) # ((B2L18) # ((B2L6 & !B2L29)));
 
 
---A1L107 is abc_xmemfl_n~_wirecell
-A1L107 = !abc_xmemfl_n;
+--B2L20 is tmdsenc:hdmitmds[1].enc|Add8~5
+B2L20 = (B2L6 & ((B2L15) # ((B2L16) # (!dummydata[9]))));
 
 
---F1L84 is sdram:sdram|dram_cmd[0]~_wirecell
-F1L84 = !F1_dram_cmd[0];
+--B2L21 is tmdsenc:hdmitmds[1].enc|Add8~6
+B2L21 = (!B2L29 & (!B2L20 & ((!B2L27) # (!B2L16))));
 
 
---F1L91 is sdram:sdram|dram_cmd[1]~_wirecell
-F1L91 = !F1L19;
+--B2L22 is tmdsenc:hdmitmds[1].enc|Add8~7
+B2L22 = B2L14 $ (((B2L21) # ((B2L29 & B2L45))));
 
 
---F1L95 is sdram:sdram|dram_cmd[2]~_wirecell
-F1L95 = !F1_dram_cmd[2];
+--B2L23 is tmdsenc:hdmitmds[1].enc|Add8~8
+B2L23 = (B2L29) # ((!B2L15 & (B2L14 $ (B2_disparity[3]))));
 
 
---F1L102 is sdram:sdram|dram_cmd[3]~_wirecell
-F1L102 = !F1_dram_cmd[3];
+--B2L24 is tmdsenc:hdmitmds[1].enc|Add8~9
+B2L24 = B2L16 $ (((B2L45 & ((!B2L23))) # (!B2L45 & ((B2L15) # (B2L23)))));
 
 
---F1_op_cycle[4]_OTERM1 is sdram:sdram|op_cycle[4]_OTERM1
-F1_op_cycle[4]_OTERM1 = (F1L184 & !F1L37);
+--B2L25 is tmdsenc:hdmitmds[1].enc|Add8~10
+B2L25 = (B2L15 & ((B2L14) # ((dummydata[9] & !B2L16)))) # (!B2L15 & (!dummydata[9] & ((!B2L16) # (!B2L14))));
 
 
---F1_op_cycle[1]_OTERM3 is sdram:sdram|op_cycle[1]_OTERM3
-F1_op_cycle[1]_OTERM3 = (F1L169 & !F1L37);
+--B3L45 is tmdsenc:hdmitmds[2].enc|dx~1
+B3L45 = dummydata[21] $ (B3L4);
+
 
+--B3L60 is tmdsenc:hdmitmds[2].enc|qreg~3
+B3L60 = B3L45 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
 
---F1_op_cycle[2]_OTERM5 is sdram:sdram|op_cycle[2]_OTERM5
-F1_op_cycle[2]_OTERM5 = (F1L174 & !F1L37);
 
+--J1_tx_reg[13] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]
+--register power-up is low
 
---F1_op_cycle[3]_OTERM7 is sdram:sdram|op_cycle[3]_OTERM7
-F1_op_cycle[3]_OTERM7 = (F1L179 & !F1L37);
+J1_tx_reg[13] = DFFEAS(J1L86, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_cmd[2]_OTERM9 is sdram:sdram|dram_cmd[2]_OTERM9
-F1_dram_cmd[2]_OTERM9 = (F1L101 & (F1L16)) # (!F1L101 & ((F1_dram_cmd[2])));
+--Q3_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg[4]
+--register power-up is low
 
+Q3_shift_reg[4] = DFFEAS(Q3L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---F1_dram_cmd[3]_OTERM11 is sdram:sdram|dram_cmd[3]_OTERM11
-F1_dram_cmd[3]_OTERM11 = (F1L101 & (F1L14)) # (!F1L101 & ((F1_dram_cmd[3])));
 
+--Q3L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~3
+Q3L10 = (J1_dffe11 & (J1_tx_reg[13])) # (!J1_dffe11 & ((Q3_shift_reg[4])));
 
---F1_dram_cmd[1]_OTERM13 is sdram:sdram|dram_cmd[1]_OTERM13
---register power-up is low
 
-F1_dram_cmd[1]_OTERM13 = DFFEAS(F1L19, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+--B3L61 is tmdsenc:hdmitmds[2].enc|qreg~4
+B3L61 = B3L6 $ (((!B3L28 & (B3L44 $ (!B3L7)))));
 
 
---F1_dram_cmd[1]_OTERM15 is sdram:sdram|dram_cmd[1]_OTERM15
+--J1_tx_reg[22] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[22]
 --register power-up is low
 
-F1_dram_cmd[1]_OTERM15 = DFFEAS(F1L100, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+J1_tx_reg[22] = DFFEAS(B2_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1_dram_cmd[1]_OTERM17 is sdram:sdram|dram_cmd[1]_OTERM17
+--Q6_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg[4]
 --register power-up is low
 
-F1_dram_cmd[1]_OTERM17 = DFFEAS(F1L18, T1_wire_pll1_clk[0], rst_n,  ,  ,  ,  ,  ,  );
+Q6_shift_reg[4] = DFFEAS(Q6L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---F1L22 is sdram:sdram|Selector17~4_RESYN18_BDD19
-F1L22 = (F1L2 & (((!F1_state.st_p0_rd)))) # (!F1L2 & ((F1_dram_cmd[0]) # ((!F1_state.st_p0_rd & !F1_state.st_p0_wr))));
+--Q6L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~3
+Q6L10 = (J1_dffe11 & (J1_tx_reg[22])) # (!J1_dffe11 & ((Q6_shift_reg[4])));
 
 
---F1L24 is sdram:sdram|Selector17~4_RESYN22_BDD23
-F1L24 = (!F1_state.st_idle & (!F1L12 & ((F1_dram_cmd[0]) # (!F1_state.st_rfsh))));
+--B1L62 is tmdsenc:hdmitmds[0].enc|qreg~4
+B1L62 = dummydata[1] $ (((B1L28 & ((B1L45))) # (!B1L28 & (!B1L7))));
 
 
---F1L26 is sdram:sdram|Selector17~4_RESYN24_BDD25
-F1L26 = ((F1_dram_cmd[0] & ((F1_op_cycle[4]) # (!F1L61)))) # (!F1L99);
-
-
---F1L5 is sdram:sdram|Equal4~0_RESYN28_BDD29
-F1L5 = (F1_op_cycle[1] & F1_op_cycle[2]);
-
-
---F1L40 is sdram:sdram|Selector37~1_RESYN32_BDD33
-F1L40 = (F1_op_cycle[1] & F1_op_cycle[2]);
-
-
---F1L235 is sdram:sdram|state.st_reset~2_RESYN34_BDD35
-F1L235 = (!F1_state.st_p0_wr & (F1_state.st_idle $ (F1_state.st_init)));
-
-
---abc_clk is abc_clk
-abc_clk = INPUT();
-
-
---abc_d_oe is abc_d_oe
-abc_d_oe = OUTPUT(A1L107);
-
-
---abc_rst_n is abc_rst_n
-abc_rst_n = INPUT();
-
-
---abc_cs_n is abc_cs_n
-abc_cs_n = INPUT();
-
-
---abc_out_n[0] is abc_out_n[0]
-abc_out_n[0] = INPUT();
-
-
---abc_out_n[1] is abc_out_n[1]
-abc_out_n[1] = INPUT();
-
-
---abc_out_n[2] is abc_out_n[2]
-abc_out_n[2] = INPUT();
-
-
---abc_out_n[3] is abc_out_n[3]
-abc_out_n[3] = INPUT();
-
-
---abc_out_n[4] is abc_out_n[4]
-abc_out_n[4] = INPUT();
-
-
---abc_inp_n[0] is abc_inp_n[0]
-abc_inp_n[0] = INPUT();
-
-
---abc_inp_n[1] is abc_inp_n[1]
-abc_inp_n[1] = INPUT();
-
-
---abc_rdy_x is abc_rdy_x
-abc_rdy_x = OUTPUT(A1L92);
-
-
---abc_resin_x is abc_resin_x
-abc_resin_x = OUTPUT(A1L94);
-
-
---abc_int80_x is abc_int80_x
-abc_int80_x = OUTPUT(A1L79);
-
-
---abc_int800_x is abc_int800_x
-abc_int800_x = OUTPUT(A1L81);
-
-
---abc_nmi_x is abc_nmi_x
-abc_nmi_x = OUTPUT(A1L84);
-
+--J1_tx_reg[23] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[23]
+--register power-up is low
 
---abc_xm_x is abc_xm_x
-abc_xm_x = OUTPUT(A1L102);
+J1_tx_reg[23] = DFFEAS(B3_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---abc_master is abc_master
-abc_master = OUTPUT(A1L394);
-
+--Q5_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg[4]
+--register power-up is low
 
---abc_a_oe is abc_a_oe
-abc_a_oe = OUTPUT(A1L394);
+Q5_shift_reg[4] = DFFEAS(Q5L11, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---abc_d_ce_n is abc_d_ce_n
-abc_d_ce_n = OUTPUT(A1L394);
+--Q5L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~3
+Q5L10 = (J1_dffe11 & (J1_tx_reg[23])) # (!J1_dffe11 & ((Q5_shift_reg[4])));
 
 
---exth_hc is exth_hc
-exth_hc = INPUT();
+--L1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|cout_actual~0
+L1L11 = (J1_sync_dffe12a & (L1_counter_reg_bit[2] & (!L1_counter_reg_bit[0] & !L1_counter_reg_bit[1])));
 
 
---exth_hh is exth_hh
-exth_hh = INPUT();
+--L1L8 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~0
+L1L8 = (L1_wire_counter_comb_bita_0combout[0] & (!L1L24 & !L1L11));
 
 
---sr_clk is sr_clk
-sr_clk = OUTPUT(DB1_dataout[0]);
+--L1L9 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~1
+L1L9 = (L1L24 & (((!J1_sync_dffe12a)))) # (!L1L24 & (L1_wire_counter_comb_bita_2combout[0] & (!L1L11)));
 
 
---sr_cke is sr_cke
-sr_cke = OUTPUT(F1_dram_cke);
+--L1L10 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_cntr:cntr13|counter_reg_bit~2
+L1L10 = (L1_wire_counter_comb_bita_1combout[0] & (!L1L24 & !L1L11));
 
 
---sr_ba[0] is sr_ba[0]
-sr_ba[0] = OUTPUT(F1_dram_ba[0]);
+--N2_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[4]
+--register power-up is low
 
+N2_shift_reg[4] = DFFEAS(N2L12, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---sr_ba[1] is sr_ba[1]
-sr_ba[1] = OUTPUT(F1_dram_ba[1]);
 
+--N2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~3
+N2L11 = (N2_shift_reg[4] & !J1_dffe22);
 
---sr_a[0] is sr_a[0]
-sr_a[0] = OUTPUT(F1_dram_a[0]);
 
+--N1_shift_reg[4] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[4]
+--register power-up is low
 
---sr_a[1] is sr_a[1]
-sr_a[1] = OUTPUT(F1_dram_a[1]);
+N1_shift_reg[4] = DFFEAS(N1L13, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---sr_a[2] is sr_a[2]
-sr_a[2] = OUTPUT(F1_dram_a[2]);
+--N1L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~3
+N1L12 = (N1_shift_reg[4] & !J1_dffe22);
 
 
---sr_a[3] is sr_a[3]
-sr_a[3] = OUTPUT(F1_dram_a[3]);
+--B2L63 is tmdsenc:hdmitmds[1].enc|qreg~5
+B2L63 = (B2L45) # (!B1_denreg);
 
 
---sr_a[4] is sr_a[4]
-sr_a[4] = OUTPUT(F1_dram_a[4]);
+--B3_qreg[9] is tmdsenc:hdmitmds[2].enc|qreg[9]
+--register power-up is low
 
+B3_qreg[9] = DFFEAS(B3L65, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
---sr_a[5] is sr_a[5]
-sr_a[5] = OUTPUT(F1_dram_a[5]);
 
+--J1_tx_reg[0] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]
+--register power-up is low
 
---sr_a[6] is sr_a[6]
-sr_a[6] = OUTPUT(F1_dram_a[6]);
+J1_tx_reg[0] = DFFEAS(J1L66, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---sr_a[7] is sr_a[7]
-sr_a[7] = OUTPUT(F1_dram_a[7]);
+--Q2L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg24|shift_reg~4
+Q2L11 = (J1_dffe11 & J1_tx_reg[0]);
 
 
---sr_a[8] is sr_a[8]
-sr_a[8] = OUTPUT(F1_dram_a[8]);
+--B3L62 is tmdsenc:hdmitmds[2].enc|qreg~5
+B3L62 = (B3L44) # (!B1_denreg);
 
 
---sr_a[9] is sr_a[9]
-sr_a[9] = OUTPUT(A1L394);
+--B1_qreg[8] is tmdsenc:hdmitmds[0].enc|qreg[8]
+--register power-up is low
 
+B1_qreg[8] = DFFEAS(B1L65, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
---sr_a[10] is sr_a[10]
-sr_a[10] = OUTPUT(F1_dram_a[10]);
 
+--J1_tx_reg[1] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]
+--register power-up is low
 
---sr_a[11] is sr_a[11]
-sr_a[11] = OUTPUT(A1L394);
+J1_tx_reg[1] = DFFEAS(J1L68, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---sr_a[12] is sr_a[12]
-sr_a[12] = OUTPUT(A1L394);
+--Q1L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg23|shift_reg~4
+Q1L11 = (J1_dffe11 & J1_tx_reg[1]);
 
 
---sr_dqm[0] is sr_dqm[0]
-sr_dqm[0] = OUTPUT(F1_dram_dqm[0]);
+--B3L63 is tmdsenc:hdmitmds[2].enc|qreg~6
+B3L63 = dummydata[21] $ (dummydata[22] $ (!B3L4));
 
 
---sr_dqm[1] is sr_dqm[1]
-sr_dqm[1] = OUTPUT(F1_dram_dqm[1]);
+--B3L64 is tmdsenc:hdmitmds[2].enc|qreg~7
+B3L64 = (B3L63 $ (((B3L28) # (B3L9)))) # (!B1_denreg);
 
 
---sr_cs_n is sr_cs_n
-sr_cs_n = OUTPUT(F1L102);
+--B1_qreg[5] is tmdsenc:hdmitmds[0].enc|qreg[5]
+--register power-up is low
 
+B1_qreg[5] = DFFEAS(B1L67, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
---sr_we_n is sr_we_n
-sr_we_n = OUTPUT(F1L84);
 
+--J1_tx_reg[10] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[10]
+--register power-up is low
 
---sr_cas_n is sr_cas_n
-sr_cas_n = OUTPUT(F1L91);
+J1_tx_reg[10] = DFFEAS(B2_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---sr_ras_n is sr_ras_n
-sr_ras_n = OUTPUT(F1L95);
+--Q4L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg26|shift_reg~4
+Q4L11 = (J1_dffe11 & J1_tx_reg[10]);
 
 
---sd_clk is sd_clk
-sd_clk = OUTPUT(A1L395);
+--B1L46 is tmdsenc:hdmitmds[0].enc|dx~1
+B1L46 = dummydata[5] $ (B1L5);
 
 
---sd_cmd is sd_cmd
-sd_cmd = OUTPUT(A1L395);
+--B1L63 is tmdsenc:hdmitmds[0].enc|qreg~5
+B1L63 = B1L46 $ (((B1L28 & (!B1L45)) # (!B1L28 & ((B1L7)))));
 
 
---tty_txd is tty_txd
-tty_txd = INPUT();
+--B2_qreg[5] is tmdsenc:hdmitmds[1].enc|qreg[5]
+--register power-up is low
 
+B2_qreg[5] = DFFEAS(B2L66, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
---tty_rxd is tty_rxd
-tty_rxd = OUTPUT(A1L395);
 
+--J1_tx_reg[11] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[11]
+--register power-up is low
 
---tty_rts is tty_rts
-tty_rts = INPUT();
+J1_tx_reg[11] = DFFEAS(B3_qreg[6], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---tty_cts is tty_cts
-tty_cts = OUTPUT(A1L395);
+--Q3L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg25|shift_reg~4
+Q3L11 = (J1_dffe11 & J1_tx_reg[11]);
 
 
---tty_dtr is tty_dtr
-tty_dtr = INPUT();
+--B1L64 is tmdsenc:hdmitmds[0].enc|qreg~6
+B1L64 = B1L4 $ (((!B1L28 & (B1L45 $ (!B1L7)))));
 
 
---flash_cs_n is flash_cs_n
-flash_cs_n = OUTPUT(A1L394);
+--J1_tx_reg[20] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]
+--register power-up is low
 
+J1_tx_reg[20] = DFFEAS(J1L97, J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---flash_clk is flash_clk
-flash_clk = OUTPUT(A1L394);
 
+--Q6L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg28|shift_reg~4
+Q6L11 = (J1_dffe11 & J1_tx_reg[20]);
 
---flash_mosi is flash_mosi
-flash_mosi = OUTPUT(A1L394);
 
+--B2L64 is tmdsenc:hdmitmds[1].enc|qreg~6
+B2L64 = B2L5 $ (((!B2L29 & (B2L45 $ (!B2L6)))));
 
---flash_miso is flash_miso
-flash_miso = INPUT();
 
+--J1_tx_reg[21] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[21]
+--register power-up is low
 
---rtc_32khz is rtc_32khz
-rtc_32khz = INPUT();
+J1_tx_reg[21] = DFFEAS(B1_qreg[2], J1_tx_coreclock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---rtc_int_n is rtc_int_n
-rtc_int_n = INPUT();
+--Q5L11 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg1:shift_reg27|shift_reg~4
+Q5L11 = (J1_dffe11 & J1_tx_reg[21]);
 
 
---led[1] is led[1]
-led[1] = OUTPUT(led_ctr[26]);
+--N1_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[6]
+--register power-up is low
 
+N1_shift_reg[6] = DFFEAS(N1L14, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
---led[2] is led[2]
-led[2] = OUTPUT(led_ctr[27]);
 
+--N2L12 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg~4
+N2L12 = (N1_shift_reg[6] & !J1_dffe22);
 
---led[3] is led[3]
-led[3] = OUTPUT(led_ctr[28]);
 
+--N1_shift_reg[5] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg[5]
+--register power-up is low
 
---hdmi_d[0] is hdmi_d[0]
-hdmi_d[0] = OUTPUT(M1_wire_ddio_outa_dataout[0]);
+N1_shift_reg[5] = DFFEAS(N1L15, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---hdmi_d[1] is hdmi_d[1]
-hdmi_d[1] = OUTPUT(M1_wire_ddio_outa_dataout[1]);
+--N1L13 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~4
+N1L13 = (N1_shift_reg[5] & !J1_dffe22);
 
 
---hdmi_d[2] is hdmi_d[2]
-hdmi_d[2] = OUTPUT(M1_wire_ddio_outa_dataout[2]);
+--B3L65 is tmdsenc:hdmitmds[2].enc|qreg~8
+B3L65 = (B1_denreg & ((B3L28 & ((B3L44))) # (!B3L28 & (!B3L7))));
 
 
---hdmi_clk is hdmi_clk
-hdmi_clk = OUTPUT(P1_wire_ddio_outa_dataout[0]);
+--B1_qreg[9] is tmdsenc:hdmitmds[0].enc|qreg[9]
+--register power-up is low
 
+B1_qreg[9] = DFFEAS(B1L68, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
---hdmi_sda is hdmi_sda
-hdmi_sda = BIDIR(A1L194);
 
+--B1L65 is tmdsenc:hdmitmds[0].enc|qreg~7
+B1L65 = (B1L45) # (!B1_denreg);
 
---abc_d[0] is abc_d[0]
-abc_d[0] = BIDIR(A1L48);
 
+--B2_qreg[9] is tmdsenc:hdmitmds[1].enc|qreg[9]
+--register power-up is low
 
---abc_d[1] is abc_d[1]
-abc_d[1] = BIDIR(A1L50);
+B2_qreg[9] = DFFEAS(B2L68, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
 
---abc_d[2] is abc_d[2]
-abc_d[2] = BIDIR(A1L52);
+--B1L66 is tmdsenc:hdmitmds[0].enc|qreg~8
+B1L66 = dummydata[5] $ (dummydata[6] $ (B1L5));
 
 
---abc_d[3] is abc_d[3]
-abc_d[3] = BIDIR(A1L54);
+--B1L67 is tmdsenc:hdmitmds[0].enc|qreg~9
+B1L67 = (B1L66 $ (((B1L28) # (B1L9)))) # (!B1_denreg);
 
 
---abc_d[4] is abc_d[4]
-abc_d[4] = BIDIR(A1L56);
+--B2L65 is tmdsenc:hdmitmds[1].enc|qreg~7
+B2L65 = dummydata[13] $ (dummydata[14] $ (B2L4));
 
 
---abc_d[5] is abc_d[5]
-abc_d[5] = BIDIR(A1L58);
+--B2L66 is tmdsenc:hdmitmds[1].enc|qreg~8
+B2L66 = (B2L65 $ (((B2L29) # (B2L9)))) # (!B1_denreg);
 
 
---abc_d[6] is abc_d[6]
-abc_d[6] = BIDIR(A1L60);
+--B2L8 is tmdsenc:hdmitmds[1].enc|Add4~6
+B2L8 = dummydata[11] $ (dummydata[9] $ (dummydata[10]));
 
 
---abc_d[7] is abc_d[7]
-abc_d[7] = BIDIR(A1L62);
+--B2L67 is tmdsenc:hdmitmds[1].enc|qreg~9
+B2L67 = B2L8 $ (((B2L29 & (!B2L45)) # (!B2L29 & ((B2L6)))));
 
 
---exth_ha is exth_ha
-exth_ha = BIDIR(A1L154);
+--B3_qreg[3] is tmdsenc:hdmitmds[2].enc|qreg[3]
+--register power-up is low
 
+B3_qreg[3] = DFFEAS(B3L68, T1_wire_pll1_clk[2], vid_rst_n,  ,  ,  ,  ,  ,  );
 
---exth_hb is exth_hb
-exth_hb = BIDIR(A1L156);
 
+--B3L8 is tmdsenc:hdmitmds[2].enc|Add4~6
+B3L8 = dummydata[19] $ (dummydata[17] $ (!dummydata[18]));
 
---exth_hd is exth_hd
-exth_hd = BIDIR(A1L159);
 
+--B3L66 is tmdsenc:hdmitmds[2].enc|qreg~9
+B3L66 = B3L8 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
 
---exth_he is exth_he
-exth_he = BIDIR(A1L161);
 
+--N2_shift_reg[6] is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_l|shift_reg[6]
+--register power-up is low
 
---exth_hf is exth_hf
-exth_hf = BIDIR(A1L163);
+N2_shift_reg[6] = DFFEAS(J1_dffe22, J1_fast_clock, T1_wire_pll1_locked,  ,  ,  ,  ,  ,  );
 
 
---exth_hg is exth_hg
-exth_hg = BIDIR(A1L165);
+--N1L14 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~5
+N1L14 = (J1_dffe22) # (N2_shift_reg[6]);
 
 
---sr_dq[0] is sr_dq[0]
-sr_dq[0] = BIDIR(A1L352);
+--N1L15 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|hdmitx_shift_reg:outclk_shift_h|shift_reg~6
+N1L15 = (J1_dffe22) # (N1_shift_reg[6]);
 
 
---sr_dq[1] is sr_dq[1]
-sr_dq[1] = BIDIR(A1L354);
+--B1L68 is tmdsenc:hdmitmds[0].enc|qreg~10
+B1L68 = (B1_denreg & ((B1L28 & ((B1L45))) # (!B1L28 & (!B1L7))));
 
 
---sr_dq[2] is sr_dq[2]
-sr_dq[2] = BIDIR(A1L356);
+--B2L68 is tmdsenc:hdmitmds[1].enc|qreg~10
+B2L68 = (B1_denreg & ((B2L29 & ((B2L45))) # (!B2L29 & (!B2L6))));
 
 
---sr_dq[3] is sr_dq[3]
-sr_dq[3] = BIDIR(A1L358);
+--B2L69 is tmdsenc:hdmitmds[1].enc|qreg~11
+B2L69 = B2L7 $ (((B2L29 & (!B2L45)) # (!B2L29 & ((B2L6)))));
 
 
---sr_dq[4] is sr_dq[4]
-sr_dq[4] = BIDIR(A1L360);
+--B3L67 is tmdsenc:hdmitmds[2].enc|qreg~10
+B3L67 = B3L5 $ (((B3L28 & (!B3L44)) # (!B3L28 & ((B3L7)))));
 
 
---sr_dq[5] is sr_dq[5]
-sr_dq[5] = BIDIR(A1L362);
+--B3L68 is tmdsenc:hdmitmds[2].enc|qreg~11
+B3L68 = (B3L4 $ (((B3L28) # (B3L9)))) # (!B1_denreg);
 
 
---sr_dq[6] is sr_dq[6]
-sr_dq[6] = BIDIR(A1L364);
+--B1L8 is tmdsenc:hdmitmds[0].enc|Add4~6
+B1L8 = dummydata[3] $ (dummydata[1] $ (dummydata[2]));
 
 
---sr_dq[7] is sr_dq[7]
-sr_dq[7] = BIDIR(A1L366);
+--B1L69 is tmdsenc:hdmitmds[0].enc|qreg~11
+B1L69 = B1L8 $ (((B1L28 & (!B1L45)) # (!B1L28 & ((B1L7)))));
 
 
---sr_dq[8] is sr_dq[8]
-sr_dq[8] = BIDIR(A1L368);
+--F1L41 is sdram:sdram|Selector42~3
+F1L41 = (abc_a[10] & ((F1_state.st_p0_rd) # ((F1_state.st_p0_wr) # (F1L40))));
 
 
---sr_dq[9] is sr_dq[9]
-sr_dq[9] = BIDIR(A1L370);
+--F1L39 is sdram:sdram|Selector41~2
+F1L39 = (abc_a[11] & ((F1_state.st_p0_rd) # ((F1_state.st_p0_wr) # (F1L40))));
 
 
---sr_dq[10] is sr_dq[10]
-sr_dq[10] = BIDIR(A1L372);
+--F1L31 is sdram:sdram|Selector28~2
+F1L31 = (F1_state.st_p0_rd & (((abc_a[5])))) # (!F1_state.st_p0_rd & ((F1_state.st_p0_wr & ((abc_a[5]))) # (!F1_state.st_p0_wr & (F1L34))));
 
 
---sr_dq[11] is sr_dq[11]
-sr_dq[11] = BIDIR(A1L374);
+--F1L30 is sdram:sdram|Selector27~2
+F1L30 = (F1_state.st_p0_rd & (((abc_a[6])))) # (!F1_state.st_p0_rd & ((F1_state.st_p0_wr & ((abc_a[6]))) # (!F1_state.st_p0_wr & (F1L34))));
 
 
---sr_dq[12] is sr_dq[12]
-sr_dq[12] = BIDIR(A1L376);
+--F1L15 is sdram:sdram|Selector16~5
+F1L15 = (F1_state.st_idle & (((!F1L12)))) # (!F1_state.st_idle & ((F1_state.st_reset) # ((F1_init_ctr[15]))));
 
 
---sr_dq[13] is sr_dq[13]
-sr_dq[13] = BIDIR(A1L378);
+--F1L17 is sdram:sdram|Selector17~3
+F1L17 = (F1_state.st_idle & (!F1L12)) # (!F1_state.st_idle & (((!F1L13 & !F1L16))));
 
 
---sr_dq[14] is sr_dq[14]
-sr_dq[14] = BIDIR(A1L380);
+--F1L222 is sdram:sdram|state~33
+F1L222 = (F1L210 & ((F1_state.st_reset) # ((F1_init_ctr[15]) # (F1_state.st_idle))));
 
 
---sr_dq[15] is sr_dq[15]
-sr_dq[15] = BIDIR(A1L382);
+--B1L9 is tmdsenc:hdmitmds[0].enc|Add4~7
+B1L9 = B1L14 $ (B1_disparity[3] $ (B1L45));
 
 
---sd_dat[0] is sd_dat[0]
-sd_dat[0] = BIDIR(A1L312);
+--B2L9 is tmdsenc:hdmitmds[1].enc|Add4~7
+B2L9 = B2L14 $ (B2_disparity[3] $ (B2L45));
 
 
---sd_dat[1] is sd_dat[1]
-sd_dat[1] = BIDIR(A1L314);
+--B3L24 is tmdsenc:hdmitmds[2].enc|Add8~13
+B3L24 = B3L14 $ (((B3L28 & ((!B3L44))) # (!B3L28 & (!B3_disparity[3]))));
 
 
---sd_dat[2] is sd_dat[2]
-sd_dat[2] = BIDIR(A1L316);
+--B3L25 is tmdsenc:hdmitmds[2].enc|Add8~14
+B3L25 = (B3L19 & ((B3L14 & ((B3L16) # (!B3_disparity[3]))) # (!B3L14 & (B3_disparity[3])))) # (!B3L19 & (((B3L16))));
 
 
---sd_dat[3] is sd_dat[3]
-sd_dat[3] = BIDIR(A1L318);
+--B3L26 is tmdsenc:hdmitmds[2].enc|Add8~15
+B3L26 = (B3L28 & (((!B3L44)))) # (!B3L28 & (B3L14 $ ((B3_disparity[3]))));
 
 
---spi_clk is spi_clk
-spi_clk = BIDIR(A1L320);
+--B1L24 is tmdsenc:hdmitmds[0].enc|Add8~11
+B1L24 = (B1L14 & (!B1_disparity[3])) # (!B1L14 & ((B1_disparity[3]) # ((B1L16 & B1L26))));
 
 
---spi_miso is spi_miso
-spi_miso = BIDIR(A1L326);
+--B1L25 is tmdsenc:hdmitmds[0].enc|Add8~12
+B1L25 = (B1L28 & (((!B1L45)))) # (!B1L28 & (B1L14 $ ((B1_disparity[3]))));
 
 
---spi_mosi is spi_mosi
-spi_mosi = BIDIR(A1L328);
+--B2L26 is tmdsenc:hdmitmds[1].enc|Add8~11
+B2L26 = (B2L29 & (((!B2L45)))) # (!B2L29 & (B2L14 $ ((B2_disparity[3]))));
 
 
---spi_cs_esp_n is spi_cs_esp_n
-spi_cs_esp_n = BIDIR(A1L322);
+--B3L9 is tmdsenc:hdmitmds[2].enc|Add4~7
+B3L9 = B3L14 $ (B3_disparity[3] $ (B3L44));
 
 
---spi_cs_flash_n is spi_cs_flash_n
-spi_cs_flash_n = BIDIR(A1L324);
+--A1L205 is led_ctr[0]~84
+A1L205 = !led_ctr[0];
 
 
---esp_io0 is esp_io0
-esp_io0 = BIDIR(A1L152);
+--A1L292 is rst_ctr[0]~0
+A1L292 = !rst_ctr[0];
 
 
---esp_int is esp_int
-esp_int = BIDIR(A1L150);
+--A1L109 is abc_xmemrd_q~0
+A1L109 = !abc_xmemfl_n;
 
 
---i2c_scl is i2c_scl
-i2c_scl = BIDIR(A1L196);
+--F1L128 is sdram:sdram|init_ctr[10]~15
+F1L128 = !F1_init_ctr[10];
 
 
---i2c_sda is i2c_sda
-i2c_sda = BIDIR(A1L198);
+--J1L79 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[8]~0
+J1L79 = !B3_qreg[7];
 
 
---gpio[0] is gpio[0]
-gpio[0] = BIDIR(A1L173);
+--J1L93 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[18]~1
+J1L93 = !B1_qreg[3];
 
 
---gpio[1] is gpio[1]
-gpio[1] = BIDIR(A1L175);
+--J1L95 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[19]~2
+J1L95 = !B2_qreg[3];
 
 
---gpio[2] is gpio[2]
-gpio[2] = BIDIR(A1L177);
+--J1L75 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[6]~3
+J1L75 = !B1_qreg[7];
 
 
---gpio[3] is gpio[3]
-gpio[3] = BIDIR(A1L179);
+--J1L62 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|sync_dffe12a~0
+J1L62 = !J1_sync_dffe12a;
 
 
---gpio[4] is gpio[4]
-gpio[4] = BIDIR(A1L181);
+--J1L77 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[7]~4
+J1L77 = !B2_qreg[7];
 
 
---gpio[5] is gpio[5]
-gpio[5] = BIDIR(A1L183);
+--A1L147 is dummydata[22]~0
+A1L147 = !dummydata[21];
 
 
---hdmi_scl is hdmi_scl
-hdmi_scl = BIDIR(A1L192);
+--A1L142 is dummydata[19]~1
+A1L142 = !dummydata[18];
 
 
---hdmi_hpd is hdmi_hpd
-hdmi_hpd = BIDIR(A1L190);
+--A1L144 is dummydata[20]~2
+A1L144 = !dummydata[19];
 
 
---abc_xmemfl_n is abc_xmemfl_n
-abc_xmemfl_n = INPUT();
+--A1L121 is dummydata[3]~3
+A1L121 = !dummydata[2];
 
 
---abc_a[10] is abc_a[10]
-abc_a[10] = INPUT();
+--A1L126 is dummydata[7]~4
+A1L126 = !dummydata[6];
 
 
---abc_a[11] is abc_a[11]
-abc_a[11] = INPUT();
+--J1L88 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[14]~5
+J1L88 = !B3_qreg[5];
 
 
---abc_a[12] is abc_a[12]
-abc_a[12] = INPUT();
+--A1L132 is dummydata[11]~5
+A1L132 = !dummydata[10];
 
 
---abc_a[1] is abc_a[1]
-abc_a[1] = INPUT();
+--A1L130 is dummydata[10]~6
+A1L130 = !dummydata[9];
 
 
---abc_a[13] is abc_a[13]
-abc_a[13] = INPUT();
+--A1L138 is dummydata[16]~7
+A1L138 = !dummydata[15];
 
 
---abc_a[2] is abc_a[2]
-abc_a[2] = INPUT();
+--J1L70 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[2]~6
+J1L70 = !B3_qreg[9];
 
 
---abc_a[14] is abc_a[14]
-abc_a[14] = INPUT();
+--J1L84 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[12]~7
+J1L84 = !B1_qreg[5];
 
 
---abc_a[3] is abc_a[3]
-abc_a[3] = INPUT();
+--J1L86 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[13]~8
+J1L86 = !B2_qreg[5];
 
 
---abc_a[15] is abc_a[15]
-abc_a[15] = INPUT();
+--J1L66 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[0]~9
+J1L66 = !B1_qreg[9];
 
 
---abc_a[4] is abc_a[4]
-abc_a[4] = INPUT();
+--J1L68 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[1]~10
+J1L68 = !B2_qreg[9];
 
 
---abc_a[5] is abc_a[5]
-abc_a[5] = INPUT();
+--J1L97 is hdmitx:hdmitx|altlvds_tx:ALTLVDS_TX_component|hdmitx_lvds_tx:auto_generated|tx_reg[20]~11
+J1L97 = !B3_qreg[3];
 
 
---abc_a[6] is abc_a[6]
-abc_a[6] = INPUT();
+--T1_remap_decoy_le3a_0 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_0
+T1_remap_decoy_le3a_0 = LCELL(GND);
 
 
---abc_a[7] is abc_a[7]
-abc_a[7] = INPUT();
+--T1_remap_decoy_le3a_1 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_1
+T1_remap_decoy_le3a_1 = LCELL(GND);
 
 
---abc_a[8] is abc_a[8]
-abc_a[8] = INPUT();
+--T1_remap_decoy_le3a_2 is pll:pll|altpll:altpll_component|pll_altpll:auto_generated|remap_decoy_le3a_2
+T1_remap_decoy_le3a_2 = LCELL(GND);
 
 
---abc_a[9] is abc_a[9]
-abc_a[9] = INPUT();
+--A1L394 is ~GND
+A1L394 = GND;
 
 
---abc_a[0] is abc_a[0]
-abc_a[0] = INPUT();
+--A1L395 is ~VCC
+A1L395 = VCC;
 
 
---clock_48 is clock_48
-clock_48 = INPUT();
+--A1L107 is abc_xmemfl_n~_wirecell
+A1L107 = !abc_xmemfl_n;
 
 
---abc_xmemw800_n is abc_xmemw800_n
-abc_xmemw800_n = INPUT();
+--F1L75 is sdram:sdram|dram_cmd[0]~_wirecell
+F1L75 = !F1_dram_cmd[0];
 
 
---abc_xmemw80_n is abc_xmemw80_n
-abc_xmemw80_n = INPUT();
+--F1L77 is sdram:sdram|dram_cmd[1]~_wirecell
+F1L77 = !F1_dram_cmd[1];
 
 
---abc_xinpstb_n is abc_xinpstb_n
-abc_xinpstb_n = INPUT();
+--F1L79 is sdram:sdram|dram_cmd[2]~_wirecell
+F1L79 = !F1_dram_cmd[2];
 
 
---abc_xoutpstb_n is abc_xoutpstb_n
-abc_xoutpstb_n = INPUT();
+--F1L84 is sdram:sdram|dram_cmd[3]~_wirecell
+F1L84 = !F1_dram_cmd[3];
 
 

sdram.sv

@@ -23,48 +23,18 @@
 //
 //  All signals are in the sdram clock domain.
 //
+//  The ack signals are arrays that give (some) advance notification:
+//  e.g. rack0[1] is asserted exactly one cycle before rack0[0].
+//
+//  rack*[0] is asserted during the first cycle rd* is valid.
+//  wack*[0] is asserted during the cycle after wd* was sampled.
+//
+//  Thus, especially for bursts on port 1, generally rack1[0] and
+//  wack1[1] are the relevant signals.
+//
 
-module sdram (
-	      // Reset and clock
-	      input	    rst_n,
-	      input	    clk,
-
-	      // SDRAM hardware interface
-	      output	    sr_clk, // SDRAM clock output buffer
-	      output	    sr_cke, // SDRAM clock enable
-	      output	    sr_cs_n, // SDRAM CS#
-	      output	    sr_ras_n, // SDRAM RAS#
-	      output	    sr_cas_n, // SDRAM CAS#
-	      output	    sr_we_n, // SDRAM WE#
-	      output [1:0]  sr_dqm, // SDRAM DQM (per byte)
-	      output [1:0]  sr_ba, // SDRAM bank selects
-	      output [12:0] sr_a, // SDRAM address bus
-	      inout [15:0]  sr_dq, // SDRAM data bus
-
-	      // Port 0: single byte, high priority
-	      input [24:0]  a0, // Address, must be stable until ack
-
-	      output [7:0]  rd0, // Data from SDRAM
-	      input	    rrq0, // Read request
-	      output	    rack0, // Read ack
-
-	      input [7:0]   wd0, // Data to SDRAM
-	      input	    wrq0, // Write request
-	      output	    wack0, // Write ack
-
-	      // Port 1
-	      input [24:1]  a1,
-
-	      output [15:0] rd1,
-	      input	    rrq1,
-	      output	    rack1,
-
-	      input [15:0]  wd1,
-	      input [1:0]   wbe1, // Write byte enable
-	      input	    wrq1,
-	      output	    wack1
-	      );
-
+module sdram
+#( parameter
    //  Timing parameters
    //  The parameters are hardcoded for Micron MT48LC16M16A2-6A,
    //  per datasheet:
@@ -80,26 +50,68 @@ module sdram (
    //    tMRD                   2	 2    MODE REGISTER to ACTIVE/REFRESH
    //
    //    These parameters are set by power of 2:
-   //    tREF  64/8192 ms     781     1302    Refresh time per row (max)
+   //    tREFi 64/8192 ms     781     1302    Refresh time per row (max)
    //    tP        100 us   10000    16667    Time until first command (min)
 
-   parameter t_cl	=  3;
-   parameter t_rcd	=  3;
-   parameter t_rfc	= 10;
-   parameter t_rp	=  3;
-   parameter t_ras	=  7;
-   parameter t_rc	= 10;
-   parameter t_wr	=  2;
-   parameter t_mrd	=  2;
-   parameter t_ref	=  9;	// 512 cycles (extra conservative)
-   parameter t_p	= 15;	// 32768 cycles
+   t_cl		=  3,
+   t_rcd	=  3,
+   t_rfc	= 10,
+   t_rp		=  3,
+   t_ras	=  7,
+   t_rc		= 10,
+   t_wr		=  2,
+   t_mrd	=  2,
+
+   t_refi_lg2	=  9,	// 512 cycles (extra conservative)
+   t_p_lg2	= 15,	// 32768 cycles
+
+   burst_lg2	=  3	// Burst length on port 1
+)
+(
+	      // Reset and clock
+	      input		      rst_n,
+	      input		      clk,
+
+	      // SDRAM hardware interface
+	      output		      sr_clk, // SDRAM clock output buffer
+	      output		      sr_cke, // SDRAM clock enable
+	      output		      sr_cs_n, // SDRAM CS#
+	      output		      sr_ras_n, // SDRAM RAS#
+	      output		      sr_cas_n, // SDRAM CAS#
+	      output		      sr_we_n, // SDRAM WE#
+	      output [1:0]	      sr_dqm, // SDRAM DQM (per byte)
+	      output [1:0]	      sr_ba, // SDRAM bank selects
+	      output [12:0]	      sr_a, // SDRAM address bus
+	      inout [15:0]	      sr_dq, // SDRAM data bus
+
+	      // Port 0: single byte, high priority
+	      input [24:0]	      a0, // Address, must be stable until ack
+
+	      output [7:0]	      rd0, // Data from SDRAM
+	      input		      rrq0, // Read request
+	      output [t_rcd+t_cl+1:0] rack0, // Read ack
 
-   parameter burst      =  3;	// 8-cycle bursts
+	      input [7:0]	      wd0, // Data to SDRAM
+	      input		      wrq0, // Write request
+	      output [t_rcd:0]	      wack0, // Write ack
+
+	      // Port 1
+	      input [24:1]	      a1,
+
+	      output [15:0]	      rd1,
+	      input		      rrq1,
+	      output [t_rcd+t_cl+1:0] rack1,
+
+	      input [15:0]	      wd1,
+	      input [1:0]	      wbe1, // Write byte enable
+	      input		      wrq1,
+	      output [t_rcd:0]	      wack1
+	      );
 
    // Mode register data
    wire			    mrd_wburst = 1'b1;     // Write bursts enabled
    wire [2:0]		    mrd_cl     = t_cl;
-   wire [2:0]		    mrd_burst  = burst;
+   wire [2:0]		    mrd_burst  = burst_lg2;
    wire			    mrd_interleave = 1'b0; // Interleaved bursts
    wire [12:0] mrd_val  = { 3'b000,		// Reserved
 			    ~mrd_wburst,	// Write burst disable
@@ -119,27 +131,33 @@ module sdram (
       max3 = max(max(a,b),c);
    endfunction // max3
 
-   // Command opcodes (CS#, RAS#, CAS#, WE#)
-   parameter		    cmd_desl = 4'b1111;	// Deselect (= NOP)
-   parameter		    cmd_nop  = 4'b0111; // NO OPERATION
-   parameter		    cmd_bst  = 4'b0110; // BURST TERMINATE
-   parameter		    cmd_rd   = 4'b0101; // READ
-   parameter		    cmd_wr   = 4'b0100; // WRITE
-   parameter		    cmd_act  = 4'b0011; // ACTIVE
-   parameter		    cmd_pre  = 4'b0010; // PRECHARGE
-   parameter		    cmd_ref  = 4'b0001; // AUTO REFRESH
-   parameter		    cmd_mrd  = 4'b0000; // LOAD MODE REGISTER
-
    // Where to issue a PRECHARGE when we only want to read one word
    // (terminate the burst as soon as possible, but no sooner...)
-   parameter t_pre_rd_when = max(t_ras, t_rcd + 1);
+   localparam t_pre_rd_when = max(t_ras, t_rcd + 1);
 
    // Where to issue a PRECHARGE when we only want to write one word
    // (terminate the burst as soon as possible, but no sooner...)
-   parameter t_pre_wr_when = max(t_ras, t_rcd + t_wr);
-
-   // Actual burst length (2^burst)
-   parameter burst_n = 1 << burst;
+   localparam t_pre_wr_when = max(t_ras, t_rcd + t_wr);
+
+   // Actual burst length (2^burst_lg2)
+   localparam burst_n = 1 << burst_lg2;
+
+   // Command opcodes and attributes (is_rfsh, CS#, RAS#, CAS#, WE#)
+   localparam	cmd_desl = 5'b0_1111; // Deselect (= NOP)
+   localparam	cmd_nop  = 5'b0_0111;  // NO OPERATION
+   localparam	cmd_bst  = 5'b0_0110;  // BURST TERMINATE
+   localparam	cmd_rd   = 5'b0_0101;  // READ
+   localparam	cmd_wr   = 5'b0_0100;  // WRITE
+   localparam	cmd_act  = 5'b0_0011;  // ACTIVE
+   localparam	cmd_pre  = 5'b0_0010;  // PRECHARGE
+   localparam	cmd_ref  = 5'b1_0001;  // AUTO REFRESH
+   localparam	cmd_mrd  = 5'b0_0000;  // LOAD MODE REGISTER
+   reg [4:0]	dram_cmd;
+   wire		is_rfsh = dram_cmd[4];
+   assign	sr_cs_n  = dram_cmd[3];
+   assign	sr_ras_n = dram_cmd[2];
+   assign	sr_cas_n = dram_cmd[1];
+   assign	sr_we_n  = dram_cmd[0];
 
    // SDRAM output clock buffer. The SDRAM output clock is
    // inverted with respect to our internal clock, so that
@@ -160,12 +178,7 @@ module sdram (
    // SDRAM output signal registers
    reg			    dram_cke;
    assign		    sr_cke = dram_cke;
-   reg [3:0]		    dram_cmd;
-   assign		    sr_cs_n  = dram_cmd[3];
-   assign		    sr_ras_n = dram_cmd[2];
-   assign		    sr_cas_n = dram_cmd[1];
-   assign		    sr_we_n  = dram_cmd[0];
-   reg [11:0]		    dram_a;
+   reg [12:0]		    dram_a;
    assign		    sr_a = dram_a;
    reg [1:0]		    dram_ba;
    assign		    sr_ba = dram_ba;
@@ -181,38 +194,38 @@ module sdram (
 
    // Port 0 output signals
    assign                   rd0 = a0[0] ? dram_q[15:8] : dram_q[7:0];
-   reg			    rack0_q;
+   reg [t_rcd+t_cl+1:0]     rack0_q;
    assign                   rack0 = rack0_q;
-   reg			    wack0_q;
+   reg [t_rcd:0]	    wack0_q;
    assign                   wack0 = wack0_q;
 
    // Port 1 output signals
    assign                   rd1 = dram_q;
-   reg			    rack1_q;
+   reg [t_rcd+t_cl+1:0]	    rack1_q;
    assign                   rack1 = rack1_q;
-   reg			    wack1_q;
+   reg [t_rcd:0]	    wack1_q;
    assign                   wack1 = wack1_q;
 
    // State machine and counters
-   reg [t_ref:0]	    rfsh_ctr;  // Refresh timer
-   reg [t_p:t_ref]	    init_ctr;  // Reset to init counter
+   reg [t_refi_lg2:0]	    rfsh_ctr;  // Refresh timer
+   reg [t_p_lg2:t_refi_lg2] init_ctr;  // Reset to init counter
 
    // XXX: compute the necessary width of this field elsewhere
    reg [4:0]	            op_cycle;	// Cycles into the current operation
 
    // The actual values are unimportant; the compiler will optimize
-   // the state machine implementation for us.
-   reg [3:0]		    state;
-   parameter st_reset       = 4'h00;  // Reset until init timer expires
-   parameter st_init        = 4'h01;  // 1st refresh during initialization
-   parameter st_idle        = 4'h02;  // Idle state: all banks precharged
-   parameter st_rfsh        = 4'h03;
-   parameter st_p0_rd       = 4'h04;
-   parameter st_p0_wr       = 4'h05;
-   parameter st_p1_rd       = 4'h06;
-   parameter st_p1_wr       = 4'h07;
-
-   reg is_rfsh; // A refresh cycle, clear rfsh_ctr
+   // the state machine implementation.
+   typedef enum logic [2:0] {
+	 st_reset,		// Reset until init timer expires
+	 st_init,		// 1st refresh during initialization
+	 st_idle,		// Idle state: all banks precharged
+	 st_rfsh,
+	 st_p0_rd,
+	 st_p0_wr,
+	 st_p1_rd,
+	 st_p1_wr
+   } state_t;
+   state_t state = st_reset;
 
    always @(posedge clk or negedge rst_n)
      if (~rst_n)
@@ -222,17 +235,15 @@ module sdram (
        end
      else
        begin
-	  if (is_rfsh)
-	    rfsh_ctr <= 1'b0;
-	  else
-	    rfsh_ctr <= rfsh_ctr + 1'b1;
+	  rfsh_ctr <= is_rfsh ? 1'b0 : rfsh_ctr + 1'b1;
 
 	  // The refresh counter is also used as a prescaler
 	  // for the initialization counter.
-	  if (init_ctr[t_ref] ^ rfsh_ctr[t_ref])
+	  if (init_ctr[t_refi_lg2] ^ rfsh_ctr[t_refi_lg2])
 	    begin
-	       init_ctr[t_p:t_ref+1] <= init_ctr[t_p:t_ref+1] + 1'b1;
-	       init_ctr[t_ref] <= rfsh_ctr[t_ref];
+	       init_ctr[t_p_lg2:t_refi_lg2+1]
+		 <= init_ctr[t_p_lg2:t_refi_lg2+1] + 1'b1;
+	       init_ctr[t_refi_lg2] <= rfsh_ctr[t_refi_lg2];
 	    end
        end // else: !if(~rst_n)
 
@@ -253,7 +264,6 @@ module sdram (
 	  dram_d_en     <= 1'b1; // Don't float except during read
 	  op_cycle      <= 1'b0;
 	  state         <= st_reset;
-	  is_rfsh       <= 1'b0;
 
 	  rack0_q       <= 1'b0;
 	  wack0_q       <= 1'b0;
@@ -270,8 +280,6 @@ module sdram (
 	  dram_dqm      <= 2'b11;
 	  dram_d        <= 16'h0000;
 
-	  is_rfsh       <= 1'b0;
-
 	  rack0_q       <= 1'b0;
 	  wack0_q       <= 1'b0;
 	  rack1_q       <= 1'b0;
@@ -288,7 +296,7 @@ module sdram (
 	    st_reset:
 	      begin
 		 dram_cmd  <= cmd_desl;
-		 if (init_ctr[t_p])
+		 if (init_ctr[t_p_lg2])
 		   begin
 		      dram_cmd   <= cmd_pre;
 		      dram_a[10] <= 1'b1; // Precharge All Banks
@@ -297,17 +305,16 @@ module sdram (
 	      end
 	    st_init:
 	      begin
-		 if ( op_cycle == t_rp || op_cycle == t_rp + t_ref )
+		 if ( op_cycle == t_rp || op_cycle == t_rp + t_rfc )
 		   begin
 		      dram_cmd   <= cmd_ref;
-		      is_rfsh    <= 1'b1;
 		   end
-		 if ( op_cycle == t_rp + t_ref*2 )
+		 if ( op_cycle == t_rp + t_rfc*2 )
 		   begin
 		      dram_cmd   <= cmd_mrd;
 		      dram_a     <= mrd_val;
 		   end
-		 if ( op_cycle >= t_rp + t_ref*2 + t_mrd - 1 )
+		 if ( op_cycle >= t_rp + t_rfc*2 + t_mrd - 1 )
 		   state <= st_idle;
 	      end // case: st_init
 	    st_idle:
@@ -319,14 +326,23 @@ module sdram (
 		 // is started opportunistically if nothing is
 		 // pending and the refresh counter is no less than
 		 // half expired.
-		 casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_ctr[t_ref:t_ref-1]} )
+		 casez ( {rrq0|wrq0, rrq1|wrq1, rfsh_ctr[t_refi_lg2:t_refi_lg2-1]} )
 		   4'b1zzz:
 		     begin
 			// Begin port 0 transaction
 			dram_cmd    <= cmd_act;
 			dram_a      <= a0[24:12];
 			dram_ba     <= a0[11:10];
-			state       <= wrq0 ? st_p0_wr : st_p0_rd;
+			if ( wrq0 )
+			  begin
+			     state  <= st_p0_wr;
+			     wack0_q[t_rcd] <= 1'b1;
+			  end
+			else
+			  begin
+			     state  <= st_p0_rd;
+			     rack0_q[t_rcd + t_cl + 1] <= 1'b1;
+			  end
 		     end
 		   4'b010z:
 		     begin
@@ -334,13 +350,21 @@ module sdram (
 			dram_cmd    <= cmd_act;
 			dram_a      <= a1[24:12];
 			dram_ba     <= a1[11:10];
-			state       <= wrq1 ? st_p1_wr : st_p1_rd;
+			if ( wrq1 )
+			  begin
+			     state  <= st_p1_wr;
+			     wack1_q[t_rcd] <= 1'b1;
+			  end
+			else
+			  begin
+			     state  <= st_p1_rd;
+			     rack1_q[t_rcd + t_cl + 1] <= 1'b1;
+			  end
 		     end
 		   4'b0z1z, 4'b0001:
 		     begin
 			// Begin refresh transaction
 			dram_cmd    <= cmd_ref;
-			is_rfsh     <= 1'b1;
 			state       <= st_rfsh;
 		     end
 		   default:
@@ -363,14 +387,20 @@ module sdram (
 		 dram_a[10]  <= 1'b0;		// No auto precharge
 		 dram_dqm    <= 2'b00;
 
-		 if ( op_cycle == t_rfc )
+		 if ( op_cycle == t_rcd )
 		   dram_cmd <= cmd_rd;
 
 		 if ( op_cycle == t_pre_rd_when )
 		   dram_cmd <= cmd_pre; // Precharge and stop burst
 
-		 // Latch input data. The +1 is due to bus turnaround.
-		 if ( op_cycle == t_rfc + t_cl + 1 )
+		 // Latch and ack input data. There is an implicit
+		 // due to bus turnaround.
+		 for (int i = 0; i <= t_rcd + t_cl; i++)
+		   begin
+		      rack0_q[i] <= (op_cycle == t_rcd + t_cl + 1 - i);
+		   end
+
+		 if ( op_cycle == t_rcd + t_cl + 1 )
 		   begin
 		      dram_q      <= sr_dq;
 		      rack0_q     <= 1'b1;
@@ -386,11 +416,13 @@ module sdram (
 		 dram_a[10]       <= 1'b0;  // No auto precharge
 		 dram_d           <= { wd0, wd0 };
 
-		 // Due to register delay ack write one cycle early
-		 if ( op_cycle == t_rfc-1 )
-		   wack0_q        <= 1'b1;
+		 // Ack data
+		 for (int i = 0; i <= t_rcd; i++)
+		   begin
+		      wack0_q[i] <= (op_cycle == t_rcd - i);
+		   end
 
-		 if ( op_cycle == t_rfc )
+		 if ( op_cycle == t_rcd )
 		   begin
 		      dram_cmd <= cmd_wr;
 		      dram_dqm <= { ~a0[0], a0[0] };
@@ -412,19 +444,24 @@ module sdram (
 		 dram_a[10]  <= 1'b1;		// Auto precharge
 		 dram_dqm    <= 2'b00;
 
-		 if ( op_cycle == t_rfc )
+		 if ( op_cycle == t_rcd )
 		   dram_cmd <= cmd_rd;
 
-		 // Latch input data. There is an implicit +1
+		 // Latch and ack input data. There is an implicit +1
 		 // due to bus turnaround.
-		 if ( op_cycle > t_rfc + t_cl &&
-		      op_cycle <= t_rfc + t_cl + burst_n )
+		 for (int i = 0; i <= t_rcd + t_cl + 1; i++)
+		   begin
+		      rack1_q[i] <= (op_cycle > t_rcd + t_cl - i &&
+				     op_cycle <= t_rcd + t_cl + burst_n - i);
+		   end
+
+		 if ( op_cycle > t_rcd + t_cl &&
+		      op_cycle <= t_rcd + t_cl + burst_n )
 		   begin
 		      dram_q      <= sr_dq;
-		      rack1_q     <= 1'b1;
 		   end
 
-		 if ( op_cycle >= max(t_rc - 1, t_rfc + t_cl + burst_n) )
+		 if ( op_cycle >= max(t_rc - 1, t_rcd + t_cl + burst_n) )
 		   state <= st_idle;
 	      end // case: st_p1_rd
 	    st_p1_wr:
@@ -435,14 +472,17 @@ module sdram (
 		 dram_dqm    <= ~wbe1;
 		 dram_d      <= wd1;
 
-		 if ( op_cycle == t_rfc )
-		   dram_cmd <= cmd_wr;
+		 // Ack data
+		 for (int i = 0; i <= t_rcd; i++)
+		   begin
+		      wack1_q[i] <= (op_cycle >= t_rcd - i &&
+				     op_cycle < t_rcd + burst_n);
+		   end
 
-		 // Due to register delay ack write one cycle early
-		 if ( op_cycle >= t_rfc - 1 && op_cycle < t_rfc + burst_n - 1 )
-		   wack1_q        <= 1'b1;
+		 if ( op_cycle == t_rcd )
+		   dram_cmd <= cmd_wr;
 
-		 if ( op_cycle >= max(t_rfc + burst_n + t_wr + t_rp, t_rc) - 1 )
+		 if ( op_cycle >= max(t_rcd + burst_n + t_wr + t_rp, t_rc) - 1 )
 		   state <= st_idle;
 	      end // case: st_p1_wr
 	  endcase // case(state)