picorv32: further IRQ latency improvements; regenerate with Quartus 22.1

Further IRQ improvements to the picorv32 core. This should lay the
groundwork for using the hardware context switch for threading.

Recompile the FPGA using Quartus 22.1. The improvement is quite
noticable!

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

fpga/bypass.qsf

@@ -7,7 +7,7 @@ set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE EP4CE15F17C8
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:21:14  DECEMBER 22, 2021"
-set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

fpga/ip/int_osc.qsys

@@ -47,7 +47,7 @@
  <module
    name="int_osc_0"
    kind="altera_int_osc"
-   version="21.1"
+   version="22.1"
    enabled="1"
    autoexport="1">
   <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />

fpga/ip/int_osc.sopcinfo

@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="int_osc" kind="int_osc" version="1.0" fabric="QSYS">
- <!-- Format version 21.1 842 (Future versions may contain additional information.) -->
- <!-- 2021.12.09.22:00:36 -->
+ <!-- Format version 22.1 915 (Future versions may contain additional information.) -->
+ <!-- 2023.01.23.17:46:00 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1639116036</value>
+  <value>1674524760</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -68,7 +68,7 @@
  <module
    name="int_osc_0"
    kind="altera_int_osc"
-   version="21.1"
+   version="22.1"
    path="int_osc_0">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -154,7 +154,7 @@ the requested settings for a module instance. -->
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="oscena" kind="conduit_end" version="21.1">
+  <interface name="oscena" kind="conduit_end" version="22.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -203,7 +203,7 @@ parameters are a RESULT of the module parameters. -->
     <role>oscena</role>
    </port>
   </interface>
-  <interface name="clkout" kind="clock_source" version="21.1">
+  <interface name="clkout" kind="clock_source" version="22.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -283,7 +283,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>Internal Oscillator</displayName>
-  <version>21.1</version>
+  <version>22.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -291,7 +291,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Conduit</displayName>
-  <version>21.1</version>
+  <version>22.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -299,8 +299,8 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Output</displayName>
-  <version>21.1</version>
+  <version>22.1</version>
  </plugin>
- <reportVersion>21.1 842</reportVersion>
+ <reportVersion>22.1 915</reportVersion>
  <uniqueIdentifier></uniqueIdentifier>
 </EnsembleReport>

fpga/ip/int_osc/int_osc.csv

@@ -1,12 +1,12 @@
-# system info int_osc on 2021.12.09.22:00:35
+# system info int_osc on 2023.01.23.17:46:00
 system_info:
 name,value
 DEVICE,EP4CE15F17C8
 DEVICE_FAMILY,Cyclone IV E
-GENERATION_ID,1639116035
+GENERATION_ID,1674524759
 #
 #
-# Files generated for int_osc on 2021.12.09.22:00:35
+# Files generated for int_osc on 2023.01.23.17:46:00
 files:
 filepath,kind,attributes,module,is_top
 simulation/int_osc.v,VERILOG,,int_osc,true

fpga/ip/int_osc/int_osc.html

@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2021.12.09.22:00:36</td>
+    <td class="l">2023.01.23.17:46:00</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -95,7 +95,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   <a name="module_int_osc_0"> </a>
   <div>
    <hr/>
-   <h2>int_osc_0</h2>altera_int_osc v21.1
+   <h2>int_osc_0</h2>altera_int_osc v22.1
    <br/>
    <br/>
    <br/>

fpga/ip/int_osc/int_osc.xml

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <deploy
- date="2021.12.09.22:00:36"
+ date="2023.01.23.17:46:00"
  outputDirectory="/home/hpa/abc80/max80/fw/fpga/ip/int_osc/">
  <perimeter>
   <parameter
@@ -49,12 +49,12 @@
  </perimeter>
  <entity
    path=""
-   parameterizationKey="int_osc:1.0:AUTO_DEVICE=EP4CE15F17C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1639116036,AUTO_UNIQUE_ID=(altera_int_osc:21.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=UNKNOWN,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=Cyclone IV E,DEVICE_ID=UNKNOWN,INFORMATION=The maximum output frequency is 80MHz,PART_NAME=EP4CE15F17C8)"
+   parameterizationKey="int_osc:1.0:AUTO_DEVICE=EP4CE15F17C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1674524760,AUTO_UNIQUE_ID=(altera_int_osc:22.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=UNKNOWN,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=Cyclone IV E,DEVICE_ID=UNKNOWN,INFORMATION=The maximum output frequency is 80MHz,PART_NAME=EP4CE15F17C8)"
    instancePathKey="int_osc"
    kind="int_osc"
    version="1.0"
    name="int_osc">
-  <parameter name="AUTO_GENERATION_ID" value="1639116036" />
+  <parameter name="AUTO_GENERATION_ID" value="1674524760" />
   <parameter name="AUTO_DEVICE" value="EP4CE15F17C8" />
   <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
   <parameter name="AUTO_UNIQUE_ID" value="" />
@@ -75,7 +75,7 @@
   </sourceFiles>
   <childSourceFiles>
    <file
-       path="/opt/altera/21.1/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
+       path="/opt/altera/22.1/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
   </childSourceFiles>
   <messages>
    <message level="Debug" culprit="int_osc">queue size: 0 starting:int_osc "int_osc"</message>
@@ -99,10 +99,10 @@
  </entity>
  <entity
    path="submodules/"
-   parameterizationKey="altera_int_osc:21.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=UNKNOWN,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=Cyclone IV E,DEVICE_ID=UNKNOWN,INFORMATION=The maximum output frequency is 80MHz,PART_NAME=EP4CE15F17C8"
+   parameterizationKey="altera_int_osc:22.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=UNKNOWN,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=Cyclone IV E,DEVICE_ID=UNKNOWN,INFORMATION=The maximum output frequency is 80MHz,PART_NAME=EP4CE15F17C8"
    instancePathKey="int_osc:.:int_osc_0"
    kind="altera_int_osc"
-   version="21.1"
+   version="22.1"
    name="altera_int_osc">
   <parameter name="CLOCK_FREQUENCY_2" value="77" />
   <parameter name="CLOCK_FREQUENCY_1" value="116" />
@@ -121,7 +121,7 @@
   <childGeneratedFiles/>
   <sourceFiles>
    <file
-       path="/opt/altera/21.1/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
+       path="/opt/altera/22.1/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
   </sourceFiles>
   <childSourceFiles/>
   <instantiator instantiator="int_osc" as="int_osc_0" />

fpga/ip/int_osc/simulation/aldec/rivierapro_setup.tcl

@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2023 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 842 linux 2021.12.09.22:00:36
+# ACDS 22.1 915 linux 2023.01.23.17:46:00
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
@@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/opt/altera/21.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/opt/altera/22.1/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 

fpga/ip/int_osc/simulation/int_osc.sip

@@ -1,5 +1,5 @@
 set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_NAME "Qsys"
-set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_VERSION "22.1"
 set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "lib_int_osc" -name SPD_FILE [file join $::quartus(sip_path) "../int_osc.spd"]
 set_global_assignment -library "lib_int_osc" -name MISC_FILE [file join $::quartus(sip_path) "../../int_osc.qsys"]

fpga/ip/int_osc/simulation/int_osc.v

@@ -1,6 +1,6 @@
 // int_osc.v
 
-// Generated using ACDS version 21.1 842
+// Generated using ACDS version 22.1 915
 
 `timescale 1 ps / 1 ps
 module int_osc (

fpga/ip/int_osc/simulation/mentor/msim_setup.tcl

@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2023 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 842 linux 2021.12.09.22:00:35
+# ACDS 22.1 915 linux 2023.01.23.17:46:00
 
 # ----------------------------------------
 # Initialize variables
@@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/opt/altera/21.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/opt/altera/22.1/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 

fpga/ip/int_osc/simulation/submodules/altera_int_osc.v

@@ -1,11 +1,11 @@
 //altint_osc CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone IV E" clkout oscena
-//VERSION_BEGIN 21.1 cbx_altint_osc 2021:10:21:11:02:24:SJ cbx_arriav 2021:10:21:11:02:24:SJ cbx_cycloneii 2021:10:21:11:02:24:SJ cbx_lpm_add_sub 2021:10:21:11:02:24:SJ cbx_lpm_compare 2021:10:21:11:02:24:SJ cbx_lpm_counter 2021:10:21:11:02:24:SJ cbx_lpm_decode 2021:10:21:11:02:24:SJ cbx_mgl 2021:10:21:11:11:47:SJ cbx_nadder 2021:10:21:11:02:24:SJ cbx_nightfury 2021:10:21:11:02:24:SJ cbx_stratix 2021:10:21:11:02:24:SJ cbx_stratixii 2021:10:21:11:02:24:SJ cbx_stratixiii 2021:10:21:11:02:24:SJ cbx_stratixv 2021:10:21:11:02:24:SJ cbx_tgx 2021:10:21:11:02:24:SJ cbx_zippleback 2021:10:21:11:02:24:SJ  VERSION_END
+//VERSION_BEGIN 22.1 cbx_altint_osc 2022:10:25:15:32:10:SC cbx_arriav 2022:10:25:15:32:09:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_counter 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_nightfury 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_tgx 2022:10:25:15:32:10:SC cbx_zippleback 2022:10:25:15:32:10:SC  VERSION_END
 // synthesis VERILOG_INPUT_VERSION VERILOG_2001
 // altera message_off 10463
 
 
 
-// Copyright (C) 2021  Intel Corporation. All rights reserved.
+// Copyright (C) 2022  Intel Corporation. All rights reserved.
 //  Your use of Intel Corporation's design tools, logic functions 
 //  and other software and tools, and any partner logic 
 //  functions, and any output files from any of the foregoing 

fpga/ip/int_osc/simulation/synopsys/vcs/vcs_setup.sh

@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2023 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 842 linux 2021.12.09.22:00:36
+# ACDS 22.1 915 linux 2023.01.23.17:46:00
 
 # ----------------------------------------
 # vcs - auto-generated simulation script
@@ -94,12 +94,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 842 linux 2021.12.09.22:00:36
+# ACDS 22.1 915 linux 2023.01.23.17:46:00
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="int_osc"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/opt/altera/21.1/quartus/"
+QUARTUS_INSTALL_DIR="/opt/altera/22.1/quartus/"
 SKIP_FILE_COPY=0
 SKIP_SIM=0
 USER_DEFINED_ELAB_OPTIONS=""

fpga/ip/int_osc/simulation/synopsys/vcsmx/vcsmx_setup.sh

@@ -1,5 +1,5 @@
 
-# (C) 2001-2021 Altera Corporation. All rights reserved.
+# (C) 2001-2023 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 21.1 842 linux 2021.12.09.22:00:36
+# ACDS 22.1 915 linux 2023.01.23.17:46:00
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,12 +107,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 21.1 842 linux 2021.12.09.22:00:36
+# ACDS 22.1 915 linux 2023.01.23.17:46:00
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="int_osc"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/opt/altera/21.1/quartus/"
+QUARTUS_INSTALL_DIR="/opt/altera/22.1/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0

fpga/ip/int_osc/synthesis/int_osc.debuginfo

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport name="int_osc" kind="system" version="21.1" fabric="QSYS">
- <!-- Format version 21.1 842 (Future versions may contain additional information.) -->
- <!-- 2021.12.09.22:00:36 -->
+<EnsembleReport name="int_osc" kind="system" version="22.1" fabric="QSYS">
+ <!-- Format version 22.1 915 (Future versions may contain additional information.) -->
+ <!-- 2023.01.23.17:46:00 -->
  <!-- A collection of modules and connections -->
  <parameter name="clockCrossingAdapter">
   <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -53,7 +53,7 @@
  </parameter>
  <parameter name="generationId">
   <type>int</type>
-  <value>1639116036</value>
+  <value>1674524760</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
@@ -150,7 +150,7 @@
  <module
    name="int_osc_0"
    kind="altera_int_osc"
-   version="21.1"
+   version="22.1"
    path="int_osc_0">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -236,7 +236,7 @@ the requested settings for a module instance. -->
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="oscena" kind="conduit_end" version="21.1">
+  <interface name="oscena" kind="conduit_end" version="22.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -285,7 +285,7 @@ parameters are a RESULT of the module parameters. -->
     <role>oscena</role>
    </port>
   </interface>
-  <interface name="clkout" kind="clock_source" version="21.1">
+  <interface name="clkout" kind="clock_source" version="22.1">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -365,7 +365,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
   <displayName>Internal Oscillator</displayName>
-  <version>21.1</version>
+  <version>22.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -373,7 +373,7 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Conduit</displayName>
-  <version>21.1</version>
+  <version>22.1</version>
  </plugin>
  <plugin>
   <instanceCount>1</instanceCount>
@@ -381,8 +381,8 @@ parameters are a RESULT of the module parameters. -->
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Clock Output</displayName>
-  <version>21.1</version>
+  <version>22.1</version>
  </plugin>
- <reportVersion>21.1 842</reportVersion>
- <uniqueIdentifier>5254001B7C8D0000017DA2EDD937</uniqueIdentifier>
+ <reportVersion>22.1 915</reportVersion>
+ <uniqueIdentifier>5254001B7C8D00000185E1741B16</uniqueIdentifier>
 </EnsembleReport>

fpga/ip/int_osc/synthesis/int_osc.qip

@@ -1,8 +1,8 @@
 set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_NAME "Qsys"
-set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_VERSION "22.1"
 set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "int_osc" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../int_osc.sopcinfo"]
-set_global_assignment -entity "int_osc" -library "int_osc" -name SLD_INFO "QSYS_NAME int_osc HAS_SOPCINFO 1 GENERATION_ID 1639116036"
+set_global_assignment -entity "int_osc" -library "int_osc" -name SLD_INFO "QSYS_NAME int_osc HAS_SOPCINFO 1 GENERATION_ID 1674524760"
 set_global_assignment -library "int_osc" -name MISC_FILE [file join $::quartus(qip_path) "../int_osc.cmp"]
 set_global_assignment -library "int_osc" -name SLD_FILE [file join $::quartus(qip_path) "int_osc.debuginfo"]
 set_global_assignment -entity "int_osc" -library "int_osc" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
@@ -15,7 +15,7 @@ set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_DI
 set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYzOTExNjAzNg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3NDUyNDc2MA==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxNUYxN0M4::QXV0byBERVZJQ0U="
 set_global_assignment -entity "int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -24,7 +24,7 @@ set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPO
 set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_VERSION "MjEuMQ=="
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_VERSION "MjIuMQ=="
 set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_DESCRIPTION "SW50ZXJuYWwgT3NjaWxsYXRvciBwcm92aWRlcyBpbnRlcm5hbCBjbG9jayBzb3VyY2UgZm9yIGRlYnVnZ2luZyBwdXJwb3NlLg=="
 set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "SU5GT1JNQVRJT04=::VGhlIG1heGltdW0gb3V0cHV0IGZyZXF1ZW5jeSBpcyA4ME1Ieg==::SU5GT1JNQVRJT04="
 set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBJViBF::RGV2aWNlIGZhbWlseQ=="
@@ -37,5 +37,5 @@ set_global_assignment -library "int_osc" -name VERILOG_FILE [file join $::quartu
 set_global_assignment -library "int_osc" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_int_osc.v"]
 
 set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_NAME "altera_int_osc"
-set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_VERSION "22.1"
 set_global_assignment -entity "altera_int_osc" -library "int_osc" -name IP_TOOL_ENV "Qsys"

fpga/ip/int_osc/synthesis/int_osc.v

@@ -1,6 +1,6 @@
 // int_osc.v
 
-// Generated using ACDS version 21.1 842
+// Generated using ACDS version 22.1 915
 
 `timescale 1 ps / 1 ps
 module int_osc (

fpga/ip/int_osc/synthesis/submodules/altera_int_osc.v

@@ -1,11 +1,11 @@
 //altint_osc CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone IV E" clkout oscena
-//VERSION_BEGIN 21.1 cbx_altint_osc 2021:10:21:11:02:24:SJ cbx_arriav 2021:10:21:11:02:24:SJ cbx_cycloneii 2021:10:21:11:02:24:SJ cbx_lpm_add_sub 2021:10:21:11:02:24:SJ cbx_lpm_compare 2021:10:21:11:02:24:SJ cbx_lpm_counter 2021:10:21:11:02:24:SJ cbx_lpm_decode 2021:10:21:11:02:24:SJ cbx_mgl 2021:10:21:11:11:47:SJ cbx_nadder 2021:10:21:11:02:24:SJ cbx_nightfury 2021:10:21:11:02:24:SJ cbx_stratix 2021:10:21:11:02:24:SJ cbx_stratixii 2021:10:21:11:02:24:SJ cbx_stratixiii 2021:10:21:11:02:24:SJ cbx_stratixv 2021:10:21:11:02:24:SJ cbx_tgx 2021:10:21:11:02:24:SJ cbx_zippleback 2021:10:21:11:02:24:SJ  VERSION_END
+//VERSION_BEGIN 22.1 cbx_altint_osc 2022:10:25:15:32:10:SC cbx_arriav 2022:10:25:15:32:09:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_counter 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_nightfury 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_tgx 2022:10:25:15:32:10:SC cbx_zippleback 2022:10:25:15:32:10:SC  VERSION_END
 // synthesis VERILOG_INPUT_VERSION VERILOG_2001
 // altera message_off 10463
 
 
 
-// Copyright (C) 2021  Intel Corporation. All rights reserved.
+// Copyright (C) 2022  Intel Corporation. All rights reserved.
 //  Your use of Intel Corporation's design tools, logic functions 
 //  and other software and tools, and any partner logic 
 //  functions, and any output files from any of the foregoing 

fpga/ip/pll2_16.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_TOOL_VERSION "22.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll2_16.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2_16_bb.v"]

fpga/ip/pll2_16.v

@@ -9,16 +9,16 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
+//Copyright (C) 2022  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -343,5 +343,4 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16.bsf FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16_inst.v FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll2_16_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

fpga/ip/pll2_48.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_TOOL_VERSION "22.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll2_48.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll2_48_bb.v"]

fpga/ip/pll2_48.v

@@ -9,16 +9,16 @@
 // 			altpll
 //
 // Simulation Library Files(s):
-// 			altera_mf
+// 			
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+// 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2021  Intel Corporation. All rights reserved.
+//Copyright (C) 2022  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -343,5 +343,4 @@ endmodule
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48.bsf FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48_inst.v FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll2_48_bb.v TRUE
-// Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

fpga/ip/vjtag/synthesis/vjtag.qip

@@ -1,8 +1,8 @@
 set_global_assignment -entity "vjtag" -library "vjtag" -name IP_TOOL_NAME "Qsys"
-set_global_assignment -entity "vjtag" -library "vjtag" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "vjtag" -library "vjtag" -name IP_TOOL_VERSION "22.1"
 set_global_assignment -entity "vjtag" -library "vjtag" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "vjtag" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../vjtag.sopcinfo"]
-set_global_assignment -entity "vjtag" -library "vjtag" -name SLD_INFO "QSYS_NAME vjtag HAS_SOPCINFO 1 GENERATION_ID 1644142626"
+set_global_assignment -entity "vjtag" -library "vjtag" -name SLD_INFO "QSYS_NAME vjtag HAS_SOPCINFO 1 GENERATION_ID 1674524765"
 set_global_assignment -library "vjtag" -name MISC_FILE [file join $::quartus(qip_path) "../vjtag.cmp"]
 set_global_assignment -library "vjtag" -name SLD_FILE [file join $::quartus(qip_path) "vjtag.debuginfo"]
 set_global_assignment -entity "vjtag" -library "vjtag" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
@@ -15,7 +15,7 @@ set_global_assignment -entity "vjtag" -library "vjtag" -name IP_COMPONENT_DISPLA
 set_global_assignment -entity "vjtag" -library "vjtag" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "vjtag" -library "vjtag" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "vjtag" -library "vjtag" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "vjtag" -library "vjtag" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY0NDE0MjYyNg==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "vjtag" -library "vjtag" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3NDUyNDc2NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "vjtag" -library "vjtag" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "vjtag" -library "vjtag" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxNUYxN0M4::QXV0byBERVZJQ0U="
 set_global_assignment -entity "vjtag" -library "vjtag" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -24,7 +24,7 @@ set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPO
 set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPONENT_VERSION "MjEuMQ=="
+set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPONENT_VERSION "MjIuMQ=="
 set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPONENT_DESCRIPTION "VmlydHVhbCBKVEFHIEludGVyZmFjZSAoVkpJKSBtZWdhZnVuY3Rpb24uIFRoaXMgbWVnYWZ1bmN0aW9uIHByb3ZpZGVzIGFjY2VzcyB0byB0aGUgUExEIHNvdXJjZSB0aHJvdWdoIHRoZSBKVEFHIGludGVyZmFjZS4KVGhlIFF1YXJ0dXMgUHJpbWUgc29mdHdhcmUgb3IgSlRBRyBjb250cm9sIGhvc3QgaWRlbnRpZmllcyBlYWNoIGluc3RhbmNlIG9mIHRoaXMgbWVnYWZ1bmN0aW9uIGJ5IGEgdW5pcXVlIGluZGV4LiBFYWNoIG1lZ2FmdW5jdGlvbiBpbnN0YW5jZQpmdW5jdGlvbnMgaW4gYSBmbG93IHRoYXQgcmVzZW1ibGVzIHRoZSBKVEFHIG9wZXJhdGlvbiBvZiBhIGRldmljZS4gVGhlIGxvZ2ljIHRoYXQgdXNlcyB0aGlzIGludGVyZmFjZSBtdXN0IG1haW50YWluIHRoZSBjb250aW51aXR5IG9mCnRoZSBKVEFHIGNoYWluIG9uIGJlaGFsZiB0aGUgUExEIGRldmljZSB3aGVuIHRoaXMgaW5zdGFuY2UgYmVjb21lcyBhY3RpdmUu"
 set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlX2ZhbWlseQ=="
 set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hdXRvX2luZGV4::ZmFsc2U=::QXV0b21hdGljIEluc3RhbmNlIEluZGV4IEFzc2lnbm1lbnQ="
@@ -36,5 +36,5 @@ set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_COMPO
 set_global_assignment -library "vjtag" -name VERILOG_FILE [file join $::quartus(qip_path) "vjtag.v"]
 
 set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_TOOL_NAME "altera_virtual_jtag"
-set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_TOOL_VERSION "22.1"
 set_global_assignment -entity "sld_virtual_jtag" -library "vjtag" -name IP_TOOL_ENV "Qsys"

fpga/ip/vjtag/synthesis/vjtag.v

@@ -1,13 +1,13 @@
 // vjtag.v
 
-// Generated using ACDS version 21.1 842
+// Generated using ACDS version 22.1 915
 
 `timescale 1 ps / 1 ps
 module vjtag (
 		output wire       tdi,                // jtag.tdi
 		input  wire       tdo,                //     .tdo
-		output wire [4:0] ir_in,              //     .ir_in
-		input  wire [4:0] ir_out,             //     .ir_out
+		output wire [3:0] ir_in,              //     .ir_in
+		input  wire [3:0] ir_out,             //     .ir_out
 		output wire       virtual_state_cdr,  //     .virtual_state_cdr
 		output wire       virtual_state_sdr,  //     .virtual_state_sdr
 		output wire       virtual_state_e1dr, //     .virtual_state_e1dr
@@ -20,9 +20,9 @@ module vjtag (
 	);
 
 	sld_virtual_jtag #(
-		.sld_auto_instance_index ("YES"),
-		.sld_instance_index      (0),
-		.sld_ir_width            (5)
+		.sld_auto_instance_index ("NO"),
+		.sld_instance_index      (4),
+		.sld_ir_width            (4)
 	) virtual_jtag_0 (
 		.tdi                (tdi),                // jtag.tdi
 		.tdo                (tdo),                //     .tdo

fpga/max80.qpf

@@ -1,6 +1,6 @@
 # -------------------------------------------------------------------------- #
 #
-# Copyright (C) 2021  Intel Corporation. All rights reserved.
+# Copyright (C) 2022  Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions 
 # and other software and tools, and any partner logic 
 # functions, and any output files from any of the foregoing 
@@ -18,16 +18,16 @@
 # -------------------------------------------------------------------------- #
 #
 # Quartus Prime
-# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 00:10:29  January 23, 2023
+# Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
+# Date created = 18:09:55  January 23, 2023
 #
 # -------------------------------------------------------------------------- #
 
-QUARTUS_VERSION = "21.1"
-DATE = "00:10:29  January 23, 2023"
+QUARTUS_VERSION = "22.1"
+DATE = "18:09:55  January 23, 2023"
 
 # Revisions
 
-PROJECT_REVISION = "v1"
 PROJECT_REVISION = "v2"
+PROJECT_REVISION = "v1"
 PROJECT_REVISION = "bypass"

fpga/max80.sv

@@ -496,8 +496,8 @@ module max80
    wire        cpu_halt;
 
    picorv32 #(
-	      .ENABLE_COUNTERS ( 1 ),
-	      .ENABLE_COUNTERS64 ( 1 ),
+	      .COUNTER_CYCLE_WIDTH ( 64 ),
+	      .COUNTER_INSTR_WIDTH ( 0 ), // No use...
 	      .ENABLE_REGS_16_31 ( 1 ),
 	      .ENABLE_REGS_DUALPORT ( 1 ),
 	      .LATCHED_MEM_RDATA ( 0 ),

fpga/output/bypass.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2021  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2022  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 CHIP  "bypass"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

fpga/output/v1.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2021  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2022  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 CHIP  "v1"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

fpga/output/v2.pin

@@ -1,4 +1,4 @@
- -- Copyright (C) 2021  Intel Corporation. All rights reserved.
+ -- Copyright (C) 2022  Intel Corporation. All rights reserved.
  -- Your use of Intel Corporation's design tools, logic functions 
  -- and other software and tools, and any partner logic 
  -- functions, and any output files from any of the foregoing 
@@ -64,7 +64,7 @@
  -- Pin directions (input, output or bidir) are based on device operating in user mode.
  ---------------------------------------------------------------------------------
 
-Quartus Prime Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
+Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
 CHIP  "v2"  ASSIGNED TO AN: EP4CE15F17C8
 
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment

fpga/picorv32.v

@@ -15,14 +15,15 @@
  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- *  Changes by hpa 2021-2022:
+ *  Changes by hpa 2021-2023:
  *  - maskirq instruction takes a mask in rs2.
- *  - retirq opcode changed to mret; no functional change.
+ *  - retirq opcode changed to mret.
  *  - qregs replaced with a full register bank switch. In general,
  *    non-power-of-two register files don't save anything, especially in
  *    FPGAs.
  *  - getq and setq replaced with new instructions addqxi and addxqi
  *    for cross-bank register accesses if needed,
+ *    taking immediate as additive argument.
  *    e.g. for stack setup (addqxi sp,sp,frame_size).
  *  - PROGADDR_RESET and PROGADDR_IRQ changed to ports (allows external
  *    implementation of vectorized interrupts or fallback reset.)
@@ -30,8 +31,23 @@
  *  - add two masks to waitirq: an AND mask and an OR mask.
  *    waitirq exists if either all interrupts in the AND
  *    mask are pending or any interrupt in the OR mask is pending.
+ *    Note that waitirq with an AND mask of zero will exit immediately;
+ *    this can be used to poll the status of interrupts (masked and unmasked.)
  *  - multiple user (non-interrupt) register banks (tasks) now supported;
- *
+ *    these are set via a custom user_context CSR (0x7f0). They are numbered
+ *    starting with 1; 0 is reserved for the IRQ context. After reset,
+ *    this register is set to the maximum supported user context number.
+ *    Writing this register also causes a transition to the IRQ context,
+ *    so the context switch can be processed atomically.
+ *  - the interrupt return address moved the mepc CSR, to make it
+ *    globally available at interrupt time. This simplifies context switching.
+ *  - implement the ctz instruction from the Zbb extension to improve
+ *    interrupt latency by speeding up the dispatch substantially.
+ *  - new pollirq instruction: returns a mask of pending unmasked
+ *    interrupts AND ~rs1 OR rs2. EOIs pending unmasked interrupts AND ~rs1.
+ *    This is intended to avoid priority inversion in the IRQ dispatch.
+ *  - separately parameterize the width of the cycle and instruction counters;
+ *    they can be independently set to any value from 0 to 64 bits.
  */
 
 /* verilator lint_off WIDTH */
@@ -88,8 +104,8 @@ endfunction // do_ctz
  ***************************************************************/
 
 module picorv32 #(
-	parameter [ 0:0] ENABLE_COUNTERS = 1,
-	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter integer COUNTER_CYCLE_WIDTH = 64,
+	parameter integer COUNTER_INSTR_WIDTH = 64,
 	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
 	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
 	parameter [ 0:0] LATCHED_MEM_RDATA = 0,
@@ -111,9 +127,8 @@ module picorv32 #(
 	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
 	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
 	parameter [31:0] STACKADDR = 32'h ffff_ffff,
-	parameter [ 4:0] RA_IRQ_REG    = ENABLE_IRQ_QREGS ? 26 : 3,
-	parameter [ 4:0] MASK_IRQ_REG  = ENABLE_IRQ_QREGS ? 27 : 4,
-        parameter        USER_CONTEXTS = 1,
+	parameter [ 4:0] MASK_IRQ_REG = ENABLE_IRQ_QREGS ? 27 : 4,
+	parameter	 USER_CONTEXTS = 1,
 	parameter [ 0:0] ENABLE_IRQ_QREGS = USER_CONTEXTS > 0
 ) (
 	input		  clk, resetn,
@@ -121,7 +136,7 @@ module picorv32 #(
 	output reg	  trap,
 
 	input [31:0]	  progaddr_reset,
-        input [31:0]	  progaddr_irq,
+	input [31:0]	  progaddr_irq,
 
 	output reg	  mem_valid,
 	output reg	  mem_instr,
@@ -215,8 +230,12 @@ module picorv32 #(
 	localparam [35:0] TRACE_ADDR   = {4'b 0010, 32'b 0};
 	localparam [35:0] TRACE_IRQ    = {4'b 1000, 32'b 0};
 
-	reg [63:0] count_cycle, count_instr;
-	reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
+        reg [63:0]  count_cycle;
+        localparam [63:0] count_cycle_mask = (1'b1 << COUNTER_CYCLE_WIDTH) - 1'b1;
+        reg  [63:0] count_instr;
+        localparam [63:0] count_instr_mask = (1'b1 << COUNTER_INSTR_WIDTH) - 1'b1;
+
+	reg [31:0] reg_pc, reg_next_pc, reg_mepc, reg_op1, reg_op2, reg_out;
 	reg [4:0] reg_sh;
 
 	reg [31:0] next_insn_opcode;
@@ -695,7 +714,7 @@ module picorv32 #(
 	reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
 	reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
 	reg instr_csrr, instr_ecall_ebreak;
-	reg instr_addqxi, instr_addxqi, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
+	reg instr_addqxi, instr_addxqi, instr_retirq, instr_maskirq, instr_waitirq, instr_timer, instr_pollirq;
 	reg instr_ctz;
         reg [2:0] instr_funct2;
 
@@ -730,7 +749,7 @@ module picorv32 #(
 			instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
 			instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
 			instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
-			instr_csrr, instr_addqxi, instr_retirq, instr_maskirq, instr_waitirq, instr_timer, instr_ctz};
+			instr_csrr, instr_addqxi, instr_retirq, instr_maskirq, instr_waitirq, instr_timer, instr_pollirq, instr_ctz};
 
 	reg [63:0] new_ascii_instr;
 	`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
@@ -793,10 +812,11 @@ module picorv32 #(
 
 	        if (instr_addqxi)   new_ascii_instr = "addqxi";
 	        if (instr_addxqi)   new_ascii_instr = "addxqi";
-		if (instr_retirq)   new_ascii_instr = "retirq";
+	        if (instr_retirq)   new_ascii_instr = "mret";
 		if (instr_maskirq)  new_ascii_instr = "maskirq";
 		if (instr_waitirq)  new_ascii_instr = "waitirq";
 		if (instr_timer)    new_ascii_instr = "timer";
+	        if (instr_pollirq)  new_ascii_instr = "pollirq";
 	end
 
 	reg [63:0] q_ascii_instr;
@@ -929,9 +949,6 @@ module picorv32 #(
 			decoded_rs1   <= mem_rdata_latched[19:15];
 			decoded_rs2   <= mem_rdata_latched[24:20];
 
-		        if (instr_la_retirq)
-				decoded_rs1 <= RA_IRQ_REG;
-
 			compressed_instr <= 0;
 			if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
 				compressed_instr <= 1;
@@ -1148,6 +1165,8 @@ module picorv32 #(
 			instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
 			instr_waitirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000100 && ENABLE_IRQ;
 			instr_timer   <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
+		        instr_pollirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000110 && ENABLE_IRQ;
+
 
 			// instr_addqxi includes addxqi; instr_addxqi is only used for debug
 		        instr_addqxi  <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[14:13] == 2'b01  && ENABLE_IRQ && ENABLE_IRQ_QREGS;
@@ -1230,6 +1249,7 @@ module picorv32 #(
 		        instr_addxqi <= 0;
 		        instr_maskirq <= 0;
 		        instr_waitirq <= 0;
+		        instr_pollirq <= 0;
 		        instr_timer   <= 0;
 
 		        instr_ecall_ebreak <= 0;
@@ -1394,10 +1414,6 @@ module picorv32 #(
 					cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
 					cpuregs_write = 1;
 				end
-				ENABLE_IRQ && irq_state[0]: begin
-					cpuregs_wrdata = reg_next_pc | latched_compr;
-					cpuregs_write = 1;
-				end
 				ENABLE_IRQ && irq_state[1]: begin
 					cpuregs_wrdata = irq_pending & ~irq_mask;
 					cpuregs_write = 1;
@@ -1516,14 +1532,6 @@ module picorv32 #(
 			pcpi_timeout <= !pcpi_timeout_counter;
 		end
 
-		if (ENABLE_COUNTERS) begin
-			count_cycle <= resetn ? count_cycle + 1 : 0;
-			if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
-		end else begin
-			count_cycle <= 'bx;
-			count_instr <= 'bx;
-		end
-
 		next_irq_pending = ENABLE_IRQ ? (irq_pending & LATCHED_IRQ & ~MASKED_IRQ) : 'bx;
 
 		if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
@@ -1541,11 +1549,16 @@ module picorv32 #(
 		if (!ENABLE_TRACE)
 			trace_data <= 'bx;
 
+	        if (!resetn)
+			count_cycle <= 0;
+	        else
+			count_cycle <= (count_cycle + 1'b1) & count_cycle_mask;
+
 		if (!resetn) begin
 			reg_pc <= progaddr_reset;
 			reg_next_pc <= progaddr_reset;
-			if (ENABLE_COUNTERS)
-				count_instr <= 0;
+		        reg_mepc <= 0;
+		        count_instr <= 0;
 			latched_store <= 0;
 			latched_stalu <= 0;
 			latched_branch <= 0;
@@ -1569,7 +1582,7 @@ module picorv32 #(
 				reg_out <= STACKADDR;
 			end
 			cpu_state <= cpu_state_fetch;
-		end else
+		end else // if (!resetn)
 		(* parallel_case, full_case *)
 		case (cpu_state)
 			cpu_state_trap: begin
@@ -1592,7 +1605,7 @@ module picorv32 #(
 						`debug($display("ST_RD:  %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
 					end
 					ENABLE_IRQ && irq_state[0]: begin
-						current_pc = progaddr_irq;
+						current_pc = progaddr_irq & ~1;
 						irq_active <= 1;
 						mem_do_rinst <= 1;
 					end
@@ -1631,7 +1644,8 @@ module picorv32 #(
 						irq_state == 2'b00 ? 2'b01 :
 						irq_state == 2'b01 ? 2'b10 : 2'b00;
 					latched_compr <= latched_compr;
-				        latched_rd <= irq_state[0] ? MASK_IRQ_REG : RA_IRQ_REG;
+				        latched_rd <= MASK_IRQ_REG;
+				        reg_mepc  <= reg_next_pc | latched_compr;
 				end else
 				if (ENABLE_IRQ && do_waitirq) begin
 					if (&(irq_pending | ~reg_op1) || |(irq_pending & reg_op2)) begin
@@ -1654,10 +1668,7 @@ module picorv32 #(
 					reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
 					if (ENABLE_TRACE)
 						latched_trace <= 1;
-					if (ENABLE_COUNTERS) begin
-						count_instr <= count_instr + 1;
-						if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
-					end
+				        count_instr <= (count_instr + 1'b1) & count_instr_mask;
 					if (instr_jal) begin
 						mem_do_rinst <= 1;
 						reg_next_pc <= current_pc + decoded_imm_j;
@@ -1722,13 +1733,15 @@ module picorv32 #(
 						reg_out <= 32'bx;
 						case (decoded_imm[11:0])
 							12'hc00, 12'hc01:	 // cycle, time
-							  if (ENABLE_COUNTERS)   reg_out <= count_cycle[31:0];
+							  reg_out <= count_cycle[31:0];
 							12'hc80, 12'hc81:	 // cycleh, timeh
-							  if (ENABLE_COUNTERS64) reg_out <= count_cycle[63:32];
+							  reg_out <= count_cycle[63:32];
 							12'hc02:		 // instret (rdinstr)
-							  if (ENABLE_COUNTERS)   reg_out <= count_instr[31:0];
+							  reg_out <= count_instr[31:0];
 							12'hc82:		 // instret (rdinstr)
-							  if (ENABLE_COUNTERS64) reg_out <= count_instr[63:32];
+							  reg_out <= count_instr[63:32];
+						        12'h341:		 // mepc
+							  if (ENABLE_IRQ) reg_out <= reg_mepc;
 							12'h343:		 // mtval
 							  if (CATCH_MISALIGN)    reg_out <= buserr_address;
 						        12'h7f0:                 // user_context
@@ -1740,6 +1753,9 @@ module picorv32 #(
 					        // Bitops not supported ATM, treat as readonly
 					        if (~instr_funct2[1])
 						  case (decoded_imm[11:0])
+						    12'h341: begin		        // mepc
+						       reg_mepc <= csrr_src;
+						    end
 						    12'h7f0: begin			// user_context
 						       user_context <= csrr_src;
 						       irq_active   <= 1'b1;
@@ -1766,9 +1782,9 @@ module picorv32 #(
 						irq_active <= 0;
 						latched_branch <= 1;
 						latched_store <= 1;
-						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
-						reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
-						dbg_rs1val <= cpuregs_rs1;
+					        `debug($display("MRET: 0x%08x", reg_mepc);)
+					        reg_out <= reg_mepc & ~1;
+					        dbg_rs1val <= reg_mepc;
 						dbg_rs1val_valid <= 1;
 						cpu_state <= cpu_state_fetch;
 					end
@@ -1806,6 +1822,12 @@ module picorv32 #(
 						dbg_rs1val_valid <= 1;
 						cpu_state <= cpu_state_fetch;
 					end
+				        ENABLE_IRQ && instr_pollirq: begin
+						latched_store <= 1;
+					        reg_out <= (irq_pending & ~irq_mask & ~cpuregs_rs1) | cpuregs_rs2;
+					        eoi <= irq_pending & ~irq_mask & ~cpuregs_rs1;
+					        next_irq_pending = next_irq_pending & (irq_mask | cpuregs_rs1);
+					end
 					is_lb_lh_lw_lbu_lhu && !instr_trap: begin
 						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
 						reg_op1 <= cpuregs_rs1;

fpga/v1.qsf

@@ -4,4 +4,212 @@
 # can just be reset.
 #
 
+
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v1_main.qsf
+set_global_assignment -name VERILOG_FILE ip/pll2_48.v
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to gpio[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_inp_n[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[13]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to abc_a[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to tty_txd
+set_global_assignment -name TOP_LEVEL_ENTITY v1
+set_global_assignment -name SOURCE_FILE v1.pins
+set_global_assignment -name SYSTEMVERILOG_FILE v1.sv
+set_global_assignment -name QIP_FILE ip/pll2_48.qip
+set_global_assignment -name SOURCE_FILE output/v1.jic.cof
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE max80.qsf
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE15F17C8
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:21:14  DECEMBER 22, 2021"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name DEVICE_MIGRATION_LIST EP4CE15F17C8
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VCCA_USER_VOLTAGE 2.5V
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
+set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
+set_global_assignment -name MUX_RESTRUCTURE AUTO
+set_global_assignment -name WEAK_PULL_UP_RESISTOR ON
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
+set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name GENERATE_JBC_FILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_*
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 6
+set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[2]
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[1]
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[0]
+set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[0]
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 7
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 4
+set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_clk
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to board_id
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION ALL_NODES -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME max80 -section_id eda_simulation
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to led[1]
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCQ128A
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:scripts/preflow.tcl"
+set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/postmodule.tcl"
+set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testclk -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME testclk -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME max80 -section_id testclk
+set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ms" -section_id testclk
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testclk -section_id testclk
+set_global_assignment -name EDA_TEST_BENCH_FILE simulation/testclk.sv -section_id testclk
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS ON -section_id eda_simulation
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rtc_32khz
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hc
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to exth_hh
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdo
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tck
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tdi
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to altera_reserved_tms
+set_global_assignment -name OCP_HW_EVAL DISABLE
+set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING ON
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS ON
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION ON
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
+set_global_assignment -name POWER_USE_TA_VALUE 35
+set_location_assignment PLL_3 -to "max80:max80|pll3:pll3|altpll:altpll_component|pll3_altpll:auto_generated|pll1"
+set_location_assignment PLL_4 -to "max80:max80|pll4:pll4|altpll:altpll_component|pll4_altpll:auto_generated|pll1"
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[15]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[14]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[13]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[12]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[11]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[10]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[9]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[8]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[7]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rngio[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rngio[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to rngio[2]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VERILOG_FILE usb/usb_desc.v
+set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usb_cdc_core.sv
+set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usbf_device_core.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rng.sv
+set_global_assignment -name QIP_FILE ip/int_osc/synthesis/int_osc.qip
+set_global_assignment -name VERILOG_FILE ip/pll4.v
+set_global_assignment -name VERILOG_FILE ip/pll3.v
+set_global_assignment -name VERILOG_FILE usb/usb_fs_phy/src_v/usb_fs_phy.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_tx.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_rx.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_defs.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_crc16.v
+set_global_assignment -name SYSTEMVERILOG_FILE usb/usb.sv
+set_global_assignment -name VERILOG_INCLUDE_FILE usb/usbparam.vh
+set_global_assignment -name SYSTEMVERILOG_FILE dcpktfifo.sv
+set_global_assignment -name VERILOG_FILE ip/statusram.v
+set_global_assignment -name VERILOG_INCLUDE_FILE iodevs.vh
+set_global_assignment -name SYSTEMVERILOG_FILE serial.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sdcard.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sysclock.sv
+set_global_assignment -name SYSTEMVERILOG_FILE i2c.sv
+set_global_assignment -name SYSTEMVERILOG_FILE abcbus.sv
+set_global_assignment -name VERILOG_FILE ip/abcmapram.v
+set_global_assignment -name SYSTEMVERILOG_FILE fast_mem.sv
+set_global_assignment -name MIF_FILE mif/sram.mif
+set_global_assignment -name VERILOG_FILE picorv32.v
+set_global_assignment -name SYSTEMVERILOG_FILE functions.sv
+set_global_assignment -name SYSTEMVERILOG_FILE spi_master.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
+set_global_assignment -name SYSTEMVERILOG_FILE spirom.sv
+set_global_assignment -name SYSTEMVERILOG_FILE clkbuf.sv
+set_global_assignment -name VERILOG_FILE ip/ddio_out.v
+set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
+set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl
+set_global_assignment -name VERILOG_FILE ip/hdmitx.v
+set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
+set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
+set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
+set_global_assignment -name SYSTEMVERILOG_FILE video.sv
+set_global_assignment -name SYSTEMVERILOG_FILE esp.sv
+set_global_assignment -name SDC_FILE max80.sdc
+set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
+set_global_assignment -name VERILOG_FILE ip/fifo.v
+set_global_assignment -name VERILOG_FILE ip/ddufifo.v
+set_global_assignment -name SYSTEMVERILOG_FILE vjtag_max80.sv
+set_global_assignment -name VERILOG_FILE ip/vjtag/synthesis/vjtag.v
+set_global_assignment -name QIP_FILE ip/vjtag/synthesis/vjtag.qip
+set_global_assignment -name SYSTEMVERILOG_FILE fpgarst.sv
+set_global_assignment -name VERILOG_FILE ip/altera_remote_update_core.v
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"

fpga/v2.qsf

@@ -4,4 +4,62 @@
 # can just be reset.
 #
 
+
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE v2_main.qsf
+set_global_assignment -name TOP_LEVEL_ENTITY v2
+set_global_assignment -name SOURCE_FILE output/v2.jic.cof
+set_global_assignment -name SYSTEMVERILOG_FILE v2.sv
+set_global_assignment -name SOURCE_FILE v2.pins
+set_global_assignment -name QIP_FILE ip/pll2_16.qip
+set_global_assignment -name VERILOG_INCLUDE_FILE v2.vh
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE max80.qsf
+set_global_assignment -name VERILOG_FILE usb/usb_desc.v
+set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usb_cdc_core.sv
+set_global_assignment -name SYSTEMVERILOG_FILE usb/usb_serial/src_v/usbf_device_core.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rng.sv
+set_global_assignment -name QIP_FILE ip/int_osc/synthesis/int_osc.qip
+set_global_assignment -name VERILOG_FILE ip/pll4.v
+set_global_assignment -name VERILOG_FILE ip/pll3.v
+set_global_assignment -name VERILOG_FILE usb/usb_fs_phy/src_v/usb_fs_phy.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_tx.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_rx.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_defs.v
+set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_crc16.v
+set_global_assignment -name SYSTEMVERILOG_FILE usb/usb.sv
+set_global_assignment -name VERILOG_INCLUDE_FILE usb/usbparam.vh
+set_global_assignment -name SYSTEMVERILOG_FILE dcpktfifo.sv
+set_global_assignment -name VERILOG_FILE ip/statusram.v
+set_global_assignment -name VERILOG_INCLUDE_FILE iodevs.vh
+set_global_assignment -name SYSTEMVERILOG_FILE serial.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sdcard.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sysclock.sv
+set_global_assignment -name SYSTEMVERILOG_FILE i2c.sv
+set_global_assignment -name SYSTEMVERILOG_FILE abcbus.sv
+set_global_assignment -name VERILOG_FILE ip/abcmapram.v
+set_global_assignment -name SYSTEMVERILOG_FILE fast_mem.sv
+set_global_assignment -name MIF_FILE mif/sram.mif
+set_global_assignment -name VERILOG_FILE picorv32.v
+set_global_assignment -name SYSTEMVERILOG_FILE functions.sv
+set_global_assignment -name SYSTEMVERILOG_FILE spi_master.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
+set_global_assignment -name SYSTEMVERILOG_FILE spirom.sv
+set_global_assignment -name SYSTEMVERILOG_FILE clkbuf.sv
+set_global_assignment -name VERILOG_FILE ip/ddio_out.v
+set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
+set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl
+set_global_assignment -name VERILOG_FILE ip/hdmitx.v
+set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
+set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
+set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
+set_global_assignment -name SYSTEMVERILOG_FILE video.sv
+set_global_assignment -name SYSTEMVERILOG_FILE esp.sv
+set_global_assignment -name SDC_FILE max80.sdc
+set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
+set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
+set_global_assignment -name VERILOG_FILE ip/fifo.v
+set_global_assignment -name VERILOG_FILE ip/ddufifo.v
+set_global_assignment -name SYSTEMVERILOG_FILE vjtag_max80.sv
+set_global_assignment -name QIP_FILE ip/vjtag/synthesis/vjtag.qip
+set_global_assignment -name SYSTEMVERILOG_FILE fpgarst.sv
+set_global_assignment -name VERILOG_FILE ip/altera_remote_update_core.v
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition"

rv32/checksum.h

@@ -1,4 +1,4 @@
 #ifndef CHECKSUM_H
 #define CHECKSUM_H
-#define SDRAM_SUM 0x81d1da2a
+#define SDRAM_SUM 0x8751cf2a
 #endif

rv32/irqasm.S

@@ -15,8 +15,7 @@
 	.option norvc		// Just messes up alignment
 	.option arch, +zbb	// Enable the ctz instruction
 _irq:
-	// s10 contains the IRQ return address, s11 the mask of
-	// IRQs to be handled.
+	// s11 contains the mask of IRQs to be handled.
 
 .Lirq_loop:
 	ctz a0,s11	// Vector number
@@ -26,9 +25,14 @@ _irq:
 	.option relax
 	jalr ra
 
-	// Strip the lowest set bit of s11
+	// Strip the lowest set bit of s11 - the interrupt just handled
 	addi t1,s11,-1
 	and  s11,s11,t1
+
+	// Check for newly arrived higher priority interrupts; this
+	// avoids priority inversion. This will also send EOI (really
+	// INTACK) for those interrupts.
+	pollirq s11,zero,s11
 	bnez s11,.Lirq_loop
 	mret
 

rv32/killed.c

@@ -6,16 +6,17 @@
 #include "irq.h"
 
 /* Don't mark no_return or gcc moves it to SDRAM */
-static void __hot __text_hot killed(const char *how, size_t pc)
+static void __hot __text_hot killed(const char *how)
 {
     /* Cannot use con_printf() here */
     const uint16_t *pcp;
     size_t mtval;
+    size_t mepc;
+    size_t pc;
 
-    asm volatile("csrr %0,mtval" : "=r" (mtval));
-
-    /* Try to move back to the previous instruction (if not a jump...) */
-    pc += -4 + (pc & 1);
+    /* Try to move back to the previous instruction (wrong for jumps...) */
+    asm volatile("csrr %0,mepc" : "=r" (mepc));
+    pc = mepc-4 + (mepc & 1);
     pcp = (const uint16_t *)pc;
 
     con_puts(hotstr("ERROR: "));
@@ -25,6 +26,7 @@ static void __hot __text_hot killed(const char *how, size_t pc)
     con_puts(hotstr(" (0x"));
     con_print_hex((pcp[1] << 16) + pcp[0]);
     con_puts(hotstr(")\nBad address: 0x"));
+    asm volatile("csrr %0,mtval" : "=r" (mtval));
     con_print_hex(mtval);
     con_putc('\n');
 
@@ -41,14 +43,12 @@ static void __hot __text_hot killed(const char *how, size_t pc)
     reset(SYS_RESET_SOFT);
 }
 
-register size_t _pc asm(IRQ_PC_REGISTER);
-
 IRQHANDLER(buserr,0)
 {
-    killed(hotstr("misaligned"), _pc);
+    killed(hotstr("misaligned"));
 }
 
 IRQHANDLER(ebreak,0)
 {
-    killed(hotstr("invalid instruction"), _pc);
+    killed(hotstr("invalid instruction"));
 }

rv32/picorv32.h

@@ -46,6 +46,17 @@ static inline unsigned int p_timer(unsigned int newval)
     asm volatile(".insn 0x0b, 0, 5, %0, %z1, %z2"
 		 : "=r" (oldval)
 		 : "Jr" (newval), "Jr" (0));
+    return oldval;
+}
+
+static inline unsigned int
+p_pollirq(unsigned int mask, unsigned int already)
+{
+    unsigned int irqs;
+    asm volatile(".insn 0x0b, 0, 6, %0, %z1, %z2"
+		 : "=r" (irqs)
+		 : "Jr" (mask), "Jr" (already));
+    return irqs;
 }
 
 #else  /* __ASSEMBLY__ */
@@ -77,6 +88,10 @@ static inline unsigned int p_timer(unsigned int newval)
 	.insn r 0x0b, 0, 5, \rd, \rs, zero
 .endm
 
+.macro pollirq rd, mask, already
+	.insn r 0x0b, 0, 6, \rd, \mask, \already
+.endm
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* PICORV32_H */

tools/gnusrc/binutils

@@ -1 +1 @@
-Subproject commit 93cca4cb80a332b97d1164866e1aa721b1ce925f
+Subproject commit 2c90c941d59acdc6d9948e4bdbfed6e9ef4fec3a