sdram: fix initialization sequence again

Init state counter was not working; fix it again.

fpga/sdram.sv

@@ -247,9 +247,10 @@ module sdram
 	  init_ctr <= init_ctr + rfsh_tick;
        end // else: !if(~rst_n)
 
-   reg [3:0] op_cycle;		// Cycle into the current operation
-   reg 	     op_zero;		// op_cycle wrap around
-   reg [1:0] init_op_ctr;	// op_cycle extension for init states
+   reg [5:0] op_ctr;		// Cycle into the current state
+   wire [3:0] op_cycle    = op_ctr[3:0]; // Cycle into the current command
+   wire [1:0] init_op_ctr = op_ctr[5:4]; // Init operation counter
+   reg 	      op_zero;		// op_cycle wrap around (init_op_ctr changed)
    
    reg [31:0] wdata_q;
    reg [ 3:0] be_q;
@@ -274,9 +275,8 @@ module sdram
 	  dram_d        <= 16'hxxxx;
 	  dram_d_en     <= 1'b1; // Don't float except during read
 
-	  op_cycle      <= 4'h0;
+	  op_ctr        <= 6'h0;
 	  op_zero       <= 1'b0;
-	  init_op_ctr   <= 2'b00;
 	  state         <= st_reset;
 	  is_write      <= 1'bx;
 
@@ -317,13 +317,15 @@ module sdram
 	  wacc2 <= 1'b0;
 
 	  if (state == st_reset || state == st_idle)
-	    op_cycle <= 1'b0;
+	    begin
+	       op_ctr    <= 6'b0;
+	       op_zero   <= 1'b0;
+	    end
 	  else
-	    op_cycle <= op_cycle + 1'b1;
-
-	  op_zero <= |op_cycle;
-	  if (|op_cycle)
-	    init_op_ctr <= init_op_ctr + 1'b1;
+	    begin
+	       op_ctr <= op_ctr + 1'b1;
+	       op_zero <= &op_cycle; // About to wrap around
+	    end // else: !if(state == st_reset || state == st_idle)
 	  
 	  case (state)
 	    st_reset:
@@ -551,7 +553,7 @@ module sdram
 			begin
 			   // Burst can continue
 			   wacc2       <= 1'b1;
-			   op_cycle    <= 1;
+			   op_ctr[3:0] <= 4'd1;
 			end
 		   end // case: 4
 		   6: begin