fpga/abcbus: fix clear_irq signal

fpga/abcbus.sv

@@ -463,7 +463,7 @@ module abcbus (
 		   abc_iobase <= cpu_wdata[24:4];
 		 5'b??100:
 		   irq_mask   <= cpu_wdata;
-		 5'b??100:
+		 5'b??101:
 		   clear_irq  <= 1'b1;
 		 default:
 		   /* do nothing */ ;