fpga: code lint fixes (no functional change)

fpga/abcbus.sv

@@ -133,9 +133,9 @@ module abcbus (
    reg  [7:0] abc_do;
    assign abc_d    = abc_d_oe ? abc_do : 8'hzz;
 
-   reg [8:0]  ioselx;
+   reg  [8:0] ioselx;
    wire       iosel_en = ioselx[8];
-   wire       iosel = ioselx[5:0];
+   wire [5:0] iosel = ioselx[5:0];
 
    // ABC-bus I/O select
    always @(negedge rst_n or posedge sdram_clk)
@@ -501,7 +501,7 @@ module abcbus (
 			 bus_change_mask <= cpu_wdata[31:28] & bus_change_valid;
 		      end
 		 end
-		 5'b???011: begin
+		 5'b??011: begin
 		    if (cpu_wstrb[0])
 		      begin
 			 abc_resin      <= cpu_wdata[3];
@@ -510,7 +510,7 @@ module abcbus (
 			 abc_wait_force <= cpu_wdata[0];
 		      end
 		 end
-		 5'b???101: begin
+		 5'b??101: begin
 		    if (cpu_wstrb[0])
 		      reg_inp_data[0] <= cpu_wdata[7:0];
 		    if (cpu_wstrb[1])

fpga/max80.sv

@@ -269,7 +269,7 @@ module max80 (
    wire [ 7:0] abc_sr_rd;
    wire        abc_sr_rrq;
    wire        abc_sr_rack;
-   wire        abc_sr_ready;
+   wire        abc_sr_rready;
    wire [ 7:0] abc_sr_wd;
    wire        abc_sr_wrq;
    wire        abc_sr_wack;