usb: set FIFO size to 1K

Quartus apparently can't figure out to merge FIFOs in the current
implementation, so just set the FIFO size to 1K for now. Can be
revisited if we start running out of RAM blocks.

fpga/ip/cdc_fifo.v

@@ -61,10 +61,10 @@ module cdc_fifo (
 	output	[7:0]  q;
 	output	  rdempty;
 	output	  rdfull;
-	output	[8:0]  rdusedw;
+	output	[9:0]  rdusedw;
 	output	  wrempty;
 	output	  wrfull;
-	output	[8:0]  wrusedw;
+	output	[9:0]  wrusedw;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_off
 `endif
@@ -76,17 +76,17 @@ module cdc_fifo (
 	wire [7:0] sub_wire0;
 	wire  sub_wire1;
 	wire  sub_wire2;
-	wire [8:0] sub_wire3;
+	wire [9:0] sub_wire3;
 	wire  sub_wire4;
 	wire  sub_wire5;
-	wire [8:0] sub_wire6;
+	wire [9:0] sub_wire6;
 	wire [7:0] q = sub_wire0[7:0];
 	wire  rdempty = sub_wire1;
 	wire  rdfull = sub_wire2;
-	wire [8:0] rdusedw = sub_wire3[8:0];
+	wire [9:0] rdusedw = sub_wire3[9:0];
 	wire  wrempty = sub_wire4;
 	wire  wrfull = sub_wire5;
-	wire [8:0] wrusedw = sub_wire6[8:0];
+	wire [9:0] wrusedw = sub_wire6[9:0];
 
 	dcfifo	dcfifo_component (
 				.aclr (aclr),
@@ -105,11 +105,11 @@ module cdc_fifo (
 				.eccstatus ());
 	defparam
 		dcfifo_component.intended_device_family = "Cyclone IV E",
-		dcfifo_component.lpm_numwords = 512,
+		dcfifo_component.lpm_numwords = 1024,
 		dcfifo_component.lpm_showahead = "OFF",
 		dcfifo_component.lpm_type = "dcfifo",
 		dcfifo_component.lpm_width = 8,
-		dcfifo_component.lpm_widthu = 9,
+		dcfifo_component.lpm_widthu = 10,
 		dcfifo_component.overflow_checking = "ON",
 		dcfifo_component.rdsync_delaypipe = 5,
 		dcfifo_component.read_aclr_synch = "ON",
@@ -130,7 +130,7 @@ endmodule
 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
 // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
 // Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "512"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
 // Retrieval info: PRIVATE: Empty NUMERIC "1"
 // Retrieval info: PRIVATE: Full NUMERIC "1"
 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
@@ -158,11 +158,11 @@ endmodule
 // Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
 // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
 // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
 // Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
@@ -177,12 +177,12 @@ endmodule
 // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
 // Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
 // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]"
 // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
 // Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
 // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
 // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
+// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
 // Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
@@ -192,10 +192,10 @@ endmodule
 // Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
 // Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
 // Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL cdc_fifo.v TRUE
 // Retrieval info: GEN_FILE: TYPE_NORMAL cdc_fifo.inc FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL cdc_fifo.cmp FALSE

fpga/max80.qpf

@@ -19,14 +19,14 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 20:04:26  January 09, 2022
+# Date created = 20:11:23  January 09, 2022
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "20:04:26  January 09, 2022"
+DATE = "20:11:23  January 09, 2022"
 
 # Revisions
 
-PROJECT_REVISION = "v1"
 PROJECT_REVISION = "v2"
+PROJECT_REVISION = "v1"

fpga/usb/usb_serial/src_v/usb_cdc_core.sv

@@ -90,7 +90,7 @@ module usb_cdc_channel
    input	 start_of_frame_s
    );
 
-   localparam fifo_size   = 511;
+   localparam fifo_size   = 1024;
    localparam fifo_bits   = $clog2(fifo_size);
    localparam packet_bits = 6;
    localparam packet_size = 1 << packet_bits;
@@ -218,7 +218,7 @@ module usb_cdc_channel
    always @(negedge rst_n or posedge sys_clk)
      if (~rst_n)
        begin
-	  water_ctl    <= 16'h8787 & water_ctl_mask;
+	  water_ctl    <= 16'hc3c3 & water_ctl_mask;
 	  irq_mask     <= 16'b0;
 	  recv_break_q <= 1'b0;
        end