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max80_fw
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More clock tree changes; fix rng oscillator sources

H. Peter Anvin 3 years ago
parent
e170347f76
commit
3dfb6626a1
14 changed files with 194 additions and 150 deletions
Split View Show Diff Stats
  1. 1 1
      fpga/abcbus.sv
  2. 13 15
      fpga/ip/pll2.v
  3. 56 28
      fpga/ip/pll3.v
  4. 13 13
      fpga/ip/pll4.v
  5. 2 1
      fpga/max80.qsf
  6. 8 7
      fpga/max80.sdc
  7. 46 36
      fpga/max80.sv
  8. BIN
      fpga/output_files/max80.jbc
  9. BIN
      fpga/output_files/max80.jic
  10. BIN
      fpga/output_files/max80.pof
  11. BIN
      fpga/output_files/max80.sof
  12. 10 11
      fpga/rng.sv
  13. 10 10
      fpga/sysclock.sv
  14. 35 28
      fpga/usb/usb.sv

+ 1 - 1
fpga/abcbus.sv
View File 

@@ -16,6 +16,7 @@ module abcbus (
 
 
 	       // ABC bus
 
 	       input		 abc_clk,
 
+	       output		 abc_clk_s,
 
 	       input [15:0]	 abc_a,
 
 	       inout [7:0]	 abc_d,
 
 	       output reg	 abc_d_oe,
 
@@ -70,7 +71,6 @@ module abcbus (
 
 
    // Synchronizer for ABC-bus input signals; also changes
 
    // the sense to positive logic where applicable
 
-   wire	       abc_clk_s;
 
    wire [15:0] abc_a_s;
 
    wire [7:0]  abc_di;
 
    wire        abc_rst_s;

+ 13 - 15
fpga/ip/pll2.v
View File 

@@ -103,17 +103,16 @@ module pll2 (
 
 				.vcooverrange (),
 
 				.vcounderrange ());
 
 	defparam
 
-		altpll_component.bandwidth_type = "LOW",
 
+		altpll_component.bandwidth_type = "AUTO",
 
 		altpll_component.clk0_divide_by = 1,
 
 		altpll_component.clk0_duty_cycle = 50,
 
-		altpll_component.clk0_multiply_by = 1,
 
+		altpll_component.clk0_multiply_by = 7,
 
 		altpll_component.clk0_phase_shift = "0",
 
-		altpll_component.compensate_clock = "CLK0",
 
 		altpll_component.inclk0_input_frequency = 20833,
 
 		altpll_component.intended_device_family = "Cyclone IV E",
 
 		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll2",
 
 		altpll_component.lpm_type = "altpll",
 
-		altpll_component.operation_mode = "NORMAL",
 
+		altpll_component.operation_mode = "NO_COMPENSATION",
 
 		altpll_component.pll_type = "AUTO",
 
 		altpll_component.port_activeclock = "PORT_UNUSED",
 
 		altpll_component.port_areset = "PORT_USED",
 
@@ -170,12 +169,12 @@ endmodule
 
 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
 
 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
 
 // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
 
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
 
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
 
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
 
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
 
 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
 
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
 
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
 
 // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 
@@ -183,7 +182,7 @@ endmodule
 
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
 
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "336.000000"
 
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
 
@@ -206,9 +205,9 @@ endmodule
 
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
 
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
 
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
 
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "336.00000000"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 
@@ -246,16 +245,15 @@ endmodule
 
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
 
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
 
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
 
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
 
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
 
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
 
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
 
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
 
 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
 
 // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
 
 // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"

+ 56 - 28
fpga/ip/pll3.v
View File 

@@ -44,6 +44,7 @@ module pll3 (
 
 	c1,
 
 	c2,
 
 	c3,
 
+	c4,
 
 	locked);
 
 
 	input	  areset;
 
@@ -52,6 +53,7 @@ module pll3 (
 
 	output	  c1;
 
 	output	  c2;
 
 	output	  c3;
 
+	output	  c4;
 
 	output	  locked;
 
 `ifndef ALTERA_RESERVED_QIS
 
 // synopsys translate_off
 
@@ -62,8 +64,9 @@ module pll3 (
 
 `endif
 
 
 	wire [4:0] sub_wire0;
 
-	wire  sub_wire5;
 
-	wire [0:0] sub_wire8 = 1'h0;
 
+	wire  sub_wire6;
 
+	wire [0:0] sub_wire9 = 1'h0;
 
+	wire [4:4] sub_wire5 = sub_wire0[4:4];
 
 	wire [3:3] sub_wire4 = sub_wire0[3:3];
 
 	wire [2:2] sub_wire3 = sub_wire0[2:2];
 
 	wire [1:1] sub_wire2 = sub_wire0[1:1];
 
@@ -72,15 +75,16 @@ module pll3 (
 
 	wire  c1 = sub_wire2;
 
 	wire  c2 = sub_wire3;
 
 	wire  c3 = sub_wire4;
 
-	wire  locked = sub_wire5;
 
-	wire  sub_wire6 = inclk0;
 
-	wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
 
+	wire  c4 = sub_wire5;
 
+	wire  locked = sub_wire6;
 
+	wire  sub_wire7 = inclk0;
 
+	wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
 
 
 	altpll	altpll_component (
 
 				.areset (areset),
 
-				.inclk (sub_wire7),
 
+				.inclk (sub_wire8),
 
 				.clk (sub_wire0),
 
-				.locked (sub_wire5),
 
+				.locked (sub_wire6),
 
 				.activeclock (),
 
 				.clkbad (),
 
 				.clkena ({6{1'b1}}),
 
@@ -118,21 +122,25 @@ module pll3 (
 
 		altpll_component.bandwidth_type = "AUTO",
 
 		altpll_component.clk0_divide_by = 2,
 
 		altpll_component.clk0_duty_cycle = 50,
 
-		altpll_component.clk0_multiply_by = 7,
 
-		altpll_component.clk0_phase_shift = "372",
 
+		altpll_component.clk0_multiply_by = 1,
 
+		altpll_component.clk0_phase_shift = "930",
 
 		altpll_component.clk1_divide_by = 2,
 
 		altpll_component.clk1_duty_cycle = 50,
 
-		altpll_component.clk1_multiply_by = 7,
 
+		altpll_component.clk1_multiply_by = 1,
 
 		altpll_component.clk1_phase_shift = "0",
 
 		altpll_component.clk2_divide_by = 4,
 
 		altpll_component.clk2_duty_cycle = 50,
 
-		altpll_component.clk2_multiply_by = 7,
 
+		altpll_component.clk2_multiply_by = 1,
 
 		altpll_component.clk2_phase_shift = "0",
 
 		altpll_component.clk3_divide_by = 5,
 
 		altpll_component.clk3_duty_cycle = 50,
 
-		altpll_component.clk3_multiply_by = 14,
 
+		altpll_component.clk3_multiply_by = 2,
 
 		altpll_component.clk3_phase_shift = "0",
 
-		altpll_component.inclk0_input_frequency = 20833,
 
+		altpll_component.clk4_divide_by = 7,
 
+		altpll_component.clk4_duty_cycle = 50,
 
+		altpll_component.clk4_multiply_by = 1,
 
+		altpll_component.clk4_phase_shift = "0",
 
+		altpll_component.inclk0_input_frequency = 2976,
 
 		altpll_component.intended_device_family = "Cyclone IV E",
 
 		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll3",
 
 		altpll_component.lpm_type = "altpll",
 
@@ -167,7 +175,7 @@ module pll3 (
 
 		altpll_component.port_clk1 = "PORT_USED",
 
 		altpll_component.port_clk2 = "PORT_USED",
 
 		altpll_component.port_clk3 = "PORT_USED",
 
-		altpll_component.port_clk4 = "PORT_UNUSED",
 
+		altpll_component.port_clk4 = "PORT_USED",
 
 		altpll_component.port_clk5 = "PORT_UNUSED",
 
 		altpll_component.port_clkena0 = "PORT_UNUSED",
 
 		altpll_component.port_clkena1 = "PORT_UNUSED",
 
@@ -208,14 +216,17 @@ endmodule
 
 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
 
 // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
 
 // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "5"
 
+// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "7"
 
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 
 // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 
 // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
 
+// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
 
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "168.000000"
 
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "168.000000"
 
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "84.000000"
 
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "134.399994"
 
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "48.000000"
 
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
 
@@ -223,7 +234,7 @@ endmodule
 
 // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
 
 // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
 
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
 
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "336.000"
 
 // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
 
 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
 
 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
 
@@ -239,39 +250,47 @@ endmodule
 
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
 
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
 
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
 
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
 
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 
 // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 
 // Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
 
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
 
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
 
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "7"
 
-// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "14"
 
+// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
 
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
 
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
 
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
 
+// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
 
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "168.00000000"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "168.00000000"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "84.00000000"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "134.40000000"
 
+// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "48.00000000"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
 
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
 
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
 
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
 
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
 
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "22.50000000"
 
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "56.25000000"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
 
+// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
 
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
 
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
 
@@ -297,6 +316,7 @@ endmodule
 
 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 
 // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
 
 // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
 
+// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
 
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 
@@ -304,31 +324,37 @@ endmodule
 
 // Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 
 // Retrieval info: PRIVATE: USE_CLK2 STRING "1"
 
 // Retrieval info: PRIVATE: USE_CLK3 STRING "1"
 
+// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
 
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
 
 // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 
 // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
 
 // Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
 
+// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
 
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
 
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
 
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "372"
 
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
 
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "930"
 
 // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
 
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
 
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
 
 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 
 // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
 
 // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
 
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "7"
 
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
 
 // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
 
 // Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5"
 
 // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
 
-// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "14"
 
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
 
 // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
 
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
 
+// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "7"
 
+// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
 
+// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "1"
 
+// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
 
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "2976"
 
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
 
 // Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
 
@@ -362,7 +388,7 @@ endmodule
 
 // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 
 // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
 
 // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
 
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
 
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
 
 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
 
 // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
 
 // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
 
@@ -382,6 +408,7 @@ endmodule
 
 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 
 // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 
 // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
 
+// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
 
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
 
 // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 
@@ -391,6 +418,7 @@ endmodule
 
 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 
 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
 
 // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 
+// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
 
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll3.v TRUE
 
 // Retrieval info: GEN_FILE: TYPE_NORMAL pll3.ppf TRUE

+ 13 - 13
fpga/ip/pll4.v
View File 

@@ -107,17 +107,17 @@ module pll4 (
 
 				.vcooverrange (),
 
 				.vcounderrange ());
 
 	defparam
 
-		altpll_component.bandwidth_type = "LOW",
 
+		altpll_component.bandwidth_type = "AUTO",
 
 		altpll_component.clk0_divide_by = 6,
 
 		altpll_component.clk0_duty_cycle = 50,
 
-		altpll_component.clk0_multiply_by = 35,
 
+		altpll_component.clk0_multiply_by = 5,
 
 		altpll_component.clk0_phase_shift = "0",
 
 		altpll_component.clk1_divide_by = 6,
 
 		altpll_component.clk1_duty_cycle = 50,
 
-		altpll_component.clk1_multiply_by = 7,
 
+		altpll_component.clk1_multiply_by = 1,
 
 		altpll_component.clk1_phase_shift = "0",
 
 		altpll_component.compensate_clock = "CLK0",
 
-		altpll_component.inclk0_input_frequency = 20833,
 
+		altpll_component.inclk0_input_frequency = 2976,
 
 		altpll_component.intended_device_family = "Cyclone IV E",
 
 		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll4",
 
 		altpll_component.lpm_type = "altpll",
 
@@ -178,8 +178,8 @@ endmodule
 
 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
 
 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
 
 // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
 
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
 
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
 
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
 
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
 
 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
 
@@ -202,7 +202,7 @@ endmodule
 
 // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
 
 // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
 
 // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
 
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
 
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "336.000"
 
 // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
 
 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
 
 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
 
@@ -219,8 +219,8 @@ endmodule
 
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "35"
 
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
 
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
 
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
 
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "280.00000000"
 
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "56.00000000"
 
@@ -268,17 +268,17 @@ endmodule
 
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 
-// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
 
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
 
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "35"
 
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
 
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 
 // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6"
 
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
 
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
 
 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
 
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "2976"
 
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
 
 // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"

+ 2 - 1
fpga/max80.qsf
View File 

@@ -246,7 +246,6 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[0]
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[0]
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[1]
 
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[2]
 
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
 
 set_global_assignment -name SYSTEMVERILOG_FILE rng.sv
 
 set_global_assignment -name VERILOG_FILE ip/int_osc/synthesis/int_osc.v
 
@@ -295,3 +294,5 @@ set_global_assignment -name SOURCE_FILE max80.pins
 
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 
 set_global_assignment -name VERILOG_FILE ip/fifo.v
 
 set_global_assignment -name VERILOG_FILE ip/ddufifo.v
 
+
 
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

+ 8 - 7
fpga/max80.sdc
View File 

@@ -51,22 +51,23 @@ set_multicycle_path -from [all_clocks] -to $synchro_inputs \
 
 
 # -------- SDRAM I/O constraints --------
 
 
-#set sr_data_out [remove_from_collection [get_ports sr_*] sr_clk]
 
-#set sr_data_in  [get_ports sr_dq\[*\]]
 
-#set_max_skew -to $sr_data_out 0.100ns
 
-#set_input_delay  -clock $sdram_clk 0.500ns  $sr_data_in
 
+set sr_data_out [remove_from_collection [get_ports sr_*] sr_clk]
 
+set sr_data_in  [get_ports sr_dq\[*\]]
 
+set_max_skew -to $sr_data_out 0.100ns
 
+set_input_delay  -clock $sdram_clk 0.500ns  $sr_data_in
 
 
 #set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
 
 #    -start -setup 2
 
 #set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
 
 #    -start -hold 0
 
 
-# -------- SDRAM multicycle paths (ready is retarded) --------
 
+# -------- SDRAM multicycle paths --------
 
 
+# sdram_mem_ready is deferred by one sys_clk
 
 set_multicycle_path -from [get_registers {dram_port:cpu_dram_port|rd[*]}] \
 
-    -to $sys_clk -setup 2
 
+    -to $sys_clk -start -setup 3
 
 set_multicycle_path -from [get_registers {dram_port:cpu_dram_port|rd[*]}] \
 
-    -to $sys_clk -hold 2
 
+    -to $sys_clk -start -hold 2
 
 
 # -------- SPI ROM multicycle paths --------

+ 46 - 36
fpga/max80.sv
View File 

@@ -134,48 +134,48 @@ module max80 (
 
    //  feeding into hardware PLL2 and PLL4. The SDRAM clock output
 
    //  is a dedicated clock out pin from PLL3.
 
    //
 
-   //  sys_clk and sdram_clk are very closely tied; the logic
 
-   //  assumes in a very large number of places that
 
-   //  sdram_clk = sys_clk x 2 and that they are synchronous. Therefore
 
-   //  they better come out of the same PLL!
 
+   //  The following sets of clocks are closely tied and expected to
 
+   //  be synchronous, and therefore should come from the same PLL each;
 
+   //  furthermore, the design strictly assumes the ratios specified.
 
+   //
 
+   //  sdram_clk, sys_clk    - 2:1 ratio
 
+   //  vid_hdmiclk, vid_clk  - 5:1 ratio
 
    //
 
-   wire	    sdram_clk;		// 168 MHz SDRAM clock
 
-   wire	    sys_clk;		//  84 MHz System clock
 
-   wire	    vid_clk;		//  56 MHz Video pixel clock
 
-   wire	    vid_hdmiclk;	// 280 MHz HDMI serializer clock = vid_clk x 5
 
-   wire     flash_clk;		// 134 MHz Serial flash ROM clock
 
-   wire     usb_clk;		//  48 MHz USB clock
 
-
 
-   wire     pll23_clk;		//  48 MHz PLL2 -> PLL3 clock transfer
 
-   assign   usb_clk = pll23_clk;
 
-
 
    reg	    reset_cmd_q = 1'b0;
 
    wire     reset_cmd;
 
 
+   wire     master_clk;		// 336 MHz internal master clock
 
    pll2 pll2 (
 
 	      .areset ( reset_cmd_q ),
 
 	      .locked ( pll_locked[2] ),
 
 
 	      .inclk0 ( clock_48 ),
 
-	      .c0     ( pll23_clk )
 
+	      .c0     ( master_clk )
 
 	      );
 
 
+   wire	    sdram_clk;		// 168 MHz SDRAM clock
 
+   wire	    sys_clk;		//  84 MHz System clock
 
+   wire     flash_clk;		// 134 MHz Serial flash ROM clock
 
+   wire     usb_clk;		//  48 MHz USB clock
 
    pll3 pll3 (
 
-	      .areset ( reset_cmd_q | ~pll_locked[2] ),
 
+	      .areset ( ~pll_locked[2] ),
 
 	      .locked ( pll_locked[3] ),
 
 
-	      .inclk0 ( pll23_clk ),
 
+	      .inclk0 ( master_clk ),
 
 	      .c0     ( sr_clk ),	// Output to clock pin (phase shift)
 
 	      .c1     ( sdram_clk ),	// Internal logic/buffer data clock
 
 	      .c2     ( sys_clk ),
 
-	      .c3     ( flash_clk )
 
+	      .c3     ( flash_clk ),
 
+	      .c4     ( usb_clk )
 
 	      );
 
 
+   wire	    vid_clk;		//  56 MHz Video pixel clock
 
+   wire	    vid_hdmiclk;	// 280 MHz HDMI serializer clock = vid_clk x 5
 
    pll4 pll4 (
 
-	      .areset ( reset_cmd_q ),
 
+	      .areset ( ~pll_locked[2] ),
 
 	      .locked ( pll_locked[4] ),
 
 
-	      .inclk0 ( clock_48 ),
 
+	      .inclk0 ( master_clk ),
 
 	      .c0     ( vid_hdmiclk ),
 
 	      .c1     ( vid_clk )
 
 	      );
 
@@ -332,6 +332,8 @@ module max80 (
 
    //
 
    // ABC-bus interface
 
    //
 
+   wire        abc_clk_s;	// abc_clk synchronous to sys_clk
 
+
 
    abcbus abcbus (
 
 		  .rst_n ( rst_n ),
 
 		  .sys_clk ( sys_clk ),
 
@@ -348,6 +350,7 @@ module max80 (
 
 		  .irq       ( iodev_irq_abc ),
 
 
 		  .abc_clk   ( abc_clk ),
 
+		  .abc_clk_s ( abc_clk_s ),
 
 		  .abc_a     ( abc_a ),
 
 		  .abc_d     ( abc_d ),
 
 		  .abc_d_oe  ( abc_d_oe ),
 
@@ -565,11 +568,12 @@ module max80 (
 
    assign sysreg_rdata[2] = { 29'b0, led_q };
 
 
    // Random number generator
 
+   wire        rtc_clk_s;
 
    rng #(.nclocks(2), .width(32)) rng
 
      (
 
       .sys_clk ( sys_clk ),
 
       .q       ( sysreg_rdata[4] ),
 
-      .clocks  ( { ~rtc_32khz, abc_clk } ),
 
+      .clocks  ( { rtc_clk_s, abc_clk_s } ),
 
       .rngio   ( rngio )
 
       );
 
 
@@ -674,24 +678,30 @@ module max80 (
 
 	   );
 
    assign sd_dat[2:1] = 2'bzz;
 
 
-   // System local clock (not an RTC, but settable from one)
 
-   // Also provides a periodic interrupt (set to 32 Hz)
 
-   wire clk_32kHz = ~rtc_32khz;
 
+   //
 
+   // System local clock (not an RTC per se, but settable from one);
 
+   // also provides a periodic interrupt, currently set to 32 Hz.
 
+   //
 
+   // The RTC 32.768 kHz output is open drain, so use the negative
 
+   // edge for clocking.
 
+   //
 
+   wire clk_32kHz = ~rtc_32khz;	// Inverted
 
 
    sysclock #(.PERIODIC_HZ_LG2 ( TIMER_SHIFT ))
 
    sysclock (
 
-		      .rst_n ( rst_n ),
 
-		      .sys_clk ( sys_clk ),
 
-		      .rtc_clk ( clk_32kHz ),
 
-
 
-		      .wdata   ( cpu_mem_wdata ),
 
-		      .rdata   ( iodev_rdata_sysclock ),
 
-		      .valid   ( iodev_valid_sysclock ),
 
-		      .wstrb   ( cpu_mem_wstrb ),
 
-		      .addr    ( cpu_mem_addr[2] ),
 
-
 
-		      .periodic ( iodev_irq_sysclock )
 
-		      );
 
+	     .rst_n     ( rst_n ),
 
+	     .sys_clk   ( sys_clk ),
 
+	     .rtc_clk   ( clk_32kHz ),
 
+	     .rtc_clk_s ( rtc_clk_s ),
 
+
 
+	     .wdata   ( cpu_mem_wdata ),
 
+	     .rdata   ( iodev_rdata_sysclock ),
 
+	     .valid   ( iodev_valid_sysclock ),
 
+	     .wstrb   ( cpu_mem_wstrb ),
 
+	     .addr    ( cpu_mem_addr[2] ),
 
+
 
+	     .periodic ( iodev_irq_sysclock )
 
+	     );
 
 
    // SPI bus to ESP32; using the sdcard IP as a SPI master for now at
 
    // least...

BIN
fpga/output_files/max80.jbc
View File


BIN
fpga/output_files/max80.jic
View File


BIN
fpga/output_files/max80.pof
View File


BIN
fpga/output_files/max80.sof
View File


+ 10 - 11
fpga/rng.sv
View File 

@@ -15,11 +15,10 @@ module rng
 
     output [width-1:0] q,
 
 
      // Randomness inputs
 
-    input [nclocks-1:0] clocks, // Asynchronous clocks
 
-    inout [2:0]        rngio		// Unconnected pins with pullups
 
+    input [nclocks-1:0] clocks,		// Random input synchronized to sys_clk
 
+    (* keep = 1 *) inout [2:0] rngio	// Unconnected pins with pullups
 
     );
 
 
-
 
    wire		 int_clock;	// Internal oscillator clock
 
 
    // Internal on-chip oscillator
 
@@ -29,18 +28,18 @@ module rng
 
       .oscena ( 1'b1 )
 
       );
 
 
-   // De facto RC oscillator using the rngio pins
 
-   assign rngio[0] = rngio[2] ? 1'b0 : 1'bz;
 
-   assign rngio[1] = rngio[0] ? 1'b0 : 1'bz;
 
-   assign rngio[2] = rngio[1] ? 1'b0 : 1'bz;
 
+   // Ring oscillator using the rngio pins
 
+   assign rngio[0] = ~rngio[2];
 
+   assign rngio[1] = ~rngio[0];
 
+   assign rngio[2] = ~rngio[1];
 
 
-   wire [nclocks+1:0] sclocks;
 
+   wire [1:0] sclocks;		// Internally generated clocks
 
 
-   synchronizer #(.width(nclocks+2)) synchro
 
+   synchronizer #(.width(2)) synchro
 
      (
 
       .rst_n ( 1'b1 ),
 
       .clk ( sys_clk ),
 
-      .d ( { clocks, rngio[0], int_clk } ),
 
+      .d ( { rngio[0], int_clock } ),
 
       .q ( sclocks )
 
       );
 
 
@@ -57,7 +56,7 @@ module rng
 
    reg [lsfr_max:0] lsfr;
 
 
    always @(posedge sys_clk)
 
-     lsfr <= {lsfr[lsfr_max-1:0], ^sclocks} ^
 
+     lsfr <= {lsfr[lsfr_max-1:0], ^{sclocks, clocks}} ^
 
 	     {{(lsfr_max+1){lsfr[poly_width-1]}} & poly};
 
 
    assign q = lsfr[width-1:0];

+ 10 - 10
fpga/sysclock.sv
View File 

@@ -15,6 +15,7 @@ module sysclock (
 
 		 input		   rst_n,
 
 		 input		   sys_clk,
 
 		 input		   rtc_clk,
 
+		 output		   rtc_clk_s,
 
 
 		 input		   valid,
 
 		 input		   addr,
 
@@ -27,21 +28,20 @@ module sysclock (
 
 
    parameter PERIODIC_HZ_LG2 = 5;
 
 
-   wire		rtc_clk_sync;
 
+   synchronizer synchro (
 
+			 .rst_n ( 1'b1 ),
 
+			 .clk ( sys_clk ),
 
+			 .d ( rtc_clk ),
 
+			 .q ( rtc_clk_s )
 
+			 );
 
+
 
    reg		rtc_clk_q;
 
    reg		rtc_clk_stb;
 
 
-   synchronizer rtc_sync (
 
-			  .rst_n ( 1'b1 ),
 
-			  .clk ( sys_clk ),
 
-			  .d ( rtc_clk ),
 
-			  .q ( rtc_clk_sync )
 
-			  );
 
-
 
    always @(posedge sys_clk)
 
      begin
 
-	rtc_clk_q <= rtc_clk_sync;
 
-	rtc_clk_stb <= rtc_clk_sync & ~rtc_clk_q;
 
+	rtc_clk_q   <= rtc_clk_s;
 
+	rtc_clk_stb <= rtc_clk_s & ~rtc_clk_q;
 
      end
 
 
    function logic [4:0] maxday(input [3:0] mon,

+ 35 - 28
fpga/usb/usb.sv
View File 

@@ -8,7 +8,7 @@
 
 module max80_usb (
 
 		  input  rst_n,
 
 		  input  clock48,
 
-		  
+
 
 		  output tty_rxd,
 
 		  input  tty_txd,
 
 
@@ -20,38 +20,45 @@ module max80_usb (
 
    //
 
    // UTMI interface to PHY
 
    //
 
-   wire [7:0] 		 utmi_data_out;
 
-   wire [1:0] 		 utmi_op_mode;
 
-   wire [1:0] 		 utmi_xcvrselect;
 
-   wire 		 utmi_termselect;
 
-   wire 		 utmi_dppulldown;
 
-   wire 		 utmi_dmpulldown;
 
-   wire [7:0] 		 utmi_data_in;
 
-   wire 		 utmi_txvalid;
 
-   wire 		 utmi_txready;
 
-   wire 		 utmi_rxvalid;
 
-   wire 		 utmi_rxactive;
 
-   wire 		 utmi_rxerror;
 
-   wire [1:0] 		 utmi_linestate;
 
+   wire [7:0]		 utmi_data_out;
 
+   wire [1:0]		 utmi_op_mode;
 
+   wire [1:0]		 utmi_xcvrselect;
 
+   wire			 utmi_termselect;
 
+   wire			 utmi_dppulldown;
 
+   wire			 utmi_dmpulldown;
 
+   wire [7:0]		 utmi_data_in;
 
+   wire			 utmi_txvalid;
 
+   wire			 utmi_txready;
 
+   wire			 utmi_rxvalid;
 
+   wire			 utmi_rxactive;
 
+   wire			 utmi_rxerror;
 
+   wire [1:0]		 utmi_linestate;
 
 
    //
 
    // USB hardware interface to PHY
 
    //
 
-   wire 		 usb_rx_rcv   = usb_dp & ~usb_dn;
 
-   wire 		 usb_rx_dp    = usb_dp;
 
-   wire 		 usb_rx_dn    = usb_dn;
 
-   wire 		 usb_tx_dp;
 
-   wire 		 usb_tx_dn;
 
-   wire 		 usb_tx_oen;
 
-   wire 		 usb_en;
 
-
 
-   assign usb_dp = ( rst_n & ~usb_tx_oen ) ? usb_tx_dp : 1'bz;
 
-   assign usb_dn = ( rst_n & ~usb_tx_oen ) ? usb_tx_dn : 1'bz;
 
-   assign usb_pu = ( rst_n & usb_en )      ? 1'b1 : 1'bz;
 
+   wire			 usb_rx_rcv   = usb_dp & ~usb_dn;
 
+   wire			 usb_rx_dp    = usb_dp;
 
+   wire			 usb_rx_dn    = usb_dn;
 
+   wire			 usb_tx_dp;
 
+   wire			 usb_tx_dn;
 
+   wire			 usb_tx_oen;
 
+   wire			 usb_en;
 
+
 
+   //
 
+   // Reset and I/O pins
 
+   //
 
+   reg			 usb_rst_n;
 
+   always @(negedge rst_n or posedge clock48 )
 
+     usb_rst_n <= rst_n;	// Reset synchronized with the usb clock
 
+
 
+   assign usb_dp = ( usb_rst_n & ~usb_tx_oen ) ? usb_tx_dp : 1'bz;
 
+   assign usb_dn = ( usb_rst_n & ~usb_tx_oen ) ? usb_tx_dn : 1'bz;
 
+   assign usb_pu = ( usb_rst_n & usb_en )      ? 1'b1 : 1'bz;
 
 
    usb_fs_phy usb_phy (
 
 		       .clk_i ( clock48 ),
 
-		       .rst_i ( ~rst_n ),
 
+		       .rst_i ( ~usb_rst_n ),
 
 
 		       .utmi_data_out_i ( utmi_data_out ),
 
 		       .utmi_txvalid_i  ( utmi_txvalid ),
 
@@ -79,11 +86,11 @@ module max80_usb (
 
 		       .usb_reset_detect_o ( ),
 
 		       .usb_en_o           ( usb_en )
 
 		       );
 
-   
+
 
    usb_cdc_top #(.BAUDRATE(115200))
 
    usb_serial (
 
 	       .clk_i             ( clock48 ),
 
-	       .rst_i             ( ~rst_n ),
 
+	       .rst_i             ( ~usb_rst_n ),
 
 
 	       .utmi_data_out_o   ( utmi_data_out ),
 
 	       .utmi_txvalid_o    ( utmi_txvalid ),