video: explicitly make the clock a "data" output

fpga/ip/hdmitx.v

@@ -47,20 +47,20 @@ module hdmitx (
 	tx_outclock);
 
 	input	  pll_areset;
-	input	[29:0]  tx_in;
+	input	[39:0]  tx_in;
 	input	  tx_inclock;
 	output	  tx_coreclock;
 	output	  tx_locked;
-	output	[2:0]  tx_out;
+	output	[3:0]  tx_out;
 	output	  tx_outclock;
 
 	wire  sub_wire0;
 	wire  sub_wire1;
-	wire [2:0] sub_wire2;
+	wire [3:0] sub_wire2;
 	wire  sub_wire3;
 	wire  tx_coreclock = sub_wire0;
 	wire  tx_locked = sub_wire1;
-	wire [2:0] tx_out = sub_wire2[2:0];
+	wire [3:0] tx_out = sub_wire2[3:0];
 	wire  tx_outclock = sub_wire3;
 
 	altlvds_tx	ALTLVDS_TX_component (
@@ -93,7 +93,7 @@ module hdmitx (
 		ALTLVDS_TX_component.lpm_hint = "CBX_MODULE_PREFIX=hdmitx",
 		ALTLVDS_TX_component.lpm_type = "altlvds_tx",
 		ALTLVDS_TX_component.multi_clock = "OFF",
-		ALTLVDS_TX_component.number_of_channels = 3,
+		ALTLVDS_TX_component.number_of_channels = 4,
 		ALTLVDS_TX_component.outclock_alignment = "EDGE_ALIGNED",
 		ALTLVDS_TX_component.outclock_divide_by = 10,
 		ALTLVDS_TX_component.outclock_duty_cycle = 50,
@@ -125,7 +125,7 @@ endmodule
 // Retrieval info: PRIVATE: CNX_DESER_FACTOR NUMERIC "10"
 // Retrieval info: PRIVATE: CNX_EXT_PLL STRING "OFF"
 // Retrieval info: PRIVATE: CNX_LE_SERDES STRING "ON"
-// Retrieval info: PRIVATE: CNX_NUM_CHANNEL NUMERIC "3"
+// Retrieval info: PRIVATE: CNX_NUM_CHANNEL NUMERIC "4"
 // Retrieval info: PRIVATE: CNX_OUTCLOCK_DIVIDE_BY NUMERIC "10"
 // Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "1"
 // Retrieval info: PRIVATE: CNX_PLL_FREQ STRING "56.00"
@@ -158,7 +158,7 @@ endmodule
 // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_tx"
 // Retrieval info: CONSTANT: MULTI_CLOCK STRING "OFF"
-// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "3"
+// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
 // Retrieval info: CONSTANT: OUTCLOCK_ALIGNMENT STRING "EDGE_ALIGNED"
 // Retrieval info: CONSTANT: OUTCLOCK_DIVIDE_BY NUMERIC "10"
 // Retrieval info: CONSTANT: OUTCLOCK_DUTY_CYCLE NUMERIC "50"
@@ -178,14 +178,14 @@ endmodule
 // Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
 // Retrieval info: USED_PORT: tx_coreclock 0 0 0 0 OUTPUT NODEFVAL "tx_coreclock"
 // Retrieval info: CONNECT: tx_coreclock 0 0 0 0 @tx_coreclock 0 0 0 0
-// Retrieval info: USED_PORT: tx_in 0 0 30 0 INPUT NODEFVAL "tx_in[29..0]"
-// Retrieval info: CONNECT: @tx_in 0 0 30 0 tx_in 0 0 30 0
+// Retrieval info: USED_PORT: tx_in 0 0 40 0 INPUT NODEFVAL "tx_in[39..0]"
+// Retrieval info: CONNECT: @tx_in 0 0 40 0 tx_in 0 0 40 0
 // Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT NODEFVAL "tx_inclock"
 // Retrieval info: CONNECT: @tx_inclock 0 0 0 0 tx_inclock 0 0 0 0
 // Retrieval info: USED_PORT: tx_locked 0 0 0 0 OUTPUT NODEFVAL "tx_locked"
 // Retrieval info: CONNECT: tx_locked 0 0 0 0 @tx_locked 0 0 0 0
-// Retrieval info: USED_PORT: tx_out 0 0 3 0 OUTPUT NODEFVAL "tx_out[2..0]"
-// Retrieval info: CONNECT: tx_out 0 0 3 0 @tx_out 0 0 3 0
+// Retrieval info: USED_PORT: tx_out 0 0 4 0 OUTPUT NODEFVAL "tx_out[3..0]"
+// Retrieval info: CONNECT: tx_out 0 0 4 0 @tx_out 0 0 4 0
 // Retrieval info: USED_PORT: tx_outclock 0 0 0 0 OUTPUT NODEFVAL "tx_outclock"
 // Retrieval info: CONNECT: tx_outclock 0 0 0 0 @tx_outclock 0 0 0 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.v TRUE FALSE

fpga/video.sv

@@ -1,7 +1,7 @@
 module video (
 	      input	   rst_n,
 	      input	   vid_clk,
-	      input [1:0]  pll_locked,
+	      inout [1:0]  pll_locked,
 
 	      output [2:0] hdmi_d,
 	      output	   hdmi_clk,
@@ -119,9 +119,9 @@ module video (
    // order, but TMDS is LSB first. Thus, bit-reverse the data within
    // each channel.
    //
-   wire [29:0] hdmi_to_tx;	// TMDS data in the order hdmitx expects
+   wire [39:0] hdmi_to_tx;	// TMDS data in the order hdmitx expects
 
-   transpose #(.words( 3 ),
+   transpose #(.words( 4 ),
 	       .bits( 10 ),
 	       .reverse_b ( 1'b1 ),
 	       .reverse_w ( 1'b0 ),
@@ -131,7 +131,8 @@ module video (
 	       ) hdmitranspose
      (
       .clk ( vid_clk ),
-      .d ( { hdmi_tmds_data[2], hdmi_tmds_data[1], hdmi_tmds_data[0] } ),
+      .d ( { 10'b00000_11111, hdmi_tmds_data[2],
+	     hdmi_tmds_data[1], hdmi_tmds_data[0] } ),
       .q ( hdmi_to_tx )
       );
 
@@ -143,7 +144,7 @@ module video (
 		  .tx_inclock ( vid_clk ),
 		  .tx_coreclock ( vid_hdmiclk ), // Pixel clock in HDMI domain
 		  .tx_locked ( pll_locked[1] ),
-		  .tx_out ( hdmi_d ),
-		  .tx_outclock ( hdmi_clk )
+		  .tx_out ( { hdmi_clk, hdmi_d } ),
+		  .tx_outclock ( )
 		  );
 endmodule // video