Remove unused assignments; use a DDIO buffer for sr_clk

Using a DDIO buffer for sr_clk probably will give better jitter
performance. For EP4CE15 we could also use a secondary PLL here, but
it isn't clear that that is actually better.

ip/ddio_out.v

@@ -0,0 +1,112 @@
+// megafunction wizard: %ALTDDIO_OUT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: ALTDDIO_OUT 
+
+// ============================================================
+// File Name: ddio_out.v
+// Megafunction Name(s):
+// 			ALTDDIO_OUT
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module ddio_out (
+	aclr,
+	datain_h,
+	datain_l,
+	outclock,
+	dataout);
+
+	input	  aclr;
+	input	[0:0]  datain_h;
+	input	[0:0]  datain_l;
+	input	  outclock;
+	output	[0:0]  dataout;
+
+	wire [0:0] sub_wire0;
+	wire [0:0] dataout = sub_wire0[0:0];
+
+	altddio_out	ALTDDIO_OUT_component (
+				.aclr (aclr),
+				.datain_h (datain_h),
+				.datain_l (datain_l),
+				.outclock (outclock),
+				.dataout (sub_wire0),
+				.aset (1'b0),
+				.oe (1'b1),
+				.oe_out (),
+				.outclocken (1'b1),
+				.sclr (1'b0),
+				.sset (1'b0));
+	defparam
+		ALTDDIO_OUT_component.extend_oe_disable = "OFF",
+		ALTDDIO_OUT_component.intended_device_family = "Cyclone IV E",
+		ALTDDIO_OUT_component.invert_output = "OFF",
+		ALTDDIO_OUT_component.lpm_hint = "UNUSED",
+		ALTDDIO_OUT_component.lpm_type = "altddio_out",
+		ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
+		ALTDDIO_OUT_component.power_up_high = "OFF",
+		ALTDDIO_OUT_component.width = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
+// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
+// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
+// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
+// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
+// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
+// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
+// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.qip TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.bsf TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_inst.v TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_bb.v TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.inc TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.cmp TRUE TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.ppf TRUE FALSE
+// Retrieval info: LIB_FILE: altera_mf

max80.qsf

@@ -99,17 +99,11 @@ set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 5
 set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[2]
 set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[1]
 set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d[0]
-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_d
 set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_clk
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to "hdmi_clk(n)"
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[2]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to "hdmi_d[2](n)"
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[1]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to "hdmi_d[1](n)"
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d[0]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to "hdmi_d[0](n)"
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to hdmi_d
 set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
 set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
 set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 8
@@ -142,16 +136,14 @@ set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 3.3V
 set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS OUTPUT DRIVING GROUND"
 set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/postmodule.tcl"
 
-
-
-
+set_global_assignment -name VERILOG_FILE ip/ddio_out.v
 set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
 set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl
 set_global_assignment -name SOURCE_FILE max80jic.cof
 set_global_assignment -name VERILOG_FILE ip/hdmitx.v
 set_global_assignment -name VERILOG_FILE ip/pll.v
 set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
-set_global_assignment -name SYSTEMVERILOG_FILE syncho.sv
+set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
 set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
 set_global_assignment -name SDC_FILE max80.sdc
 set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
@@ -159,4 +151,4 @@ set_global_assignment -name SOURCE_FILE max80.pins
 set_global_assignment -name TCL_SCRIPT_FILE scripts/pins.tcl
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

max80.sv

@@ -128,7 +128,7 @@ module max80 (
    pll pll (
 	    .areset ( 1'b0 ),
 	    .inclk0 ( clock_48 ),
-	    .c0 ( sr_clk ),	// SDRAM clock  (96 MHz)
+	    .c0 ( sdram_clk ),	// SDRAM clock  (96 MHz)
 	    .c1 ( clk ),	// System clock (96 MHz)
 	    .c2 ( vid_clk ),	// Video pixel clock
 	    .locked ( pll_locked ),
@@ -150,6 +150,16 @@ module max80 (
 	  { rst_n, rst_ctr } <= rst_ctr + 1'b1;
        end
 
+     // SDRAM clock buffer - use a DDIO buffer for best performance
+     // For EP4CE15 only could use a secondary PLL here, but it
+     // isn't clear it buys us a whole lot.
+     ddio_out sr_clk_out (
+			  .datain_l ( 1'b0 ),
+			  .datain_h ( 1'b1 ),
+			  .outclock ( sdram_clk ),
+			  .dataout ( sr_clk )
+			  );
+
    // Unused device stubs - remove when used
 
    // HDMI - generate random data to give Quartus something to do
@@ -190,7 +200,8 @@ module max80 (
    // However, TMDS is LSB-first, and we have three TMDS words that
    // concatenate in word(channel)-major order.
    //
-   transpose #(.words(3), .bits(10), .reverse_b(1)) hdmitranspose
+   transpose #(.words(3), .bits(10), .reverse_b(1),
+	       .reg_d(0), .reg_q(0)) hdmitranspose
      (
       .d ( { hdmi_tmds[2], hdmi_tmds[1], hdmi_tmds[0] } ),
       .q ( hdmi_to_tx )

output_files/max80.map

@@ -10,7 +10,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 Notes:
 
-- Data checksum for this conversion is 0xF75F0113
+- Data checksum for this conversion is 0xF75EFFDB
 
 - All the addresses in this file are byte addresses