abcbus: make INT#, NMI#, RESIN# and WAIT#/RDY explicitly controllable

Add a control register to explicitly assert specific ABC-bus control
signals under program control.

fpga/abcbus.sv

@@ -147,11 +147,11 @@ module abcbus (
        ioselx <= { 1'b1, abc_di };
 
    // Open drain signals with optional MOSFETs
-   wire       abc_wait  = 1'b0;
-   wire       abc_resin = 1'b0;
-   wire       abc_int   = 1'b0;
-   wire       abc_nmi   = 1'b0;
-   wire       abc_xm    = 1'b0;
+   reg 	      abc_wait  = 1'b0;
+   reg 	      abc_int   = 1'b0;
+   reg 	      abc_nmi   = 1'b0;
+   reg 	      abc_resin = 1'b0;
+   reg 	      abc_xm    = 1'b0;
 
    function reg opt_mosfet(input signal, input mosfet);
       if (mosfet)
@@ -494,6 +494,9 @@ module abcbus (
 	  abc_iobase <= 20'bx;
 	  irq_mask   <= 32'b0;
 	  clear_irq  <= 1'b0;
+	  // abc_resin, nmi, int and wait are deliberately not affected
+	  // by an internal CPU reset. They are, however, initialized
+	  // to 0 on a CPU init (see above.)
        end
      else
        begin
@@ -504,6 +507,8 @@ module abcbus (
 	       casez (cpu_addr[5:2])
 		 5'b??010:
 		   abc_iobase <= cpu_wdata[24:4];
+		 5'b??011:
+		   { abc_resin, abc_nmi, abc_int, abc_wait } <= cpu_wdata[3:0];
 		 5'b??100:
 		   irq_mask   <= cpu_wdata;
 		 5'b??101:
@@ -549,6 +554,7 @@ module abcbus (
        5'b00000: cpu_rdata = { 24'b0, abc_status[0] };
        5'b00001: cpu_rdata = { 23'b0, ~iosel_en, ioselx[7:0] };
        5'b00010: cpu_rdata = abc_iobase;
+       5'b00011: cpu_rdata = { 28'b0, abc_resin, abc_nmi, abc_int, abc_wait };
        5'b00100: cpu_rdata = irq_mask & irq_status_mask;
        5'b00101: cpu_rdata = irq_status;
        default:  cpu_rdata = 32'bx;

fw/ioregs.h

@@ -112,6 +112,11 @@
 #define ABC_STATUS_800		4
 #define ABC_IOSEL		IODEVL(ABC,1)
 #define ABC_IOBASE		IODEVL(ABC,2)
+#define ABC_BUSCTL		IODEVL(ABC,3)
+#define ABC_BUSCTL_WAIT		1
+#define ABC_BUSCTL_INT		2
+#define ABC_BUSCTL_NMI		4
+#define ABC_BUSCTL_RESET	8
 #define ABC_IRQMASK		IODEVL(ABC,4)
 #define ABC_IRQSTATUS		IODEVL(ABC,5)
 #define ABC_OUTSTATUS		IODEVB0(ABC,5)