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@@ -180,9 +180,13 @@ sub generate_verilog($)
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if ($xdev) {
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if ($xdev) {
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printf $out "\twire [%2d:0] iodev_valid_%s = xdev_valid[%d:%d];\n",
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printf $out "\twire [%2d:0] iodev_valid_%s = xdev_valid[%d:%d];\n",
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$dcount-1, $name, $nxdev+$dcount-1, $nxdev;
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$dcount-1, $name, $nxdev+$dcount-1, $nxdev;
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+ printf $out "\tlocalparam [31:0] iodev_%s_base = 32'h%08x;\n",
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+ $name, base($nxdev, $xdev_addr_bits, $xdev_addr_shift);
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} else {
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} else {
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printf $out "\twire [%2d:0] iodev_valid_%s = iodev_valid[%d:%d];\n",
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printf $out "\twire [%2d:0] iodev_valid_%s = iodev_valid[%d:%d];\n",
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$dcount-1, $name, $ndev+$dcount-1, $ndev;
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$dcount-1, $name, $ndev+$dcount-1, $ndev;
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+ printf $out "\tlocalparam [31:0] iodev_%s_base = 32'h%08x;\n",
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+ $name, base($ndev, $iodev_addr_bits, $iodev_addr_shift);
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}
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}
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printf $out "\ttri1 [%2d:0] iodev_wait_n_%s;\n", $dcount-1, $name;
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printf $out "\ttri1 [%2d:0] iodev_wait_n_%s;\n", $dcount-1, $name;
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