Cleaner way to run programming file converter

Use a generic script which runs any *.cof file in the project in the
post_quartus_asm.tcl hook.

max80.qsf

@@ -286,7 +286,6 @@ set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS OUTPUT DRIVI
 set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:postmodule.tcl"
 
 
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name TCL_SCRIPT_FILE post_quartus_asm.tcl
 set_global_assignment -name TCL_SCRIPT_FILE postmodule.tcl
 set_global_assignment -name SOURCE_FILE max80jic.cof
@@ -296,4 +295,5 @@ set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
 set_global_assignment -name SYSTEMVERILOG_FILE syncho.sv
 set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
 set_global_assignment -name SDC_FILE max80.sdc
-set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
+set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

output_files/max80.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for max80
-Fri Aug  6 19:38:14 2021
+Fri Aug  6 20:12:50 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Fri Aug  6 19:38:14 2021 ;
+; Assembler Status      ; Successful - Fri Aug  6 20:12:50 2021 ;
 ; Revision Name         ; max80                                 ;
 ; Top-level Entity Name ; max80                                 ;
 ; Family                ; Cyclone IV E                          ;
@@ -113,7 +113,7 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:38:12 2021
+    Info: Processing started: Fri Aug  6 20:12:48 2021
 Info: Command: quartus_asm --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
@@ -124,7 +124,7 @@ Info (210117): Created JAM or JBC file for the specified chain:
 Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 569 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:14 2021
+    Info: Processing ended: Fri Aug  6 20:12:50 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 

output_files/max80.cmp.rpt

@@ -1,5 +1,5 @@
 Compilation report for max80
-Fri Aug  6 19:38:21 2021
+Fri Aug  6 20:12:57 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -211,7 +211,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Fri Aug  6 19:38:21 2021       ;
+; Flow Status                        ; Successful - Fri Aug  6 20:12:57 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -235,7 +235,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 08/06/2021 19:37:59 ;
+; Start date & time ; 08/06/2021 20:12:35 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; max80               ;
 +-------------------+---------------------+
@@ -246,7 +246,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID                      ; 64552973467468.162830387951874         ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID                      ; 275741387998995.162830595557146        ; --            ; --          ; --                                ;
 ; EDA_ENABLE_GLITCH_FILTERING                ; On                                     ; --            ; --          ; eda_simulation                    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
@@ -300,13 +300,13 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 678 MB              ; 00:00:15                           ;
+; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 679 MB              ; 00:00:15                           ;
 ; Fitter               ; 00:00:06     ; 1.0                     ; 1524 MB             ; 00:00:07                           ;
 ; Assembler            ; 00:00:02     ; 1.0                     ; 569 MB              ; 00:00:02                           ;
-; Power Analyzer       ; 00:00:01     ; 1.0                     ; 1020 MB             ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:01     ; 1.1                     ; 736 MB              ; 00:00:01                           ;
-; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 813 MB              ; 00:00:00                           ;
-; Total                ; 00:00:16     ; --                      ; --                  ; 00:00:26                           ;
+; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1021 MB             ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.1                     ; 728 MB              ; 00:00:01                           ;
+; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 813 MB              ; 00:00:00                           ;
+; Total                ; 00:00:17     ; --                      ; --                  ; 00:00:26                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
@@ -330,7 +330,7 @@ https://fpgasoftware.intel.com/eula.
 quartus_map --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
 quartus_fit --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
 quartus_asm --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
-quartus_pow --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
+quartus_pow --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
 quartus_sta --lower_priority max80 -c max80
 quartus_eda --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
 
@@ -339,7 +339,7 @@ quartus_eda --lower_priority --read_settings_files=off --write_settings_files=of
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Fri Aug  6 19:38:04 2021       ;
+; Analysis & Synthesis Status        ; Successful - Fri Aug  6 20:12:40 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -1371,7 +1371,7 @@ The equations can be found in /home/hpa/abc80/max80/blinktest/output_files/max80
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:37:59 2021
+    Info: Processing started: Fri Aug  6 20:12:35 2021
 Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
@@ -1796,8 +1796,8 @@ Info (21057): Implemented 485 device resources after synthesis - the final resou
     Info (21061): Implemented 340 logic cells
     Info (21065): Implemented 2 PLLs
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 217 warnings
-    Info: Peak virtual memory: 678 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:04 2021
+    Info: Peak virtual memory: 679 megabytes
+    Info: Processing ended: Fri Aug  6 20:12:40 2021
     Info: Elapsed time: 00:00:05
     Info: Total CPU time (on all processors): 00:00:15
 
@@ -1805,7 +1805,7 @@ Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 217 warnings
 +----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                   ;
 +------------------------------------+---------------------------------------------+
-; Fitter Status                      ; Successful - Fri Aug  6 19:38:11 2021       ;
+; Fitter Status                      ; Successful - Fri Aug  6 20:12:47 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -3825,7 +3825,7 @@ Warning (169064): Following 52 pins have no output enable or a GND or VCC output
 Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 29 warnings
     Info: Peak virtual memory: 1524 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:11 2021
+    Info: Processing ended: Fri Aug  6 20:12:47 2021
     Info: Elapsed time: 00:00:06
     Info: Total CPU time (on all processors): 00:00:07
 
@@ -3839,7 +3839,7 @@ The suppressed messages can be found in /home/hpa/abc80/max80/blinktest/output_f
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Fri Aug  6 19:38:14 2021 ;
+; Assembler Status      ; Successful - Fri Aug  6 20:12:50 2021 ;
 ; Revision Name         ; max80                                 ;
 ; Top-level Entity Name ; max80                                 ;
 ; Family                ; Cyclone IV E                          ;
@@ -3911,7 +3911,7 @@ The suppressed messages can be found in /home/hpa/abc80/max80/blinktest/output_f
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:38:12 2021
+    Info: Processing started: Fri Aug  6 20:12:48 2021
 Info: Command: quartus_asm --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
@@ -3922,7 +3922,7 @@ Info (210117): Created JAM or JBC file for the specified chain:
 Device 1 (EP4CE15F17; /home/hpa/abc80/max80/blinktest/output_files/max80.sof)
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 569 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:14 2021
+    Info: Processing ended: Fri Aug  6 20:12:50 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:02
 
@@ -3947,7 +3947,7 @@ Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
 +-------------------------------------------------------------------------------------------+
 ; Power Analyzer Summary                                                                    ;
 +----------------------------------------+--------------------------------------------------+
-; Power Analyzer Status                  ; Successful - Fri Aug  6 19:38:17 2021            ;
+; Power Analyzer Status                  ; Successful - Fri Aug  6 20:12:54 2021            ;
 ; Quartus Prime Version                  ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition      ;
 ; Revision Name                          ; max80                                            ;
 ; Top-level Entity Name                  ; max80                                            ;
@@ -4274,8 +4274,8 @@ Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
 Info: *******************************************************************
 Info: Running Quartus Prime Power Analyzer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:38:16 2021
-Info: Command: quartus_pow --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
+    Info: Processing started: Fri Aug  6 20:12:52 2021
+Info: Command: quartus_pow --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
@@ -4315,8 +4315,8 @@ Info (334004): Delay annotation completed successfully
 Info (215049): Average toggle rate for this design is 10.833 millions of transitions / sec
 Info (215031): Total thermal power estimate for the design is 217.59 mW
 Info: Quartus Prime Power Analyzer was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 1020 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:18 2021
+    Info: Peak virtual memory: 1021 megabytes
+    Info: Processing ended: Fri Aug  6 20:12:54 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:01
 
@@ -4368,8 +4368,9 @@ https://fpgasoftware.intel.com/eula.
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.1%      ;
-;     Processors 3-8         ;   0.7%      ;
+;     Processor 2            ;   1.2%      ;
+;     Processor 3            ;   0.7%      ;
+;     Processors 4-8         ;   0.7%      ;
 +----------------------------+-------------+
 
 
@@ -4378,7 +4379,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------+--------+--------------------------+
 ; SDC File Path ; Status ; Read at                  ;
 +---------------+--------+--------------------------+
-; max80.sdc     ; OK     ; Fri Aug  6 19:38:19 2021 ;
+; max80.sdc     ; OK     ; Fri Aug  6 20:12:55 2021 ;
 +---------------+--------+--------------------------+
 
 
@@ -4838,55 +4839,53 @@ No paths to report.
 ; 0.466 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.758      ;
 ; 0.467 ; led_ctr[0]               ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.758      ;
 ; 0.736 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.027      ;
+; 0.737 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
+; 0.737 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
 ; 0.737 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.029      ;
 ; 0.737 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.029      ;
 ; 0.737 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.029      ;
-; 0.737 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
-; 0.737 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
 ; 0.738 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[20]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
-; 0.739 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
-; 0.739 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
-; 0.739 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
 ; 0.739 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
 ; 0.739 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
 ; 0.739 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
-; 0.740 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
+; 0.739 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
+; 0.739 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
+; 0.739 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
 ; 0.740 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[21]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[15]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[13]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
-; 0.741 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
-; 0.741 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
-; 0.741 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
+; 0.740 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
 ; 0.741 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[17]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[11]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
+; 0.741 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
+; 0.741 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
+; 0.741 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
 ; 0.742 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
 ; 0.742 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
 ; 0.742 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
-; 0.758 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.050      ;
 ; 0.758 ; led_ctr[0]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.049      ;
+; 0.758 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.050      ;
 ; 0.955 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.246      ;
 ; 0.986 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.278      ;
 ; 1.091 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.382      ;
-; 1.092 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
-; 1.092 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
-; 1.092 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
 ; 1.092 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
 ; 1.092 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
 ; 1.092 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
-; 1.093 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
-; 1.093 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
+; 1.092 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
+; 1.092 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
+; 1.092 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
 ; 1.093 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
 ; 1.093 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
 ; 1.093 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
@@ -4894,47 +4893,49 @@ No paths to report.
 ; 1.093 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
 ; 1.093 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
 ; 1.093 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
+; 1.093 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
+; 1.093 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
 ; 1.094 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.385      ;
 ; 1.094 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.385      ;
 ; 1.100 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.392      ;
-; 1.101 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
-; 1.101 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
 ; 1.101 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
 ; 1.101 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
 ; 1.101 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
 ; 1.101 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
 ; 1.101 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
-; 1.102 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
-; 1.102 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
+; 1.101 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
+; 1.101 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
 ; 1.102 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
+; 1.102 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
+; 1.102 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
 ; 1.103 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
 ; 1.103 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
 ; 1.103 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
 ; 1.109 ; rst_ctr[5]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.401      ;
-; 1.110 ; rst_ctr[3]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
-; 1.110 ; rst_ctr[1]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
 ; 1.110 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
 ; 1.110 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
 ; 1.110 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
 ; 1.110 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
 ; 1.110 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
-; 1.111 ; rst_ctr[9]               ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
-; 1.111 ; rst_ctr[7]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
+; 1.110 ; rst_ctr[3]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
+; 1.110 ; rst_ctr[1]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
 ; 1.111 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
+; 1.111 ; rst_ctr[9]               ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
+; 1.111 ; rst_ctr[7]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
 ; 1.112 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.403      ;
 ; 1.112 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.403      ;
-; 1.222 ; rst_ctr[2]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.514      ;
 ; 1.222 ; led_ctr[14]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.513      ;
+; 1.222 ; led_ctr[2]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.513      ;
 +-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
 
 
@@ -7486,7 +7487,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:38:18 2021
+    Info: Processing started: Fri Aug  6 20:12:54 2021
 Info: Command: quartus_sta --lower_priority max80 -c max80
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -7608,8 +7609,8 @@ Info (332146): Worst-case minimum pulse width slack is 2.563
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings
-    Info: Peak virtual memory: 736 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:20 2021
+    Info: Peak virtual memory: 728 megabytes
+    Info: Processing ended: Fri Aug  6 20:12:56 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:01
 
@@ -7617,7 +7618,7 @@ Info: Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Fri Aug  6 19:38:21 2021 ;
+; EDA Netlist Writer Status ; Successful - Fri Aug  6 20:12:57 2021 ;
 ; Revision Name             ; max80                                 ;
 ; Top-level Entity Name     ; max80                                 ;
 ; Family                    ; Cyclone IV E                          ;
@@ -7664,15 +7665,15 @@ Info: Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:38:20 2021
+    Info: Processing started: Fri Aug  6 20:12:57 2021
 Info: Command: quartus_eda --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
 Info (204020): Writing VCD Dump Commands for all nodes to /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 816 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:21 2021
-    Info: Elapsed time: 00:00:01
+    Info: Processing ended: Fri Aug  6 20:12:57 2021
+    Info: Elapsed time: 00:00:00
     Info: Total CPU time (on all processors): 00:00:00
 
 

output_files/max80.done

@@ -1 +1 @@
-Fri Aug  6 19:38:21 2021
+Fri Aug  6 20:12:57 2021

output_files/max80.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for max80
-Fri Aug  6 19:38:21 2021
+Fri Aug  6 20:12:57 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Fri Aug  6 19:38:21 2021 ;
+; EDA Netlist Writer Status ; Successful - Fri Aug  6 20:12:57 2021 ;
 ; Revision Name             ; max80                                 ;
 ; Top-level Entity Name     ; max80                                 ;
 ; Family                    ; Cyclone IV E                          ;
@@ -84,15 +84,15 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:38:20 2021
+    Info: Processing started: Fri Aug  6 20:12:57 2021
 Info: Command: quartus_eda --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (204019): Generated file max80.vo in folder "/home/hpa/abc80/max80/blinktest/simulation/modelsim/" for EDA simulation tool
 Info (204020): Writing VCD Dump Commands for all nodes to /home/hpa/abc80/max80/blinktest/simulation/modelsim/max80_dump_all_vcd_nodes.tcl
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 816 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:21 2021
-    Info: Elapsed time: 00:00:01
+    Info: Processing ended: Fri Aug  6 20:12:57 2021
+    Info: Elapsed time: 00:00:00
     Info: Total CPU time (on all processors): 00:00:00
 
 

output_files/max80.fit.rpt

@@ -1,5 +1,5 @@
 Fitter report for max80
-Fri Aug  6 19:38:11 2021
+Fri Aug  6 20:12:47 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -74,7 +74,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                   ;
 +------------------------------------+---------------------------------------------+
-; Fitter Status                      ; Successful - Fri Aug  6 19:38:11 2021       ;
+; Fitter Status                      ; Successful - Fri Aug  6 20:12:47 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -2094,7 +2094,7 @@ Warning (169064): Following 52 pins have no output enable or a GND or VCC output
 Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/blinktest/output_files/max80.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 29 warnings
     Info: Peak virtual memory: 1524 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:11 2021
+    Info: Processing ended: Fri Aug  6 20:12:47 2021
     Info: Elapsed time: 00:00:06
     Info: Total CPU time (on all processors): 00:00:07
 

output_files/max80.fit.summary

@@ -1,4 +1,4 @@
-Fitter Status : Successful - Fri Aug  6 19:38:11 2021
+Fitter Status : Successful - Fri Aug  6 20:12:47 2021
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for max80
-Fri Aug  6 19:38:21 2021
+Fri Aug  6 20:12:57 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Fri Aug  6 19:38:21 2021       ;
+; Flow Status                        ; Successful - Fri Aug  6 20:12:57 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 08/06/2021 19:37:59 ;
+; Start date & time ; 08/06/2021 20:12:35 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; max80               ;
 +-------------------+---------------------+
@@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                            ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +--------------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID                      ; 64552973467468.162830387951874         ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID                      ; 275741387998995.162830595557146        ; --            ; --          ; --                                ;
 ; EDA_ENABLE_GLITCH_FILTERING                ; On                                     ; --            ; --          ; eda_simulation                    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST            ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
@@ -130,13 +130,13 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 678 MB              ; 00:00:15                           ;
+; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 679 MB              ; 00:00:15                           ;
 ; Fitter               ; 00:00:06     ; 1.0                     ; 1524 MB             ; 00:00:07                           ;
 ; Assembler            ; 00:00:02     ; 1.0                     ; 569 MB              ; 00:00:02                           ;
-; Power Analyzer       ; 00:00:01     ; 1.0                     ; 1020 MB             ; 00:00:01                           ;
-; Timing Analyzer      ; 00:00:01     ; 1.1                     ; 736 MB              ; 00:00:01                           ;
-; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 813 MB              ; 00:00:00                           ;
-; Total                ; 00:00:16     ; --                      ; --                  ; 00:00:26                           ;
+; Power Analyzer       ; 00:00:02     ; 1.0                     ; 1021 MB             ; 00:00:01                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.1                     ; 728 MB              ; 00:00:01                           ;
+; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 813 MB              ; 00:00:00                           ;
+; Total                ; 00:00:17     ; --                      ; --                  ; 00:00:26                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
@@ -160,7 +160,7 @@ https://fpgasoftware.intel.com/eula.
 quartus_map --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
 quartus_fit --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
 quartus_asm --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
-quartus_pow --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
+quartus_pow --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
 quartus_sta --lower_priority max80 -c max80
 quartus_eda --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
 

output_files/max80.jam

@@ -13,7 +13,7 @@
 'refer to the applicable agreement for further details, at
 'https://fpgasoftware.intel.com/eula.
 
-'Device #1: EP4CE15 - /home/hpa/abc80/max80/blinktest/output_files/max80.sof Fri Aug  6 19:38:12 2021
+'Device #1: EP4CE15 - /home/hpa/abc80/max80/blinktest/output_files/max80.sof Fri Aug  6 20:12:48 2021
 
 
 NOTE "CREATOR" "QUARTUS PRIME JAM COMPOSER 20.1";
@@ -2284,4 +2284,4 @@ NEXT j;
 POP j;
 ENDPROC;
 ' END OF FILE
-CRC 2D51;
+CRC A9DE;

output_files/max80.map.rpt

@@ -1,5 +1,5 @@
 Analysis & Synthesis report for max80
-Fri Aug  6 19:38:04 2021
+Fri Aug  6 20:12:40 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -68,7 +68,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Fri Aug  6 19:38:04 2021       ;
+; Analysis & Synthesis Status        ; Successful - Fri Aug  6 20:12:40 2021       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; max80                                       ;
 ; Top-level Entity Name              ; max80                                       ;
@@ -1100,7 +1100,7 @@ The equations can be found in /home/hpa/abc80/max80/blinktest/output_files/max80
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:37:59 2021
+    Info: Processing started: Fri Aug  6 20:12:35 2021
 Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 8 of the 8 processors detected
@@ -1525,8 +1525,8 @@ Info (21057): Implemented 485 device resources after synthesis - the final resou
     Info (21061): Implemented 340 logic cells
     Info (21065): Implemented 2 PLLs
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 217 warnings
-    Info: Peak virtual memory: 678 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:04 2021
+    Info: Peak virtual memory: 679 megabytes
+    Info: Processing ended: Fri Aug  6 20:12:40 2021
     Info: Elapsed time: 00:00:05
     Info: Total CPU time (on all processors): 00:00:15
 

output_files/max80.map.summary

@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Fri Aug  6 19:38:04 2021
+Analysis & Synthesis Status : Successful - Fri Aug  6 20:12:40 2021
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.pow.rpt

@@ -1,5 +1,5 @@
 Power Analyzer report for max80
-Fri Aug  6 19:38:18 2021
+Fri Aug  6 20:12:54 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------------------------------+
 ; Power Analyzer Summary                                                                    ;
 +----------------------------------------+--------------------------------------------------+
-; Power Analyzer Status                  ; Successful - Fri Aug  6 19:38:17 2021            ;
+; Power Analyzer Status                  ; Successful - Fri Aug  6 20:12:54 2021            ;
 ; Quartus Prime Version                  ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition      ;
 ; Revision Name                          ; max80                                            ;
 ; Top-level Entity Name                  ; max80                                            ;
@@ -392,8 +392,8 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Power Analyzer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:38:16 2021
-Info: Command: quartus_pow --lower_priority --read_settings_files=off --write_settings_files=off max80 -c max80
+    Info: Processing started: Fri Aug  6 20:12:52 2021
+Info: Command: quartus_pow --lower_priority --read_settings_files=on --write_settings_files=off max80 -c max80
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (21077): Low junction temperature is 0 degrees C
 Info (21077): High junction temperature is 85 degrees C
@@ -433,8 +433,8 @@ Info (334004): Delay annotation completed successfully
 Info (215049): Average toggle rate for this design is 10.833 millions of transitions / sec
 Info (215031): Total thermal power estimate for the design is 217.59 mW
 Info: Quartus Prime Power Analyzer was successful. 0 errors, 11 warnings
-    Info: Peak virtual memory: 1020 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:18 2021
+    Info: Peak virtual memory: 1021 megabytes
+    Info: Processing ended: Fri Aug  6 20:12:54 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:01
 

output_files/max80.pow.summary

@@ -1,4 +1,4 @@
-Power Analyzer Status : Successful - Fri Aug  6 19:38:17 2021
+Power Analyzer Status : Successful - Fri Aug  6 20:12:54 2021
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : max80
 Top-level Entity Name : max80

output_files/max80.sta.rpt

@@ -1,5 +1,5 @@
 Timing Analyzer report for max80
-Fri Aug  6 19:38:20 2021
+Fri Aug  6 20:12:56 2021
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -123,8 +123,9 @@ https://fpgasoftware.intel.com/eula.
 ;                            ;             ;
 ; Usage by Processor         ; % Time Used ;
 ;     Processor 1            ; 100.0%      ;
-;     Processor 2            ;   1.1%      ;
-;     Processors 3-8         ;   0.7%      ;
+;     Processor 2            ;   1.2%      ;
+;     Processor 3            ;   0.7%      ;
+;     Processors 4-8         ;   0.7%      ;
 +----------------------------+-------------+
 
 
@@ -133,7 +134,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------+--------+--------------------------+
 ; SDC File Path ; Status ; Read at                  ;
 +---------------+--------+--------------------------+
-; max80.sdc     ; OK     ; Fri Aug  6 19:38:19 2021 ;
+; max80.sdc     ; OK     ; Fri Aug  6 20:12:55 2021 ;
 +---------------+--------+--------------------------+
 
 
@@ -593,55 +594,53 @@ No paths to report.
 ; 0.466 ; rst_ctr[0]               ; rst_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.758      ;
 ; 0.467 ; led_ctr[0]               ; led_ctr[0]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.758      ;
 ; 0.736 ; led_ctr[14]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.027      ;
+; 0.737 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
+; 0.737 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
 ; 0.737 ; rst_ctr[10]              ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.029      ;
 ; 0.737 ; rst_ctr[4]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.029      ;
 ; 0.737 ; rst_ctr[2]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.029      ;
-; 0.737 ; led_ctr[12]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
-; 0.737 ; led_ctr[2]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.028      ;
 ; 0.738 ; led_ctr[26]~_Duplicate_1 ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[20]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[18]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[16]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[10]              ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
 ; 0.738 ; led_ctr[4]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.029      ;
-; 0.739 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
-; 0.739 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
-; 0.739 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
 ; 0.739 ; led_ctr[28]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
 ; 0.739 ; led_ctr[8]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
 ; 0.739 ; led_ctr[6]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.030      ;
-; 0.740 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
+; 0.739 ; rst_ctr[8]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
+; 0.739 ; rst_ctr[6]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
+; 0.739 ; rst_ctr[5]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.031      ;
 ; 0.740 ; led_ctr[24]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[22]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[21]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[15]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[13]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
 ; 0.740 ; led_ctr[5]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.031      ;
-; 0.741 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
-; 0.741 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
-; 0.741 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
+; 0.740 ; rst_ctr[3]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.032      ;
 ; 0.741 ; led_ctr[19]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[17]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[11]              ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[9]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[7]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
 ; 0.741 ; led_ctr[3]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.032      ;
+; 0.741 ; rst_ctr[11]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
+; 0.741 ; rst_ctr[9]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
+; 0.741 ; rst_ctr[7]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.033      ;
 ; 0.742 ; led_ctr[27]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
 ; 0.742 ; led_ctr[25]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
 ; 0.742 ; led_ctr[23]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.033      ;
-; 0.758 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.050      ;
 ; 0.758 ; led_ctr[0]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.049      ;
+; 0.758 ; rst_ctr[1]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.050      ;
 ; 0.955 ; led_ctr[1]               ; led_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.246      ;
 ; 0.986 ; rst_ctr[0]               ; rst_ctr[1]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.278      ;
 ; 1.091 ; led_ctr[14]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.382      ;
-; 1.092 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
-; 1.092 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
-; 1.092 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
 ; 1.092 ; led_ctr[12]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
 ; 1.092 ; led_ctr[16]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
 ; 1.092 ; led_ctr[2]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.383      ;
-; 1.093 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
-; 1.093 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
+; 1.092 ; rst_ctr[4]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
+; 1.092 ; rst_ctr[2]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
+; 1.092 ; rst_ctr[10]              ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.384      ;
 ; 1.093 ; led_ctr[20]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
 ; 1.093 ; led_ctr[4]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
 ; 1.093 ; led_ctr[18]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
@@ -649,47 +648,49 @@ No paths to report.
 ; 1.093 ; led_ctr[8]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
 ; 1.093 ; led_ctr[6]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
 ; 1.093 ; led_ctr[26]~_Duplicate_1 ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.384      ;
+; 1.093 ; rst_ctr[8]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
+; 1.093 ; rst_ctr[6]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.385      ;
 ; 1.094 ; led_ctr[24]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.385      ;
 ; 1.094 ; led_ctr[22]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.385      ;
 ; 1.100 ; rst_ctr[5]               ; rst_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.392      ;
-; 1.101 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
-; 1.101 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
 ; 1.101 ; led_ctr[13]              ; led_ctr[14]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
 ; 1.101 ; led_ctr[0]               ; led_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
 ; 1.101 ; led_ctr[15]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
 ; 1.101 ; led_ctr[5]               ; led_ctr[6]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
 ; 1.101 ; led_ctr[21]              ; led_ctr[22]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.392      ;
-; 1.102 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
-; 1.102 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
+; 1.101 ; rst_ctr[3]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
+; 1.101 ; rst_ctr[1]               ; rst_ctr[2]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.393      ;
 ; 1.102 ; led_ctr[11]              ; led_ctr[12]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[19]              ; led_ctr[20]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[17]              ; led_ctr[18]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[9]               ; led_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[3]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
 ; 1.102 ; led_ctr[7]               ; led_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.393      ;
+; 1.102 ; rst_ctr[9]               ; rst_ctr[10]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
+; 1.102 ; rst_ctr[7]               ; rst_ctr[8]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.394      ;
 ; 1.103 ; led_ctr[25]              ; led_ctr[26]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
 ; 1.103 ; led_ctr[27]~_Duplicate_1 ; led_ctr[28]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
 ; 1.103 ; led_ctr[23]              ; led_ctr[24]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.394      ;
 ; 1.109 ; rst_ctr[5]               ; rst_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.401      ;
-; 1.110 ; rst_ctr[3]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
-; 1.110 ; rst_ctr[1]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
 ; 1.110 ; led_ctr[13]              ; led_ctr[15]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
 ; 1.110 ; led_ctr[15]              ; led_ctr[17]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
 ; 1.110 ; led_ctr[0]               ; led_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
 ; 1.110 ; led_ctr[5]               ; led_ctr[7]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
 ; 1.110 ; led_ctr[21]              ; led_ctr[23]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.401      ;
-; 1.111 ; rst_ctr[9]               ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
-; 1.111 ; rst_ctr[7]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
+; 1.110 ; rst_ctr[3]               ; rst_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
+; 1.110 ; rst_ctr[1]               ; rst_ctr[3]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.402      ;
 ; 1.111 ; led_ctr[11]              ; led_ctr[13]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[19]              ; led_ctr[21]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[3]               ; led_ctr[5]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[17]              ; led_ctr[19]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[9]               ; led_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
 ; 1.111 ; led_ctr[7]               ; led_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.402      ;
+; 1.111 ; rst_ctr[9]               ; rst_ctr[11]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
+; 1.111 ; rst_ctr[7]               ; rst_ctr[9]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.403      ;
 ; 1.112 ; led_ctr[25]              ; led_ctr[27]~_Duplicate_1 ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.403      ;
 ; 1.112 ; led_ctr[23]              ; led_ctr[25]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.403      ;
-; 1.222 ; rst_ctr[2]               ; rst_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 1.514      ;
 ; 1.222 ; led_ctr[14]              ; led_ctr[16]              ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.513      ;
+; 1.222 ; led_ctr[2]               ; led_ctr[4]               ; pll|altpll_component|auto_generated|pll1|clk[1] ; pll|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 1.513      ;
 +-------+--------------------------+--------------------------+-------------------------------------------------+-------------------------------------------------+--------------+------------+------------+
 
 
@@ -3241,7 +3242,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Fri Aug  6 19:38:18 2021
+    Info: Processing started: Fri Aug  6 20:12:54 2021
 Info: Command: quartus_sta --lower_priority max80 -c max80
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -3363,8 +3364,8 @@ Info (332146): Worst-case minimum pulse width slack is 2.563
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 10 warnings
-    Info: Peak virtual memory: 736 megabytes
-    Info: Processing ended: Fri Aug  6 19:38:20 2021
+    Info: Peak virtual memory: 728 megabytes
+    Info: Processing ended: Fri Aug  6 20:12:56 2021
     Info: Elapsed time: 00:00:02
     Info: Total CPU time (on all processors): 00:00:01
 

post_quartus_asm.tcl

@@ -1,2 +1,12 @@
-# Run after assembler
-qexec "quartus_cpf -c max80jic.cof"
+# Runs after the assembler (quartus_asm)
+
+# Run quartus_cpf for any .cof files in the project
+set source_file_coll [get_all_global_assignments -name SOURCE_FILE]
+foreach_in_collection file_asgn $source_file_coll {
+    set file [lindex $file_asgn 2]
+    if [string match *.cof $file] {
+	set cmd "quartus_cpf --convert \"$file\""
+	post_message -type info "Command: $cmd"
+	qexec "$cmd"
+    }
+}

postmodule.tcl

@@ -5,5 +5,6 @@ set revision [lindex $quartus(args) 1]
 set module_script "post_$module.tcl"
 
 if [file exists $module_script] {
+    project_open $project -revision $revision
     source $module_script
 }