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@@ -1,12 +1,12 @@
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// megafunction wizard: %FIFO%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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-// MODULE: dcfifo
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+// MODULE: scfifo
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// ============================================================
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// File Name: fifo.v
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// Megafunction Name(s):
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-// dcfifo
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+// scfifo
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//
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// Simulation Library Files(s):
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// altera_mf
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@@ -39,76 +39,61 @@
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// synopsys translate_on
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module fifo (
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aclr,
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+ clock,
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data,
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- rdclk,
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rdreq,
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- wrclk,
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+ sclr,
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wrreq,
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+ empty,
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+ full,
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q,
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- rdempty,
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- rdusedw,
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- wrfull,
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- wrusedw);
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+ usedw);
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input aclr;
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+ input clock;
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input [7:0] data;
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- input rdclk;
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input rdreq;
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- input wrclk;
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+ input sclr;
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input wrreq;
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+ output empty;
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+ output full;
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output [7:0] q;
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- output rdempty;
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- output [8:0] rdusedw;
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- output wrfull;
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- output [8:0] wrusedw;
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-`ifndef ALTERA_RESERVED_QIS
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-// synopsys translate_off
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-`endif
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- tri0 aclr;
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-`ifndef ALTERA_RESERVED_QIS
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-// synopsys translate_on
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-`endif
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+ output [8:0] usedw;
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- wire [7:0] sub_wire0;
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+ wire sub_wire0;
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wire sub_wire1;
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- wire [8:0] sub_wire2;
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- wire sub_wire3;
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- wire [8:0] sub_wire4;
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- wire [7:0] q = sub_wire0[7:0];
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- wire rdempty = sub_wire1;
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- wire [8:0] rdusedw = sub_wire2[8:0];
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- wire wrfull = sub_wire3;
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- wire [8:0] wrusedw = sub_wire4[8:0];
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+ wire [7:0] sub_wire2;
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+ wire [8:0] sub_wire3;
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+ wire empty = sub_wire0;
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+ wire full = sub_wire1;
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+ wire [7:0] q = sub_wire2[7:0];
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+ wire [8:0] usedw = sub_wire3[8:0];
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- dcfifo dcfifo_component (
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+ scfifo scfifo_component (
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.aclr (aclr),
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+ .clock (clock),
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.data (data),
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- .rdclk (rdclk),
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.rdreq (rdreq),
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- .wrclk (wrclk),
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+ .sclr (sclr),
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.wrreq (wrreq),
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- .q (sub_wire0),
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- .rdempty (sub_wire1),
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- .rdusedw (sub_wire2),
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- .wrfull (sub_wire3),
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- .wrusedw (sub_wire4),
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- .eccstatus (),
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- .rdfull (),
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- .wrempty ());
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+ .empty (sub_wire0),
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+ .full (sub_wire1),
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+ .q (sub_wire2),
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+ .usedw (sub_wire3),
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+ .almost_empty (),
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+ .almost_full (),
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+ .eccstatus ());
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defparam
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- dcfifo_component.intended_device_family = "Cyclone IV E",
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- dcfifo_component.lpm_numwords = 512,
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- dcfifo_component.lpm_showahead = "ON",
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- dcfifo_component.lpm_type = "dcfifo",
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- dcfifo_component.lpm_width = 8,
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- dcfifo_component.lpm_widthu = 9,
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- dcfifo_component.overflow_checking = "ON",
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- dcfifo_component.rdsync_delaypipe = 4,
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- dcfifo_component.read_aclr_synch = "OFF",
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- dcfifo_component.underflow_checking = "ON",
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- dcfifo_component.use_eab = "ON",
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- dcfifo_component.write_aclr_synch = "OFF",
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- dcfifo_component.wrsync_delaypipe = 4;
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+ scfifo_component.add_ram_output_register = "OFF",
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+ scfifo_component.intended_device_family = "Cyclone IV E",
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+ scfifo_component.lpm_numwords = 512,
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+ scfifo_component.lpm_showahead = "ON",
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+ scfifo_component.lpm_type = "scfifo",
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+ scfifo_component.lpm_width = 8,
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+ scfifo_component.lpm_widthu = 9,
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+ scfifo_component.overflow_checking = "ON",
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+ scfifo_component.underflow_checking = "ON",
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+ scfifo_component.use_eab = "ON";
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endmodule
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@@ -121,7 +106,7 @@ endmodule
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// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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-// Retrieval info: PRIVATE: Clock NUMERIC "4"
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+// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: Depth NUMERIC "512"
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// Retrieval info: PRIVATE: Empty NUMERIC "1"
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// Retrieval info: PRIVATE: Full NUMERIC "1"
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@@ -130,7 +115,7 @@ endmodule
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// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
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// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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-// Retrieval info: PRIVATE: Optimize NUMERIC "0"
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+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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@@ -143,47 +128,42 @@ endmodule
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// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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// Retrieval info: PRIVATE: rsFull NUMERIC "0"
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// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
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-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
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+// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
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+// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
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// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: wsFull NUMERIC "1"
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// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
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// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
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-// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
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+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
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// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
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// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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-// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
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-// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
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// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: USE_EAB STRING "ON"
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-// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
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-// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
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-// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
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+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
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+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
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+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
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+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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-// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
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-// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
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// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
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-// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
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-// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
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-// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
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+// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
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+// Retrieval info: USED_PORT: usedw 0 0 9 0 OUTPUT NODEFVAL "usedw[8..0]"
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// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
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-// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
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// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
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-// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
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// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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-// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
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+// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
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// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
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+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
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-// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
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-// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
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-// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
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-// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
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+// Retrieval info: CONNECT: usedw 0 0 9 0 @usedw 0 0 9 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
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