sdram: leave CKE permanently enabled

There is no point in using CKE; just leave it permanently enabled.

fpga/output_files/max80.map

@@ -10,7 +10,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 Notes:
 
-- Data checksum for this conversion is 0xF76A3AFA
+- Data checksum for this conversion is 0xF769F89A
 
 - All the addresses in this file are byte addresses
 

fpga/sdram.sv

@@ -150,6 +150,8 @@ module sdram
    assign	sr_cas_n = dram_cmd[1];
    assign	sr_we_n  = dram_cmd[0];
 
+   assign       sr_cke   = 1'b1;
+
    // SDRAM output clock buffer. The SDRAM output clock is
    // inverted with respect to our internal clock, so that
    // the SDRAM sees the positive clock edge in the middle of
@@ -167,8 +169,6 @@ module sdram
 			);
 
    // SDRAM output signal registers
-   reg			    dram_cke;
-   assign		    sr_cke = dram_cke;
    reg [12:0]		    dram_a;
    assign		    sr_a = dram_a;
    reg [1:0]		    dram_ba;
@@ -247,7 +247,6 @@ module sdram
    always @(posedge clk or negedge rst_n)
      if (~rst_n)
        begin
-	  dram_cke      <= 1'b0;
 	  dram_cmd      <= cmd_desl;
 	  dram_a        <= 13'hxxxx;
 	  dram_ba       <= 2'bxx;
@@ -275,8 +274,6 @@ module sdram
        end
      else
        begin
-	  dram_cke <= 1'b1;	// Always true once out of reset
-
 	  // Default values
 	  // Note: dram_ba are preserved
 	  dram_a        <= 13'hxxxx;