fpga/Makefile: fix additional dependency generation issues

fpga/Makefile

@@ -29,7 +29,9 @@ PREREQFILES = $(outdir)/sram.mif
 alltarg := sof jic pow.rpt sta.rpt
 allout   = $(foreach o,$(alltarg),$(outdir)/$(1).$(o))
 
-.SUFFIXES: .targets
+sram_src = ../rv32/boot.bin
+
+.SUFFIXES:
 
 .SECONDARY:
 
@@ -39,6 +41,8 @@ all:
 	$(MAKE) prereq
 	$(MAKE) $(foreach rev,$(REVISIONS),$(rev).targets)
 
+-include $(foreach rev,$(REVISIONS),$(rev).deps)
+
 .PHONY: $(REVISIONS)
 $(REVISIONS):
 	$(MAKE) prereq
@@ -48,15 +52,13 @@ $(REVISIONS):
 %.targets:
 	$(MAKE) $(call allout,$*)
 
-$(outdir)/%.map.rpt: %.qsf %_map_deps
+$(outdir)/%.map.rpt: %.qsf | $(outdir)/sram.bin
 	$(QMAP) $(PROJECT) -c $*
 
 $(outdir)/%.fit.rpt: $(outdir)/%.map.rpt
 	$(QFIT) $(PROJECT) -c $*
 
-all_map_deps: $(foreach rev,$(REVISIONS),$(rev),$(rev)_map_deps)
-
-$(outdir)/sram.bin: ../rv32/boot.bin $(all_map_deps)
+$(outdir)/sram.bin: $(sram_src) $(all_map_deps)
 	LC_ALL=C date | tr '\n' '\0' | cat $< - > $@
 
 sram_depth  := 8192
@@ -65,7 +67,7 @@ sram_stride := 1
 $(outdir)/%.mif: $(outdir)/%.bin ../tools/bin2mif.pl
 	$(PERL) ../tools/bin2mif.pl $< $@ $($*_depth) $($*_width) $($*_stride)
 
-$(outdir)/%.mif_update.rpt: $(outdir)/%.fit.rpt $(outdir)/sram.mif
+$(outdir)/%.mif_update.rpt: $(outdir)/%.fit.rpt
 	$(QCDB) --update_mif $(PROJECT) -c $*
 
 $(outdir)/%.sof: $(outdir)/%.mif_update.rpt
@@ -90,8 +92,8 @@ prereq:
 # Clean out SignalTap
 signalclean:
 	for f in *.qsf; do \
-		$(PERL) -ne 'print unless (/(SIGNALTAP_FILE\b|\bENABLE_SIGNALTAP\b|\bSLD_FILE\b|SLD_NODE_)/);' < $$f > $$f.tmp &&
-		mv -f $$f.qsf.tmp $$f.qsf ;
+		$(PERL) -ne 'print unless (/(SIGNALTAP_FILE\b|\bENABLE_SIGNALTAP\b|\bSLD_FILE\b|SLD_NODE_)/);' < $$f > $$f.tmp && \
+		mv -f $$f.tmp $$f ; \
 	done
 
 # Programming targets. Environment JTAG_CABLE can override the default,
@@ -129,5 +131,3 @@ iodevs.vh: ../iodevs.conf ../tools/iodevs.pl
 
 # Verilog header dependencies
 max80.sv: iodevs.vh
-
--include $(foreach rev,$(REVISIONS),$(rev).deps)

fpga/scripts/qsfdeps.pl

@@ -45,7 +45,7 @@ sub read_file($) {
 
 	if ($name =~ /\.cof$/i) {
 	    $cof_list{$name}++;
-	} elsif ($type =~ /^(signaltap_file|use_signaltap_file|sld_file)$/i) {
+	} elsif ($type =~ /^(signaltap_file|use_signaltap_file|sld_file|cdf_file)$/i) {
 	    # Skip
 	} elsif ($type eq 'source_tcl_script_file' &&
 		 $name =~ /\.qsf$/i) {
@@ -60,11 +60,11 @@ sub read_file($) {
 }
 
 sub print_deps($$%) {
-    my($out,$target,%deps) = @_;
+    my($out,$prefix,%deps) = @_;
 
     return if (!%deps);
 
-    print $out "\n", $target, " :";
+    print $out "\n", $prefix;
 
     foreach my $dep (sort keys(%deps)) {
 	print $out " \\\n\t", $dep;
@@ -81,12 +81,15 @@ foreach my $f (@infiles) {
 
 open(my $out, '>', $outfile) or die;
 
-print_deps($out, $outfile, %dep_deps);
+print_deps($out, "${outfile} :", %dep_deps);
 
-my $asm_target = "$output_dir/$project.mif_update.rpt";
-print_deps($out, $asm_target, %asm_deps);
+print_deps($out, "${project}_asm_deps := ", %asm_deps);
+print $out "\n$output_dir/$project.mif_update.rpt: \$(${project}_asm_deps)\n";
+print $out "\nall_asm_deps += \$(${project}_asm_deps)\n";
 
-print_deps($out, "${project}_map_deps", %map_deps);
+print_deps($out, "${project}_map_deps := ", %map_deps);
+print $out "\n$output_dir/$project.map.rpt: \$(${project}_map_deps)\n";
+print $out "\nall_map_deps += \$(${project}_map_deps)\n";
 
 close($out);