3 tahun lalu · 6b8d647c0a
--- a/fpga/output_files/max80.jam
+++ b/fpga/output_files/max80.jam
--- a/fpga/output_files/max80.jbc
+++ b/fpga/output_files/max80.jbc
--- a/fpga/output_files/max80.jic
+++ b/fpga/output_files/max80.jic
--- a/fpga/output_files/max80.map
+++ b/fpga/output_files/max80.map
@@ -11,7 +11,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
				 
			
 
				 Notes:
			
 
				 
			
 
				-- Data checksum for this conversion is 0xF3760FE4
			
 
				+- Data checksum for this conversion is 0xF3761139
			
 
				 
			
 
				 - All the addresses in this file are byte addresses
			
 
				 
			
--- a/fpga/output_files/max80.pof
+++ b/fpga/output_files/max80.pof
--- a/fpga/output_files/max80.sof
+++ b/fpga/output_files/max80.sof
--- a/fw/boot.mif
+++ b/fw/boot.mif
@@ -4,7 +4,7 @@ WIDTH = 32;
 
				 ADDRESS_RADIX = HEX;
			
 
				 DATA_RADIX = HEX;
			
 
				 CONTENT BEGIN
			
 
				-0000 : 00002137;
			
 
				+0000 : 00008137;
			
 
				 0001 : 31E0006F;
			
 
				 0002 : 00000000;
			
 
				 0003 : 00000000;
			
--- a/fw/sys.h
+++ b/fw/sys.h
@@ -1,6 +1,6 @@
 
				 #ifndef SYS_H
			
 
				 #define SYS_H
			
 
				 
			
 
				-#define SRAM_SIZE	8192	/* Size of builtin SRAM */
			
 
				+#define SRAM_SIZE	32768	/* Size of builtin SRAM */
			
 
				 
			
 
				 #endif /* SYS_H */