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fw: allow optimization if IRQ_VECTORS < 32

No need to scan for bits that can't exist if IRQ_VECTORS is smaller
than that specific number.
H. Peter Anvin 3 years ago
parent
commit
74ebfc9b60
3 changed files with 21 additions and 4 deletions
  1. 0 2
      fw/fw.h
  2. 13 2
      fw/irqasm.S
  3. 8 0
      fw/sys.h

+ 0 - 2
fw/fw.h

@@ -19,8 +19,6 @@ extern void *_sbrk(size_t);
 
 extern int disk_init(void);
 
-#define IRQ_VECTORS	32
-
 typedef void (*irq_handler_t)(unsigned int vector);
 extern irq_handler_t
 register_irq(unsigned int vector, irq_handler_t handler, bool enable);

+ 13 - 2
fw/irqasm.S

@@ -1,9 +1,10 @@
 #include "picorv32.h"
+#include "sys.h"
 
 	// The IRQ dispatch code is written in assembly to make
 	// better use of the register bank switching: can simply
 	// use the saved registers here, no saving needed.
-	// registers need to be 
+	// registers need to be
 	.pushsection ".init.irq","ax"
 	.balign 4
 	.globl _irq
@@ -11,37 +12,47 @@
 	.option norvc	// Alignment matters more here
 _irq:
 	addqxi sp,sp,0
-	
+
 	// s10 contains the IRQ return address, s11 the mask of
 	// IRQs to be handled.
 	li s1, 0
 .Lirq_loop:
 	// ctz would make this more efficient...
+#if IRQ_VECTORS > 16
 	slli t0,s11,16
 	bnez t0,1f
 	srli s11,s11,16
 	addi s1,s1,16*4
 1:
+#endif
+#if IRQ_VECTORS > 8
 	zext.b t0,s11
 	bnez t0,2f
 	srli s11,s11,8
 	addi s1,s1,8*4
 2:
+#endif
+#if IRQ_VECTORS > 4
 	andi t0,s11,15
 	bnez t0,3f
 	srli s11,s11,4
 	addi s1,s1,4*4
 3:
+#endif
+#if IRQ_VECTORS > 2
 	andi t0,s11,3
 	bnez t0,4f
 	srli s11,s11,2
 	addi s1,s1,2*4
 4:
+#endif
+#if IRQ_VECTORS > 1
 	andi t0,s11,1
 	bnez t0,5f
 	srli s11,s11,1
 	addi s1,s1,1*4
 5:
+#endif
 	// __irq_handler_table must be in the zero page
 	// However, prevent the linker from incorrectly relaxing
 	// this instruction.

+ 8 - 0
fw/sys.h

@@ -1,6 +1,11 @@
 #ifndef SYS_H
 #define SYS_H
 
+/*
+ * Various constants that need to match the hardware configuration.
+ * This file must be includable from assembly and from a linker script.
+ */
+
 #define SRAM_ADDR	0
 #define SRAM_ADDR_BITS	15
 #define SRAM_SIZE      (0x1 << SRAM_ADDR_BITS)
@@ -21,4 +26,7 @@
 #define _PC_RESET	0
 #define _PC_IRQ		0x20
 
+/* IRQ vectors not including permanently masked vectors at the top */
+#define IRQ_VECTORS	32
+
 #endif /* SYS_H */