abcbus: not busy until the transaction has completed

We are not "busy" until the transaction has completed. Otherwise we
start holding WAIT# already during the previous cycle!

fpga/abcbus.sv

@@ -363,18 +363,27 @@ module abcbus (
    //
    reg [9:0] busy_status;
    reg [9:0] busy_mask;
+   reg [9:0] busy_io_q;
    reg [1:0] inp_en;
    reg [3:0] bus_change_status;
    reg [3:0] bus_change_mask;
 
-   wire [9:0] busy_io = { abc_inp[1:0], abc_rst, 1'b0,
+   wire [9:0] is_io = { abc_inp[1:0], abc_rst, 1'b0,
 			  abc_out[4:1], abc_cs, abc_out[0] };
 
-   wire [9:0] set_busy = busy_io & busy_mask;
+   wire [9:0] busy_io = is_io & busy_mask;
    wire       is_busy = |(busy_status & busy_mask);
 
    wire [9:0] busy_valid = 10'b11_1011_1111;
 
+   wire [9:0] set_busy = busy_io_q & ~busy_io;
+
+   always @(posedge sys_clk or negedge rst_n)
+     if (~rst_n)
+       busy_io_q <= 10'b0;
+     else
+       busy_io_q <= busy_io;
+
    // WAIT# logic
    reg	      abc_wait_force = 1'b0; // Not cleared on internal reset!