usb: set the device serial number

Set the USB device serial number string from the ROM serial number.

fpga/iodevs.vh

@@ -59,6 +59,10 @@
 	wire [ 0:0] iodev_valid_abcmemmap = xdev_valid[0:0];
 	tri1 [ 0:0] iodev_wait_n_abcmemmap;
 
+	wire [31:0] iodev_rdata_usbdesc;
+	wire [ 0:0] iodev_valid_usbdesc = xdev_valid[1:1];
+	tri1 [ 0:0] iodev_wait_n_usbdesc;
+
 	wire [31:0] iodev_rdata_random;
 	wire [ 0:0] iodev_irq_random;
 	wire [ 0:0] iodev_valid_random = iodev_valid[8:8];
@@ -68,6 +72,7 @@
 	always_comb
 		case (cpu_mem_addr[29:28])
 			2'd0:	 iodev_rdata = iodev_rdata_abcmemmap;
+			2'd1:	 iodev_rdata = iodev_rdata_usbdesc;
 			2'd3:
 			case (cpu_mem_addr[10:7])
 				4'd0:	 iodev_rdata = iodev_rdata_sys;
@@ -106,4 +111,5 @@
 		(&iodev_wait_n_esp) & 
 		(&iodev_wait_n_abc) & 
 		(&iodev_wait_n_abcmemmap) & 
+		(&iodev_wait_n_usbdesc) & 
 		(&iodev_wait_n_random);

fpga/max80.sv

@@ -721,9 +721,18 @@ module max80
    max80_usb usb (
 		  .rst_n         ( hard_rst_n ),
 		  .clock48       ( usb_clk ),
+
+		  .sys_clk       ( sys_clk ),
+		  .cpu_valid     ( iodev_valid_usbdesc ),
+		  .cpu_addr      ( cpu_mem_addr[17:2] ),
+		  .cpu_rdata     ( iodev_rdata_usbdesc ),
+		  .cpu_wdata     ( cpu_mem_wdata ),
+		  .cpu_wstrb     ( cpu_mem_wstrb ),
+
 		  .tty_rxd       ( ),
 		  .tty_rxd_break ( usb_rxd_break ),
 		  .tty_txd       ( tty_data_out ),
+
 		  .usb_dp        ( usb_dp ),
 		  .usb_dn        ( usb_dn ),
 		  .usb_pu        ( usb_pu ),

fpga/usb/usb.sv

@@ -6,18 +6,25 @@
 //
 
 module max80_usb (
-		  input  rst_n,
-		  input  clock48,
-
-		  output tty_rxd,
-		  output tty_rxd_break,
-		  input  tty_txd,
-
-		  inout  usb_dp,	// Single ended D+
-		  inout  usb_dn,	// Single ended D-
-		  input  usb_rx,	// Differential input
-		  input  usb_rx_ok,	// Differential input available
-		  output usb_pu		// Driver for 1.5 kohm pullup
+		  input		rst_n,
+		  input		clock48,
+
+		  input		sys_clk,
+		  input		cpu_valid,
+		  input [15:0]	cpu_addr,
+		  output [31:0] cpu_rdata,
+		  input [31:0]	cpu_wdata,
+		  input [3:0]	cpu_wstrb,
+
+		  output	tty_rxd,
+		  output	tty_rxd_break,
+		  input		tty_txd,
+
+		  inout		usb_dp, // Single ended D+
+		  inout		usb_dn, // Single ended D-
+		  input		usb_rx, // Differential input
+		  input		usb_rx_ok, // Differential input available
+		  output	usb_pu		// Driver for 1.5 kohm pullup
 		  );
 
    //
@@ -40,7 +47,7 @@ module max80_usb (
    //
    // USB hardware interface to PHY
    //
-   wire 		 usb_rx_rcv = usb_rx_ok ? usb_rx : usb_dp & ~usb_dn;
+   wire			 usb_rx_rcv = usb_rx_ok ? usb_rx : usb_dp & ~usb_dn;
    wire			 usb_rx_dp  = usb_dp;
    wire			 usb_rx_dn  = usb_dn;
    wire			 usb_tx_dp;
@@ -113,6 +120,13 @@ module max80_usb (
 	       .utmi_rxerror_i    ( utmi_rxerror ),
 	       .utmi_linestate_i  ( utmi_linestate ),
 
+	       .sys_clk           ( sys_clk ),
+	       .cpu_valid         ( cpu_valid ),
+	       .cpu_addr          ( cpu_addr ),
+	       .cpu_rdata         ( cpu_rdata ),
+	       .cpu_wdata         ( cpu_wdata ),
+	       .cpu_wstrb         ( cpu_wstrb ),
+
 	       .tx_i              ( tty_txd ),
 	       .rx_o              ( tty_rxd ),
 	       .rx_break_o        ( tty_rxd_break )

fpga/usb/usb_desc.v

@@ -3,15 +3,16 @@
  * Trust the tools to figure out if we don't need part of the whole thing.
  */
 module usb_desc_rom (
-       input clk,
+	input clk,
 
-       input [7:0] usb_addr,
-       output [7:0] usb_rdata,
+	input [7:0] usb_addr,
+	output [7:0] usb_rdata,
 
-       input [7:0] cpu_addr,
-       output [7:0] cpu_rdata,
-       input [7:0] cpu_wdata,
-       input cpu_wren
+	input cpu_clk,
+	input [7:0] cpu_addr,
+	output [7:0] cpu_rdata,
+	input [7:0] cpu_wdata,
+	input cpu_wren
 );
 
 	reg [7:0] rom [0:255];
@@ -225,6 +226,9 @@ module usb_desc_rom (
 
 	always @(posedge clk) begin
 		usb_rdata <= rom[usb_addr];
+	end
+
+	always @(posedge cpu_clk) begin
 		cpu_rdata <= rom[cpu_addr];
 		if (cpu_wren)
 			rom[cpu_addr] <= cpu_wdata;

fpga/usb/usb_serial/src_v/usb_cdc_core.sv

@@ -37,31 +37,39 @@
 module usb_cdc_core
   (
    // Inputs
-   input clk_i
-   ,input rst_i
-   ,input enable_i
-   ,input [ 7:0] utmi_data_in_i
-   ,input utmi_txready_i
-   ,input utmi_rxvalid_i
-   ,input utmi_rxactive_i
-   ,input utmi_rxerror_i
-   ,input [ 1:0] utmi_linestate_i
-   ,input inport_valid_i
-   ,input [ 7:0] inport_data_i
-   ,input outport_accept_i
-
-   // Outputs
-   ,output [ 7:0] utmi_data_out_o
-   ,output utmi_txvalid_o
-   ,output [ 1:0] utmi_op_mode_o
-   ,output [ 1:0] utmi_xcvrselect_o
-   ,output utmi_termselect_o
-   ,output utmi_dppulldown_o
-   ,output utmi_dmpulldown_o
-   ,output inport_accept_o
-   ,output outport_valid_o
-   ,output [ 7:0] outport_data_o
-   ,output outport_break_o
+   input	 clk_i
+		 ,input rst_i
+		 ,input enable_i
+		 ,input [ 7:0] utmi_data_in_i
+		 ,input utmi_txready_i
+		 ,input utmi_rxvalid_i
+		 ,input utmi_rxactive_i
+		 ,input utmi_rxerror_i
+		 ,input [ 1:0] utmi_linestate_i
+		 ,input inport_valid_i
+		 ,input [ 7:0] inport_data_i
+		 ,input outport_accept_i
+
+		 // Outputs
+		 ,output [ 7:0] utmi_data_out_o
+		 ,output utmi_txvalid_o
+		 ,output [ 1:0] utmi_op_mode_o
+		 ,output [ 1:0] utmi_xcvrselect_o
+		 ,output utmi_termselect_o
+		 ,output utmi_dppulldown_o
+		 ,output utmi_dmpulldown_o
+		 ,output inport_accept_o
+		 ,output outport_valid_o
+		 ,output [ 7:0] outport_data_o
+		 ,output outport_break_o,
+
+   // CPU bus
+   input	 sys_clk,
+   input	 cpu_valid,
+   input [15:0]  cpu_addr,
+   output [31:0] cpu_rdata,
+   input [31:0]  cpu_wdata,
+   input [3:0]	 cpu_wstrb
    );
 
    parameter USB_SPEED_HS = "False"; // True or False
@@ -506,7 +514,7 @@ module usb_cdc_core
    //-----------------------------------------------------------------
    reg	       ctrl_stall_r; // Send STALL
    reg	       ctrl_ack_r;   // Send STATUS (ZLP)
-   reg 	       ctrl_send_data_r;
+   reg	       ctrl_send_data_r;
 
    reg [15:0]  desc_base_addr_r;
    reg [15:0]  desc_len_r;
@@ -535,7 +543,7 @@ module usb_cdc_core
 	      .addr (desc_base_addr_r),
 	      .len  (desc_len_r)
 	      );
-   
+
    always @ *
      begin
 	ctrl_stall_r    = 1'b0;
@@ -692,9 +700,9 @@ module usb_cdc_core
    reg        ctrl_sending_r;
    reg [15:0] ctrl_send_idx_r;
 
-   reg 	      ctrl_sending_zlp_r;
-   reg 	      ctrl_sending_zlp_q;
-   
+   reg	      ctrl_sending_zlp_r;
+   reg	      ctrl_sending_zlp_q;
+
    reg        ctrl_txvalid_q;
    reg [7:0]  ctrl_txdata_q;
    reg        ctrl_txstrb_q;
@@ -790,7 +798,7 @@ module usb_cdc_core
 		  ctrl_txstrb_r  = 1'b1;
 		  ctrl_txlast_r  = &(ctrl_send_idx_r[5:0]
 				     | { {3{~usb_hs_w}}, 3'b0 });
-		  
+
 		  // Advance to next data item
 		  ctrl_send_idx_r = ctrl_send_idx_r + 16'd1;
 		  desc_addr_r     = desc_addr_r + 1'b1;
@@ -876,13 +884,15 @@ module usb_cdc_core
 	.usb_addr	(desc_addr_r),
 	.usb_rdata	(desc_data_w),
 
-	// CPU interface for modifications - not used yet
-	.cpu_addr	('bx),
-	.cpu_rdata	( ),
-	.cpu_wdata	('bx),
-	.cpu_wren	(1'b0)
+	// CPU interface for modifications
+	.cpu_clk        (sys_clk),
+	.cpu_addr	(cpu_addr),
+	.cpu_rdata	(cpu_rdata[7:0]),
+	.cpu_wdata	(cpu_wdata[7:0]),
+	.cpu_wren	(cpu_valid & cpu_wstrb[0])
 	);
-   
+   assign cpu_rdata[31:8] = 24'bx;
+
    //-----------------------------------------------------------------
    // Unused Endpoint Downstream Signals
    //-----------------------------------------------------------------

fpga/usb/usb_serial/src_v/usb_cdc_top.v

@@ -9,26 +9,26 @@
 //                         License: LGPL
 //-----------------------------------------------------------------
 //
-// This source file may be used and distributed without         
-// restriction provided that this copyright statement is not    
-// removed from the file and that any derivative work contains  
-// the original copyright notice and the associated disclaimer. 
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
 //
-// This source file is free software; you can redistribute it   
-// and/or modify it under the terms of the GNU Lesser General   
-// Public License as published by the Free Software Foundation; 
-// either version 2.1 of the License, or (at your option) any   
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
 // later version.
 //
-// This source is distributed in the hope that it will be       
-// useful, but WITHOUT ANY WARRANTY; without even the implied   
-// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-// PURPOSE.  See the GNU Lesser General Public License for more 
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE.  See the GNU Lesser General Public License for more
 // details.
 //
-// You should have received a copy of the GNU Lesser General    
-// Public License along with this source; if not, write to the 
-// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
+// You should have received a copy of the GNU Lesser General
+// Public License along with this source; if not, write to the
+// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
 // Boston, MA  02111-1307  USA
 //-----------------------------------------------------------------
 
@@ -47,27 +47,34 @@ module usb_cdc_top
 // Ports
 //-----------------------------------------------------------------
 (
-     input 	  clk_i,
-     input 	  rst_i,
-
-     output [7:0] utmi_data_out_o,
-     output 	  utmi_txvalid_o,
-     output [1:0] utmi_op_mode_o,
-     output [1:0] utmi_xcvrselect_o,
-     output 	  utmi_termselect_o,
-     output 	  utmi_dppulldown_o,
-     output 	  utmi_dmpulldown_o,
-
-     input [7:0]  utmi_data_in_i,
-     input 	  utmi_txready_i,
-     input 	  utmi_rxvalid_i,
-     input 	  utmi_rxactive_i,
-     input 	  utmi_rxerror_i,
-     input [1:0]  utmi_linestate_i,
-
-     input 	  tx_i,
-     output 	  rx_o,
-     output       rx_break_o
+     input	   clk_i,
+     input	   rst_i,
+
+     output [7:0]  utmi_data_out_o,
+     output	   utmi_txvalid_o,
+     output [1:0]  utmi_op_mode_o,
+     output [1:0]  utmi_xcvrselect_o,
+     output	   utmi_termselect_o,
+     output	   utmi_dppulldown_o,
+     output	   utmi_dmpulldown_o,
+
+     input [7:0]   utmi_data_in_i,
+     input	   utmi_txready_i,
+     input	   utmi_rxvalid_i,
+     input	   utmi_rxactive_i,
+     input	   utmi_rxerror_i,
+     input [1:0]   utmi_linestate_i,
+
+     input	   sys_clk,
+     input	   cpu_valid,
+     input [15:0]  cpu_addr,
+     output [31:0] cpu_rdata,
+     input [31:0]  cpu_wdata,
+     input [3:0]   cpu_wstrb,
+
+     input	   tx_i,
+     output	   rx_o,
+     output	   rx_break_o
 );
 
 wire  [  7:0]  usb_rx_data_w;
@@ -107,7 +114,15 @@ u_usb
     ,.inport_accept_o(usb_tx_accept_w)
     ,.outport_valid_o(usb_rx_valid_w)
     ,.outport_data_o(usb_rx_data_w)
-    ,.outport_break_o(usb_rx_break_w)
+    ,.outport_break_o(usb_rx_break_w),
+
+ // CPU bus
+ .sys_clk           ( sys_clk ),
+ .cpu_valid         ( cpu_valid ),
+ .cpu_addr          ( cpu_addr ),
+ .cpu_rdata         ( cpu_rdata ),
+ .cpu_wdata         ( cpu_wdata ),
+ .cpu_wstrb         ( cpu_wstrb )
 );
 
 //-----------------------------------------------------------------
@@ -181,9 +196,6 @@ localparam   START_BIT = 4'd0;
 localparam   STOP_BIT0 = 4'd9;
 localparam   STOP_BIT1 = 4'd10;
 
-// Xilinx placement pragmas:
-//synthesis attribute IOB of txd_q is "TRUE"
-
 // TX Signals
 reg          tx_busy_q;
 reg [3:0]    tx_bits_q;
@@ -271,7 +283,7 @@ begin
             rx_busy_q <= 1'b0;
     end
     // Rx shift register
-    else 
+    else
         rx_shift_reg_q <= {rxd_q, rx_shift_reg_q[7:1]};
 end
 // Start bit?

iodevs.conf

@@ -36,5 +36,6 @@ our @iodevs = (
     { -name => 'esp',       -irq => 'l' },
     { -name => 'abc',       -irq => 'l' },
     { -name => 'abcmemmap', -xdev => 1 },
+    { -name => 'usbdesc',   -xdev => 1 },
     { -name => 'random',    -irq => 'l' }
 );

rv32/boot.mif

@@ -60,7 +60,7 @@ CONTENT BEGIN
 0035 : 4E00006F;
 0036 : 34E0006F;
 0037 : 00000000;
-0038 : 4101D980;
+0038 : 4101D990;
 0039 : 00000000;
 003A : FFFFFFFF;
 003B : FFFFFFFF;
@@ -132,7 +132,7 @@ CONTENT BEGIN
 007D : 866317A0;
 007E : 70970002;
 007F : 80E74000;
-0080 : 547D6480;
+0080 : 547D6600;
 0081 : 0680008B;
 0082 : 0810878B;
 0083 : 17B04303;
@@ -140,7 +140,7 @@ CONTENT BEGIN
 0085 : 40001097;
 0086 : 2D0080E7;
 0087 : 40002097;
-0088 : 646080E7;
+0088 : 660080E7;
 0089 : 0000B7C5;
 008A : 00000697;
 008B : E7468693;
@@ -357,7 +357,7 @@ CONTENT BEGIN
 015E : 85B74000;
 015F : 05134000;
 0160 : 889310C0;
-0161 : 0613FC85;
+0161 : 0613FE05;
 0162 : 22230008;
 0163 : 86330EA0;
 0164 : 458140C8;
@@ -365,10 +365,10 @@ CONTENT BEGIN
 0166 : 8EB7B5D5;
 0167 : 4FB74000;
 0168 : 8F134001;
-0169 : 8793FC8E;
-016A : 85B3978F;
+0169 : 8793FE0E;
+016A : 85B3990F;
 016B : 851341E7;
-016C : BF05FC8E;
+016C : BF05FE0E;
 016D : CE061101;
 016E : CC22CA26;
 016F : C64EC84A;
@@ -461,7 +461,7 @@ CONTENT BEGIN
 01C6 : FE3703F5;
 01C7 : 9A134000;
 01C8 : 0E930028;
-01C9 : 8F33E28E;
+01C9 : 8F33E40E;
 01CA : 2A83014E;
 01CB : 0A23000F;
 01CC : A0230F10;
@@ -494,7 +494,7 @@ CONTENT BEGIN
 01E7 : F9B7B910;
 01E8 : 2A234000;
 01E9 : 4401B800;
-01EA : E2898993;
+01EA : E4098993;
 01EB : 10000A13;
 01EC : 00898E33;
 01ED : 000E2503;
@@ -611,9 +611,9 @@ CONTENT BEGIN
 025C : 63654420;
 025D : 20363220;
 025E : 31323032;
-025F : 3A353120;
-0260 : 353A3832;
-0261 : 00000A36;
+025F : 3A363120;
+0260 : 353A3033;
+0261 : 00000A37;
 0262 : 00000101;
 0263 : 00000000;
 0264 : 00000000;
@@ -634,13 +634,13 @@ CONTENT BEGIN
 0273 : 00007FBF;
 0274 : 00000000;
 0275 : D3030300;
-0276 : 4000300E;
+0276 : 40003028;
 0277 : 00000000;
-0278 : 40003032;
+0278 : 4000304C;
 0279 : 00000000;
 027A : 00000000;
 027B : 00000000;
-027C : 40003020;
+027C : 4000303A;
 027D : 00000000;
 027E : 00000000;
 027F : 00000000;

rv32/ioregs.h

@@ -19,6 +19,8 @@
 #define IODEVH(d,r) IODEVV(d,r,0)
 #define IODEVL(d,r) IODEVV(d,r,0)
 
+#define PTR(x)	    x
+
 #else
 
 /* Writable registers */
@@ -45,6 +47,8 @@
 #define IODEVRH1(d,r) (*(const volatile uint16_t *)IODEVA(d,r,2))
 #define IODEVRL(d,r)  (*(const volatile uint32_t *)IODEVA(d,r,0))
 
+#define PTR(x) (&(x))
+
 #endif
 
 #define CPU_HZ			84000000
@@ -160,4 +164,7 @@
 
 #define RANDOM_DATA		IODEVRL(RANDOM,0)
 
+#define USBDESC_ROM		IODEVL(USBDESC,0)
+#define usbdesc_rom		PTR(USBDESC_ROM)
+
 #endif /* IODEV_H */

rv32/romcopy.c

@@ -123,10 +123,13 @@ uint64_t rom_get_serial(void)
     serial_str[12] = '\0';
     uint64_t v = o.q;
     for (int i = 11; i >= 0; i--) {
+	unsigned char c;
 	unsigned int d = v % 36;
 	v /= 36;
 
-	serial_str[i] = d + '0' + ('A'-'0'-10)*(d >= 10);
+	c = d + '0' + ('A'-'0'-10)*(d >= 10);
+	serial_str[i] = c;
+	usbdesc_rom[2+2*i] = c;
     }
 
     if ( 1 )

tools/usbdescgen.pl

@@ -700,15 +700,16 @@ sub output_verilog($) {
  * Trust the tools to figure out if we don't need part of the whole thing.
  */
 module ${module_name}_rom (
-       input clk,
+	input clk,
 
-       input [$amax:0] usb_addr,
-       output [7:0] usb_rdata,
+	input [$amax:0] usb_addr,
+	output [7:0] usb_rdata,
 
-       input [$amax:0] cpu_addr,
-       output [7:0] cpu_rdata,
-       input [7:0] cpu_wdata,
-       input cpu_wren
+	input cpu_clk,
+	input [$amax:0] cpu_addr,
+	output [7:0] cpu_rdata,
+	input [7:0] cpu_wdata,
+	input cpu_wren
 );
 
 	reg [7:0] rom [0:$bmax];
@@ -729,6 +730,9 @@ EOF
 
 	always \@(posedge clk) begin
 		usb_rdata <= rom[usb_addr];
+	end
+
+	always \@(posedge cpu_clk) begin
 		cpu_rdata <= rom[cpu_addr];
 		if (cpu_wren)
 			rom[cpu_addr] <= cpu_wdata;