fpga: dirty bit tracking for SDRAM

Add a tracking RAM for page-granularity dirty bits for the SDRAM;
these work both for CPU and DMA access.

common/iodevs.conf

@@ -45,5 +45,7 @@ our @iodevs = (
     { -name => 'esp',       -irq => 'l' },
     { -name => 'random',    -irq => 'l' },
 
+    { -name => 'dirty',	    -xdev => 1 },
+
     { -name => 'vjtag',     -irq => 'e' }
 );

fpga/dirty.sv

@@ -0,0 +1,44 @@
+//
+// dirty.sv
+//
+// SDRAM dirty bit
+//
+// Tracks dirty SDRAM pages on a 4K granularity. Currently accessed
+// from the CPU one bit at a time, but could be improved.
+// W1C semantics from the CPU.
+//
+
+module dirty
+  #(parameter pagebits = 13,
+    parameter pages = 1 << pagebits
+    )
+   (
+    input		 rst_n,
+    input		 clk,
+    input [pagebits-1:0] dirty_pg,
+    input		 dirty_stb,
+
+    input  [31:2]	 cpu_addr,
+    input  [ 3:0]	 cpu_wstrb,
+    input  [31:0]	 cpu_wdata,
+    output [31:0]	 cpu_rdata
+    );
+
+   assign cpu_rdata[31:1] = 'b0;
+
+   dirtyram ram (
+		 .clock (clk),
+
+		 .address_a	(cpu_addr[pagebits+1:2]),
+		 .data_a	(1'b0),
+		 .wren_a	(cpu_wstrb[0] & cpu_wdata[0]),
+		 .q_a		(cpu_rdata[0]),
+		 .rden_a	(1'b1),
+
+		 .address_b	(dirty_pg),
+		 .data_b	(1'b1),
+		 .wren_b	(dirty_stb),
+		 .q_b		( ),
+		 .rden_b	(1'b0)
+		 );
+endmodule

fpga/ip/dirtyram.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "22.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dirtyram.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dirtyram_inst.v"]

fpga/ip/dirtyram.v

@@ -0,0 +1,253 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: dirtyram.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2023  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module dirtyram (
+	address_a,
+	address_b,
+	clock,
+	data_a,
+	data_b,
+	rden_a,
+	rden_b,
+	wren_a,
+	wren_b,
+	q_a,
+	q_b);
+
+	input	[12:0]  address_a;
+	input	[12:0]  address_b;
+	input	  clock;
+	input	[0:0]  data_a;
+	input	[0:0]  data_b;
+	input	  rden_a;
+	input	  rden_b;
+	input	  wren_a;
+	input	  wren_b;
+	output	[0:0]  q_a;
+	output	[0:0]  q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden_a;
+	tri1	  rden_b;
+	tri0	  wren_a;
+	tri0	  wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [0:0] sub_wire0;
+	wire [0:0] sub_wire1;
+	wire [0:0] q_a = sub_wire0[0:0];
+	wire [0:0] q_b = sub_wire1[0:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address_a),
+				.address_b (address_b),
+				.clock0 (clock),
+				.data_a (data_a),
+				.data_b (data_b),
+				.rden_a (rden_a),
+				.rden_b (rden_b),
+				.wren_a (wren_a),
+				.wren_b (wren_b),
+				.q_a (sub_wire0),
+				.q_b (sub_wire1),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.eccstatus ());
+	defparam
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.indata_reg_b = "CLOCK0",
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 8192,
+		altsyncram_component.numwords_b = 8192,
+		altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.outdata_reg_b = "CLOCK0",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
+		altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
+		altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
+		altsyncram_component.widthad_a = 13,
+		altsyncram_component.widthad_b = 13,
+		altsyncram_component.width_a = 1,
+		altsyncram_component.width_b = 1,
+		altsyncram_component.width_byteena_a = 1,
+		altsyncram_component.width_byteena_b = 1,
+		altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "1"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "1"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 13 0 INPUT NODEFVAL "address_a[12..0]"
+// Retrieval info: USED_PORT: address_b 0 0 13 0 INPUT NODEFVAL "address_b[12..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data_a 0 0 1 0 INPUT NODEFVAL "data_a[0..0]"
+// Retrieval info: USED_PORT: data_b 0 0 1 0 INPUT NODEFVAL "data_b[0..0]"
+// Retrieval info: USED_PORT: q_a 0 0 1 0 OUTPUT NODEFVAL "q_a[0..0]"
+// Retrieval info: USED_PORT: q_b 0 0 1 0 OUTPUT NODEFVAL "q_b[0..0]"
+// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
+// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 13 0 address_a 0 0 13 0
+// Retrieval info: CONNECT: @address_b 0 0 13 0 address_b 0 0 13 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 1 0 data_a 0 0 1 0
+// Retrieval info: CONNECT: @data_b 0 0 1 0 data_b 0 0 1 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
+// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 1 0 @q_a 0 0 1 0
+// Retrieval info: CONNECT: q_b 0 0 1 0 @q_b 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL dirtyram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dirtyram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dirtyram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dirtyram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dirtyram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL dirtyram_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf

fpga/max80.qsf

@@ -236,6 +236,9 @@ set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
 set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
 set_global_assignment -name SYSTEMVERILOG_FILE video.sv
 set_global_assignment -name SYSTEMVERILOG_FILE esp.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sam.sv
+set_global_assignment -name SYSTEMVERILOG_FILE dirty.sv
+set_global_assignment -name VERILOG_FILE ip/dirtyram.v
 set_global_assignment -name SDC_FILE max80.sdc
 set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl

fpga/max80.sv

@@ -396,6 +396,10 @@ module max80
    wire [ 1:0] sdram_rom_wrq;
    wire        sdram_rom_wacc;
 
+   // Dirty page tracking
+   wire [12:0] sdram_dirty_pg;
+   wire	       sdram_dirty_stb;
+
    sdram #(.port1_count(dram_port_count))
    sdram (
 	  .rst_n    ( rst_n ),
@@ -417,9 +421,24 @@ module max80
 	  .a2       ( sdram_rom_waddr ),
 	  .wd2      ( sdram_rom_wd ),
 	  .wrq2     ( sdram_rom_wrq ),
-	  .wacc2    ( sdram_rom_wacc )
+	  .wacc2    ( sdram_rom_wacc ),
+
+	  .dirty_pg ( sdram_dirty_pg ),
+	  .dirty_stb ( sdram_dirty_stb )
 	  );
 
+   // Dirty page memory
+   dirty sdram_dirty (
+		      .rst_n     ( rst_n ),
+		      .clk       ( sdram_clk ),
+		      .dirty_pg  ( sdram_dirty_pg ),
+		      .dirty_stb ( sdram_dirty_stb ),
+		      .cpu_addr  ( cpu_mem_addr ),
+		      .cpu_wstrb ( cpu_mem_wstrb ),
+		      .cpu_wdata ( cpu_mem_wdata ),
+		      .cpu_rdata ( iodev_rdata_dirty )
+		      );
+
    //
    // ABC-bus interface
    //

fpga/sdram.sv

@@ -293,7 +293,11 @@ module sdram
 	      input [24:1]  a2,
 	      input [15:0]  wd2,
 	      input [1:0]   wrq2,
-	      output reg    wacc2 // Data accepted, advance data & addr
+	      output reg    wacc2, // Data accepted, advance data & addr
+
+	      // Output for dirty page tracking
+	      output [12:0] dirty_pg,	// 4K page
+	      output reg    dirty_stb	// Mark page dirty (one cycle strobe)
 	      );
 
 `include "functions.sv"		// For modelsim
@@ -411,13 +415,16 @@ module sdram
    reg [24:0] addr;
    reg	      wrq2_more;
 
-   wire [13:0] row_addr  = addr[24:12];
+   wire [12:0] row_addr  = addr[24:12];
    wire  [1:0] bank_addr = addr[11:10];
    wire  [8:0] col_addr  = addr[9:1];
    assign p1.addr0       = addr[0];
 
    assign p1.rd = dram_q;
 
+   // Page for dirty page tracking. This must not include col_addr bits.
+   assign dirty_pg = addr[24:12];
+
    //
    // Careful with the timing here... there is one cycle between
    // registers and wires, and the DRAM observes the clock 1/2
@@ -448,6 +455,8 @@ module sdram
 	  wacc2         <= 1'b0;
 	  wrq2_more     <= 1'bx;
 
+	  dirty_stb	<= 1'b0;
+
 	  wdata_q       <= 32'hxxxx_xxxx;
 	  be_q          <= 4'bxxxx;
 	  addr          <= 25'bx;
@@ -467,6 +476,8 @@ module sdram
 	  p1.rstrb      <= 2'b00;
 	  wacc2         <= 1'b0;
 
+	  dirty_stb     <= 1'b0;
+
 	  op_ctr  <= op_ctr + 1'b1;
 	  op_zero <= &op_cycle; // About to wrap around
 
@@ -537,6 +548,7 @@ module sdram
 		   begin
 		      addr         <= p1.addr;
 		      p1.wrack     <= |p1.wstrb;
+		      dirty_stb    <= |p1.wstrb;
 		      wdata_q      <= p1.wd;
 		      be_q         <= p1.wstrb;
 		      state        <= st_rd_wr_act;
@@ -547,6 +559,7 @@ module sdram
 		      // Begin port 2 write
 		      addr         <= { a2, 1'b0 };
 		      state        <= st_wr2_act;
+		      dirty_stb    <= 1'b1;
 		   end
 	      end // case: st_ready
 
@@ -558,14 +571,14 @@ module sdram
 	      end
 
 	    st_rd_wr_act: begin
-	       op_ctr  <= 6'b0;
-	       op_zero <= 1'b0;
+	       op_ctr   <= 6'b0;
+	       op_zero  <= 1'b0;
 
-	       dram_cmd <= cmd_act;
-	       dram_a   <= row_addr;
-	       dram_ba  <= bank_addr;
+	       dram_cmd  <= cmd_act;
+	       dram_a    <= row_addr;
+	       dram_ba   <= bank_addr;
 
-	       state    <= st_rd_wr;
+	       state     <= st_rd_wr;
 	    end
 
 	    st_rd_wr: