v2: abc_host and abc_a_oe are redundant and unified in v2

The signals abc_host and abc_a_oe are fundamentally redundant. Unify
them under the name abc_host, and make abc_a_oe an explicit alias in
the v1.sv top level file.

The actual pin assignment in v2 is the one for "abc_a_oe" (schematic
wire AD16), but abc_host makes more sense as a common name.

fpga/abcbus.sv

@@ -39,7 +39,6 @@ module abcbus (
 	       inout		 abc_xm_x, // System memory override (ABC800)
 	       // Host/device control
 	       output		 abc_host, // 1 = host, 0 = device
-	       output reg	 abc_a_oe,
 
 	       // ABC-bus extension header
 	       // (Note: cannot use an array here because HC and HH are
@@ -95,7 +94,6 @@ module abcbus (
 
    // Only support device mode for now (v2 cards could support host mode)
    assign abc_host  = 1'b0;
-   assign abc_a_oe  = 1'b0;
 
    reg	     abc_clk_active;
 

fpga/max80.sdc

@@ -73,17 +73,28 @@ set_multicycle_path -from $cpu_dram_rd -to $sys_clk -start -hold 1
 
 # -------- SPI ROM multicycle paths --------
 
-# go_spi is delayed by the synchronizer, so other bits in the ROMCOPY_DATALEN
-# register have some more time to settle.
+# CPU-writable registers
 set romcopy_datalen [get_registers \
  {*|spirom:*|datalen[*] *|spirom:*|cmdlen[*] *|spirom:*|spi_dual *|spirom:*|spi_more}]
+set romcopy_romcmd [get_registers {*|spirom:*|romcmd[*]}]
+set romcopy_ramstart [get_registers {*|spirom:*|ramstart[*]}]
+set romcopy_go [get_registers {*|spirom:*|is_* *|spirom:*|go_* *|spirom:*|irq}]
+set romcopy_cpuregs [add_to_collection $romcopy_datalen $romcopy_romcmd]
+set romcopy_cpuregs [add_to_collection $romcopy_cpuregs $romcopy_ramstart]
+set romcopy_cpuregs [add_to_collection $romcopy_cpuregs $romcopy_go]
+
+# CPU writes to the spirom registers are delayed by one ram_clk
+set_multicycle_path -from $sys_clk -to $romcopy_cpuregs -end -setup 2
+set_multicycle_path -from $sys_clk -to $romcopy_cpuregs -end -hold 1
+
+# go_spi is delayed by the synchronizer, so other bits in the ROMCOPY_DATALEN
+# register have some more time to settle.
 set_multicycle_path -from $romcopy_datalen -to $flash_clk -end -setup 2
 set_multicycle_path -from $romcopy_datalen -to $flash_clk -end -hold 1
 
 # A load of romcmd does not affect the SPI unit for a minimum of 3 target
 # clock cycles (in reality much more, since the CPU needs to
 # write datalen in order to start the transfer).
-set romcopy_romcmd [get_registers {*|spirom:*|romcmd[*]}]
 set_multicycle_path -from $romcopy_romcmd -to $flash_clk -end -setup 3
 set_multicycle_path -from $romcopy_romcmd -to $flash_clk -end -hold 2
 

fpga/max80.sv

@@ -20,7 +20,6 @@ module max80
     inout 	  abc_clk, // ABC-bus 3 MHz clock
     inout [15:0]  abc_a, // ABC address bus
     inout [7:0]   abc_d, // ABC data bus
-    output 	  abc_a_oe, // Address bus output enable
     output 	  abc_d_oe, // Data bus output enable
     inout 	  abc_rst_n, // ABC bus reset strobe
     inout 	  abc_cs_n, // ABC card select strobe
@@ -414,7 +413,6 @@ module max80
 	   .abc_nmi_x ( abc_nmi_x ),
 	   .abc_xm_x ( abc_xm_x ),
 	   .abc_host ( abc_host ),
-	   .abc_a_oe ( abc_a_oe ),
 
 	   .exth_ha ( exth_ha ),
 	   .exth_hb ( exth_hb ),

fpga/output/v2.pin

@@ -102,8 +102,8 @@ sr_a[1]                      : B14       : output : 3.3-V LVTTL       :
 GND                          : B15       : gnd    :                   :         :           :                
 rtc_int_n                    : B16       : input  : 3.3-V LVTTL       :         : 6         : Y              
 flash_io[0]                  : C1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-abc_a_oe                     : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
-abc_host                     : C3        : output : 3.3-V LVTTL       :         : 8         : N              
+abc_host                     : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND*                         : C3        :        :                   :         : 8         :                
 VCCIO8                       : C4        : power  :                   : 3.3V    : 8         :                
 GND                          : C5        : gnd    :                   :         :           :                
 sr_dq[14]                    : C6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              

fpga/spirom.sv

@@ -47,7 +47,7 @@ module spirom (
    reg	      spi_more;		// Do not raise CS# after command done
    reg	      ram_done;
    reg	      ram_done_q;
-   reg	      cpu_wr_q;
+   reg [1:0]  cpu_wr_q;
    reg [31:0] spi_in_shr;	// Input shift register for one-bit input
    wire       spi_active_s;
 
@@ -68,7 +68,7 @@ module spirom (
 	  irq          <= 1'b1;
 	  spi_dual     <= 1'b0;
 	  spi_more     <= 1'b0;
-	  cpu_wr_q     <= 1'b0;
+	  cpu_wr_q     <= 2'b0;
        end
      else
        begin
@@ -82,10 +82,14 @@ module spirom (
 	  if (ram_done_q & ~go_ram & ~spi_active_s & ~go_spi)
 	    irq     <= 1'b1;
 
-	  cpu_wr_q <= cpu_wr_w;
-
 	  // Don't allow writing unless the unit is idle (IRQ = 1)
-	  if (cpu_wr_w & ~cpu_wr_q & irq)
+	  // Delay the recognition of the write by one ram_clk
+	  // cycle (so it is recognized on the second half of the
+	  // corresponding sys_clk cycle) to relax timings; this
+	  // is not performance critical at all.
+	  cpu_wr_q <= { cpu_wr_q[0], cpu_wr_w & irq };
+
+	  if (cpu_wr_q == 2'b01)
 	    begin
 	       // Only full word accesses supported via DMA!!
 	       case (cpu_addr)

fpga/v1.sv

@@ -117,6 +117,9 @@ module v1
    // ABC data bus isolation not supported or needed
    assign abc_d_ce_n  = 1'b0;
 
+   // This signal duplicates abc_host
+   assign abc_a_oe    = abc_host;
+
    // Permanently unused
    assign sd_dat[2:1] = 2'bzz;
    assign gpio[0] = 1'bz;
@@ -151,7 +154,6 @@ module v1
 	  .abc_nmi_x              ( abc_nmi_x ),
 	  .abc_xm_x               ( abc_xm_x ),
 	  .abc_host               ( abc_host ),
-	  .abc_a_oe               ( abc_a_oe ),
 	  .exth_ha                ( exth_ha ),
 	  .exth_hb                ( exth_hb ),
 	  .exth_hc                ( exth_hc ),

fpga/v2.pins

@@ -5,7 +5,7 @@
 # h4	TDI
 # e1	GND
 b1	abc_xm_x
-c2	abc_a_oe
+c2	abc_host
 c1	flash_io[0]
 f3	abc_a[5]
 d2	flash_cs_n

fpga/v2.sv

@@ -35,7 +35,6 @@ module v2
     inout 	  abc_xm_x, // System memory override (ABC800)
     // Host/device control
     output 	  abc_host, // 1 = host, 0 = target
-    output 	  abc_a_oe,
 
     // ABC-bus extension header
     // (Note: cannot use an array here because HC and HH are
@@ -147,7 +146,6 @@ module v2
 	  .abc_nmi_x              ( abc_nmi_x ),
 	  .abc_xm_x               ( abc_xm_x ),
 	  .abc_host               ( abc_host ),
-	  .abc_a_oe               ( abc_a_oe ),
 	  .exth_ha                ( exth_ha ),
 	  .exth_hb                ( exth_hb ),
 	  .exth_hc                ( exth_hc ),

rv32/boot.mif

@@ -1314,11 +1314,11 @@ CONTENT BEGIN
 051B : 64656C69;
 051C : 3A6E6F20;
 051D : 63654420;
-051E : 20363220;
+051E : 20373220;
 051F : 31323032;
-0520 : 3A303220;
-0521 : 353A3032;
-0522 : 00000A33;
+0520 : 3A313020;
+0521 : 343A3932;
+0522 : 00000A37;
 0523 : 00000101;
 0524 : 00000000;
 0525 : 00000000;