vjtag: fix "one bit behind" problem for write properly; use sys_clk

The "one bit behind" problem for write is simply because the last bit
is shifted in in the last st_sdr state; capture the data from tdi_s
rather than from the shift register; no need for a hack with checking
s_udr.

The vjtag unit can be clocked with sys_clk, absolutely no reason to
clock it faster.

fpga/max80.qpf

@@ -19,12 +19,12 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 18:38:47  February 09, 2022
+# Date created = 18:47:04  February 09, 2022
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "18:38:47  February 09, 2022"
+DATE = "18:47:04  February 09, 2022"
 
 # Revisions
 

fpga/max80.sv

@@ -894,7 +894,7 @@ module max80
 		 .sdram_bits(SDRAM_BITS))
    vjtag (
 	  .rst_n	( rst_n ),
-	  .sys_clk      ( sdram_clk ),
+	  .sys_clk      ( sys_clk ),
 
 	  .sdram	( sr_bus[2].dstr ),
 

fpga/output/sram.mif

@@ -1751,8 +1751,8 @@ CONTENT BEGIN
 06D0 : 65462064;
 06D1 : 39202062;
 06D2 : 3A383120;
-06D3 : 333A3633;
-06D4 : 53502031;
+06D3 : 333A3434;
+06D4 : 53502030;
 06D5 : 30322054;
 06D6 : 003232;
 [06D7..1FFF] : 00;

fpga/vjtag_max80.sv

@@ -189,6 +189,10 @@ module vjtag_max80
    // SDR state.
    reg [4:0] sdr_ctr;
 
+   wire [31:0] jtag_shr_in =
+	       ir_cmd[3] ? { tdi_s : jtag_shr[31:1] } :
+	       { 30'bx, tdi_s, jtag_shr[1] };
+
    always @(posedge sys_clk)
      begin
 	if ( ~rst_n )
@@ -199,12 +203,7 @@ module vjtag_max80
 	if ( tck_stb )
 	  begin
 	     if ( st_sdr_s )
-	       begin
-		  if ( ir_cmd[3] )
-		    jtag_shr <= { tdi_s, jtag_shr[31:1] };
-		  else
-		    jtag_shr <= { 30'bx, tdi_s, jtag_shr[1] };
-	       end
+	       jtag_shr <= jtag_shr_in;
 
 	     if ( st_cdr_s )
 	       case ( ir_cmd )
@@ -251,7 +250,7 @@ module vjtag_max80
 		       sdr_ctr            <= 5'b0;
 		    end
 
-		  if ( st_sdr_s | st_udr_s )
+		  if ( st_sdr_s )
 		    begin
 		       sdr_ctr <= sdr_ctr + 1'b1;
 
@@ -265,7 +264,7 @@ module vjtag_max80
 			    else
 			      begin
 				 // Write
-				 if ( jtag_shr == VJTAG_WRITE_PREFIX )
+				 if ( jtag_shr_in == VJTAG_WRITE_PREFIX )
 				   mem_header_done <= 1'b1;
 				 sdr_ctr <= 5'b0;
 			      end
@@ -301,7 +300,7 @@ module vjtag_max80
 			 // Write
 			 if ( &sdr_ctr )
 			   begin
-			      mem_wdata          <= jtag_shr;
+			      mem_wdata          <= jtag_shr_in;
 			      mem_valid          <= 1'b1;
 			      mem_done           <= 1'b0;
 			      advance_mem_addr   <= 1'b1;