Timing improvements; allow SRAM to be read over JTAG

Retime memory quadrant decode by using memory lookahead addresses to
convert to 1-hot before clock.

Enable JTAG reading of SRAM content.

Corrections to some sdc entries.

fpga/ip/fastmem_ip.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "20.1"
+set_global_assignment -name IP_TOOL_VERSION "21.1"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
 set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fastmem_ip.v"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fastmem_ip_inst.v"]

fpga/ip/fastmem_ip.v

@@ -14,11 +14,11 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// 21.1.0 Build 842 10/21/2021 SJ Lite Edition
 // ************************************************************
 
 
-//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Copyright (C) 2021  Intel Corporation. All rights reserved.
 //Your use of Intel Corporation's design tools, logic functions 
 //and other software and tools, and any partner logic 
 //functions, and any output files from any of the foregoing 
@@ -99,7 +99,7 @@ module fastmem_ip (
 		altsyncram_component.clock_enable_output_a = "BYPASS",
 		altsyncram_component.init_file = "output/sram.mif",
 		altsyncram_component.intended_device_family = "Cyclone IV E",
-		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SRAM",
 		altsyncram_component.lpm_type = "altsyncram",
 		altsyncram_component.numwords_a = 8192,
 		altsyncram_component.operation_mode = "SINGLE_PORT",
@@ -133,8 +133,8 @@ endmodule
 // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
 // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
+// Retrieval info: PRIVATE: JTAG_ID STRING "SRAM"
 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
 // Retrieval info: PRIVATE: MIFfilename STRING "output/sram.mif"
 // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
@@ -156,7 +156,7 @@ endmodule
 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
 // Retrieval info: CONSTANT: INIT_FILE STRING "output/sram.mif"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=SRAM"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
 // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
 // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"

fpga/max80.qpf

@@ -19,14 +19,14 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 00:17:28  January 28, 2022
+# Date created = 01:12:15  January 28, 2022
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "00:17:28  January 28, 2022"
+DATE = "01:12:15  January 28, 2022"
 
 # Revisions
 
-PROJECT_REVISION = "v2"
 PROJECT_REVISION = "v1"
+PROJECT_REVISION = "v2"

fpga/max80.sdc

@@ -77,10 +77,10 @@ set_multicycle_path -from $cpu_dram_rd -to $sys_clk -start -hold 1
 
 # CPU-writable registers
 set romcopy_datalen [get_registers \
- {*|spirom:*|datalen[*] *|spirom:*|cmdlen[*] *|spirom:*|spi_dual *|spirom:*|spi_more}]
+ {*|spirom:*|datalen[*] *|spirom:*|cmdlen[*] *|spirom:*|spi_dual *|spirom:*|spi_more *|spirom:*|is_*}]
 set romcopy_romcmd [get_registers {*|spirom:*|romcmd[*]}]
 set romcopy_ramstart [get_registers {*|spirom:*|ramstart[*]}]
-set romcopy_go [get_registers {*|spirom:*|is_* *|spirom:*|go_* *|spirom:*|irq}]
+set romcopy_go [get_registers {*|spirom:*|go_* *|spirom:*|irq}]
 set romcopy_cpuregs [add_to_collection $romcopy_datalen $romcopy_romcmd]
 set romcopy_cpuregs [add_to_collection $romcopy_cpuregs $romcopy_ramstart]
 set romcopy_cpuregs [add_to_collection $romcopy_cpuregs $romcopy_go]
@@ -122,3 +122,6 @@ set fast_mem_we [get_keepers {*|fast_mem:fast_mem|*porta_we_reg*}]
 set cpu_regs    [get_keepers {*|picorv32:cpu|*}]
 set_multicycle_path -from $fast_mem_we -to $cpu_regs -start -setup 2
 set_multicycle_path -from $fast_mem_we -to $cpu_regs  -start -hold 1
+
+# -------- Random number generator pins are asynchronous --------
+set_false_path -from [get_keepers {*|rng|rngio*}] -to [get_keepers *]

fpga/max80.sv

@@ -287,7 +287,18 @@ module max80
    wire [ 3:0]		      cpu_la_wstrb;
 
    // cpu_mem_valid by address quadrant
-   wire [ 3:0] cpu_mem_quad = cpu_mem_valid << cpu_mem_addr[31:30];
+   wire [3:0]		      cpu_la_quad;
+   reg [3:0]		      cpu_mem_quad;
+
+   assign cpu_la_quad = 1'b1 << cpu_la_addr[31:30];
+
+   always @(negedge rst_n or posedge sys_clk)
+     if (~rst_n)
+       cpu_mem_quad <= 4'b0;
+     else if (cpu_la_read|cpu_la_write)
+       cpu_mem_quad <= cpu_la_quad;
+     else if (~cpu_mem_valid)
+       cpu_mem_quad <= 4'b0;
 
    // I/O device map from iodevs.conf
    wire        iodev_mem_valid = cpu_mem_quad[3];
@@ -529,15 +540,10 @@ module max80
    // accesses...)
    reg	       iodev_mem_ready;
 
-   always @(*)
-     case ( cpu_mem_quad )
-       4'b0000: cpu_mem_ready = 1'b0;
-       4'b0001: cpu_mem_ready = 1'b1;
-       4'b0010: cpu_mem_ready = sdram_mem_ready;
-       4'b0100: cpu_mem_ready = 1'b1;
-       4'b1000: cpu_mem_ready = iodev_mem_ready;
-       default: cpu_mem_ready = 1'bx;
-     endcase // case ( mem_quad )
+   assign cpu_mem_ready = cpu_mem_quad[0] |
+			  (cpu_mem_quad[1] & sdram_mem_ready) |
+			  cpu_mem_quad[2] |
+			  (cpu_mem_quad[3] & iodev_mem_ready);
 
    //
    // Fast memory. This runs on the SDRAM clock, i.e. 2x the speed
@@ -550,8 +556,8 @@ module max80
    fast_mem(
 	    .rst_n ( rst_n ),
 	    .clk   ( sys_clk ),
-	    .read  ( cpu_la_read  & cpu_la_addr[31:30] == 2'b00 ),
-	    .write ( cpu_la_write & cpu_la_addr[31:30] == 2'b00 ),
+	    .read  ( cpu_la_read  & cpu_la_quad[0] ),
+	    .write ( cpu_la_write & cpu_la_quad[0] ),
 	    .wstrb ( cpu_la_wstrb ),
 	    .addr  ( cpu_la_addr[14:2] ),
 	    .wdata ( cpu_la_wdata ),

fpga/output/v1.pin

@@ -183,8 +183,8 @@ sd_clk                       : G15       : output : 3.3-V LVTTL       :
 sd_cmd                       : G16       : output : 3.3-V LVTTL       :         : 6         : Y              
 flash_sck                    : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
 flash_io[1]                  : H2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-TCK                          : H3        : input  :                   :         : 1         :                
-TDI                          : H4        : input  :                   :         : 1         :                
+altera_reserved_tck          : H3        : input  : 3.3-V LVTTL       :         : 1         : N              
+altera_reserved_tdi          : H4        : input  : 3.3-V LVTTL       :         : 1         : N              
 nCONFIG                      : H5        :        :                   :         : 1         :                
 VCCINT                       : H6        : power  :                   : 1.2V    :           :                
 GND                          : H7        : gnd    :                   :         :           :                
@@ -200,8 +200,8 @@ GND                          : H16       : gnd    :                   :
 abc_a[9]                     : J1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_out_n[1]                 : J2        : input  : 3.3-V LVTTL       :         : 2         : Y              
 nCE                          : J3        :        :                   :         : 1         :                
-TDO                          : J4        : output :                   :         : 1         :                
-TMS                          : J5        : input  :                   :         : 1         :                
+altera_reserved_tdo          : J4        : output : 3.3-V LVTTL       :         : 1         : N              
+altera_reserved_tms          : J5        : input  : 3.3-V LVTTL       :         : 1         : N              
 VCCINT                       : J6        : power  :                   : 1.2V    :           :                
 GND                          : J7        : gnd    :                   :         :           :                
 GND                          : J8        : gnd    :                   :         :           :                

fpga/output/v2.pin

@@ -183,8 +183,8 @@ sd_clk                       : G15       : output : 3.3-V LVTTL       :
 sd_di                        : G16       : output : 3.3-V LVTTL       :         : 6         : Y              
 flash_sck                    : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
 flash_io[1]                  : H2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-TCK                          : H3        : input  :                   :         : 1         :                
-TDI                          : H4        : input  :                   :         : 1         :                
+altera_reserved_tck          : H3        : input  : 3.3-V LVTTL       :         : 1         : N              
+altera_reserved_tdi          : H4        : input  : 3.3-V LVTTL       :         : 1         : N              
 nCONFIG                      : H5        :        :                   :         : 1         :                
 VCCINT                       : H6        : power  :                   : 1.2V    :           :                
 GND                          : H7        : gnd    :                   :         :           :                
@@ -200,8 +200,8 @@ GND                          : H16       : gnd    :                   :
 abc_a[9]                     : J1        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
 abc_out_n[1]                 : J2        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
 nCE                          : J3        :        :                   :         : 1         :                
-TDO                          : J4        : output :                   :         : 1         :                
-TMS                          : J5        : input  :                   :         : 1         :                
+altera_reserved_tdo          : J4        : output : 3.3-V LVTTL       :         : 1         : N              
+altera_reserved_tms          : J5        : input  : 3.3-V LVTTL       :         : 1         : N              
 VCCINT                       : J6        : power  :                   : 1.2V    :           :                
 GND                          : J7        : gnd    :                   :         :           :                
 GND                          : J8        : gnd    :                   :         :           :                

fpga/v2.qsf

@@ -19,4 +19,5 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to sd_cd_n
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd_n
 
 # Quartus insists on this line...
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top