Restructure clock tree; better sdram timing; random number generator

Restructure the clock tree for (hopefully) better clock timing.

Improve the sdram timing by deferring ACT for one cycle after arbiter
accept.

Add hardware random number generator.

fpga/ip/hdmitx.v

@@ -38,44 +38,32 @@
 `timescale 1 ps / 1 ps
 // synopsys translate_on
 module hdmitx (
-	pll_areset,
 	tx_in,
 	tx_inclock,
-	tx_coreclock,
-	tx_locked,
-	tx_out,
-	tx_outclock);
+	tx_syncclock,
+	tx_out);
 
-	input	  pll_areset;
 	input	[39:0]  tx_in;
 	input	  tx_inclock;
-	output	  tx_coreclock;
-	output	  tx_locked;
+	input	  tx_syncclock;
 	output	[3:0]  tx_out;
-	output	  tx_outclock;
 
-	wire  sub_wire0;
-	wire  sub_wire1;
-	wire [3:0] sub_wire2;
-	wire  sub_wire3;
-	wire  tx_coreclock = sub_wire0;
-	wire  tx_locked = sub_wire1;
-	wire [3:0] tx_out = sub_wire2[3:0];
-	wire  tx_outclock = sub_wire3;
+	wire [3:0] sub_wire0;
+	wire [3:0] tx_out = sub_wire0[3:0];
 
 	altlvds_tx	ALTLVDS_TX_component (
-				.pll_areset (pll_areset),
 				.tx_in (tx_in),
 				.tx_inclock (tx_inclock),
-				.tx_coreclock (sub_wire0),
-				.tx_locked (sub_wire1),
-				.tx_out (sub_wire2),
-				.tx_outclock (sub_wire3),
+				.tx_syncclock (tx_syncclock),
+				.tx_out (sub_wire0),
+				.pll_areset (1'b0),
 				.sync_inclock (1'b0),
+				.tx_coreclock (),
 				.tx_data_reset (1'b0),
 				.tx_enable (1'b1),
-				.tx_pll_enable (1'b1),
-				.tx_syncclock (1'b0));
+				.tx_locked (),
+				.tx_outclock (),
+				.tx_pll_enable (1'b1));
 	defparam
 		ALTLVDS_TX_component.center_align_msb = "UNUSED",
 		ALTLVDS_TX_component.common_rx_tx_pll = "ON",
@@ -105,8 +93,8 @@ module hdmitx (
 		ALTLVDS_TX_component.pll_self_reset_on_loss_lock = "ON",
 		ALTLVDS_TX_component.preemphasis_setting = 0,
 		ALTLVDS_TX_component.refclk_frequency = "UNUSED",
-		ALTLVDS_TX_component.registered_input = "TX_CORECLK",
-		ALTLVDS_TX_component.use_external_pll = "OFF",
+		ALTLVDS_TX_component.registered_input = "OFF",
+		ALTLVDS_TX_component.use_external_pll = "ON",
 		ALTLVDS_TX_component.use_no_phase_shift = "ON",
 		ALTLVDS_TX_component.vod_setting = 0,
 		ALTLVDS_TX_component.clk_src_is_pll = "off";
@@ -123,24 +111,24 @@ endmodule
 // Retrieval info: PRIVATE: CNX_COMMON_PLL NUMERIC "1"
 // Retrieval info: PRIVATE: CNX_DATA_RATE STRING "560.0"
 // Retrieval info: PRIVATE: CNX_DESER_FACTOR NUMERIC "10"
-// Retrieval info: PRIVATE: CNX_EXT_PLL STRING "OFF"
+// Retrieval info: PRIVATE: CNX_EXT_PLL STRING "ON"
 // Retrieval info: PRIVATE: CNX_LE_SERDES STRING "ON"
 // Retrieval info: PRIVATE: CNX_NUM_CHANNEL NUMERIC "4"
 // Retrieval info: PRIVATE: CNX_OUTCLOCK_DIVIDE_BY NUMERIC "10"
-// Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "1"
+// Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "0"
 // Retrieval info: PRIVATE: CNX_PLL_FREQ STRING "56.00"
 // Retrieval info: PRIVATE: CNX_PLL_PERIOD STRING "17.857"
 // Retrieval info: PRIVATE: CNX_REG_INOUT NUMERIC "1"
-// Retrieval info: PRIVATE: CNX_TX_CORECLOCK STRING "ON"
-// Retrieval info: PRIVATE: CNX_TX_LOCKED STRING "ON"
-// Retrieval info: PRIVATE: CNX_TX_OUTCLOCK STRING "ON"
+// Retrieval info: PRIVATE: CNX_TX_CORECLOCK STRING "OFF"
+// Retrieval info: PRIVATE: CNX_TX_LOCKED STRING "OFF"
+// Retrieval info: PRIVATE: CNX_TX_OUTCLOCK STRING "OFF"
 // Retrieval info: PRIVATE: CNX_USE_CLOCK_RESC STRING "Auto selection"
 // Retrieval info: PRIVATE: CNX_USE_PLL_ENABLE NUMERIC "0"
-// Retrieval info: PRIVATE: CNX_USE_TX_OUT_PHASE NUMERIC "0"
+// Retrieval info: PRIVATE: CNX_USE_TX_OUT_PHASE NUMERIC "1"
 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-// Retrieval info: PRIVATE: pCNX_OUTCLK_ALIGN STRING "UNUSED"
+// Retrieval info: PRIVATE: pCNX_OUTCLK_ALIGN STRING "EDGE_ALIGNED"
 // Retrieval info: PRIVATE: pINCLOCK_PHASE_SHIFT STRING "0.00"
-// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT STRING "0.00"
+// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT NUMERIC "0"
 // Retrieval info: CONSTANT: CENTER_ALIGN_MSB STRING "UNUSED"
 // Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
 // Retrieval info: CONSTANT: CORECLOCK_DIVIDE_BY NUMERIC "2"
@@ -170,24 +158,18 @@ endmodule
 // Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "ON"
 // Retrieval info: CONSTANT: PREEMPHASIS_SETTING NUMERIC "0"
 // Retrieval info: CONSTANT: REFCLK_FREQUENCY STRING "UNUSED"
-// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CORECLK"
-// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
+// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "OFF"
+// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "ON"
 // Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
 // Retrieval info: CONSTANT: VOD_SETTING NUMERIC "0"
-// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
-// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
-// Retrieval info: USED_PORT: tx_coreclock 0 0 0 0 OUTPUT NODEFVAL "tx_coreclock"
-// Retrieval info: CONNECT: tx_coreclock 0 0 0 0 @tx_coreclock 0 0 0 0
 // Retrieval info: USED_PORT: tx_in 0 0 40 0 INPUT NODEFVAL "tx_in[39..0]"
 // Retrieval info: CONNECT: @tx_in 0 0 40 0 tx_in 0 0 40 0
 // Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT NODEFVAL "tx_inclock"
 // Retrieval info: CONNECT: @tx_inclock 0 0 0 0 tx_inclock 0 0 0 0
-// Retrieval info: USED_PORT: tx_locked 0 0 0 0 OUTPUT NODEFVAL "tx_locked"
-// Retrieval info: CONNECT: tx_locked 0 0 0 0 @tx_locked 0 0 0 0
 // Retrieval info: USED_PORT: tx_out 0 0 4 0 OUTPUT NODEFVAL "tx_out[3..0]"
 // Retrieval info: CONNECT: tx_out 0 0 4 0 @tx_out 0 0 4 0
-// Retrieval info: USED_PORT: tx_outclock 0 0 0 0 OUTPUT NODEFVAL "tx_outclock"
-// Retrieval info: CONNECT: tx_outclock 0 0 0 0 @tx_outclock 0 0 0 0
+// Retrieval info: USED_PORT: tx_syncclock 0 0 0 0 INPUT NODEFVAL "tx_syncclock"
+// Retrieval info: CONNECT: @tx_syncclock 0 0 0 0 tx_syncclock 0 0 0 0
 // Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.v TRUE FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.qip TRUE FALSE
 // Retrieval info: GEN_FILE: TYPE_NORMAL hdmitx.bsf TRUE TRUE

fpga/ip/int_osc.qsys

@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element int_osc_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4CE15F17C8" />
+ <parameter name="deviceFamily" value="Cyclone IV E" />
+ <parameter name="deviceSpeedGrade" value="8" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clkout" internal="int_osc_0.clkout" type="clock" dir="start">
+  <port name="clkout" internal="clkout" />
+ </interface>
+ <interface name="oscena" internal="int_osc_0.oscena" type="conduit" dir="end">
+  <port name="oscena" internal="oscena" />
+ </interface>
+ <module
+   name="int_osc_0"
+   kind="altera_int_osc"
+   version="20.1"
+   enabled="1"
+   autoexport="1">
+  <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+  <parameter name="CLOCK_FREQUENCY_1" value="116" />
+  <parameter name="CLOCK_FREQUENCY_2" value="77" />
+  <parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
+  <parameter name="PART_NAME" value="EP4CE15F17C8" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>

fpga/ip/int_osc.sopcinfo

@@ -0,0 +1,306 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="int_osc" kind="int_osc" version="1.0" fabric="QSYS">
+ <!-- Format version 20.1 720 (Future versions may contain additional information.) -->
+ <!-- 2021.12.01.09:19:29 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1638379169</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>CYCLONEIVE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>EP4CE15F17C8</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>8</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>Cyclone IV E</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="int_osc_0"
+   kind="altera_int_osc"
+   version="20.1"
+   path="int_osc_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="INFORMATION">
+   <type>java.lang.String</type>
+   <value>The maximum output frequency is 80MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>CYCLONEIVE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="PART_NAME">
+   <type>java.lang.String</type>
+   <value>EP4CE15F17C8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="DEVICE_ID">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLOCK_FREQUENCY_1">
+   <type>java.lang.String</type>
+   <value>116</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLOCK_FREQUENCY_2">
+   <type>java.lang.String</type>
+   <value>77</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLOCK_FREQUENCY">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CBX_AUTO_BLACKBOX">
+   <type>java.lang.String</type>
+   <value>ALL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="oscena" kind="conduit_end" version="20.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>INPUT</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>oscena</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>oscena</role>
+   </port>
+  </interface>
+  <interface name="clkout" kind="clock_source" version="20.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>OUTPUT</value>
+   </assignment>
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>clkout</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_int_osc</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Internal Oscillator</displayName>
+  <version>20.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>20.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>20.1</version>
+ </plugin>
+ <reportVersion>20.1 720</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>

fpga/ip/int_osc/greybox/int_osc.v

@@ -0,0 +1,82 @@
+// Copyright (C) 2020  Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions 
+// and other software and tools, and any partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License 
+// Subscription Agreement, the Intel Quartus Prime License Agreement,
+// the Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is for
+// the sole purpose of programming logic devices manufactured by
+// Intel and sold by Intel or its authorized distributors.  Please
+// refer to the applicable agreement for further details, at
+// https://fpgasoftware.intel.com/eula.
+
+// VENDOR "Altera"
+// PROGRAM "Quartus Prime"
+// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+
+// DATE "12/01/2021 09:19:36"
+
+// 
+// Device: Altera EP4CE15F17C8 Package FBGA256
+// 
+
+// 
+// This greybox netlist file is for third party Synthesis Tools
+// for timing and resource estimation only.
+// 
+
+
+module int_osc (
+	clkout,
+	oscena)/* synthesis synthesis_greybox=0 */;
+output 	clkout;
+input 	oscena;
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+// unknown value (1'bx) is not needed for this tool. Default to 1'b0
+assign unknown = 1'b0;
+
+wire \int_osc_0|wire_sd1_clkout ;
+wire \oscena~input_o ;
+
+
+int_osc_altera_int_osc int_osc_0(
+	.clkout(\int_osc_0|wire_sd1_clkout ),
+	.oscena(\oscena~input_o ));
+
+assign \oscena~input_o  = oscena;
+
+assign clkout = \int_osc_0|wire_sd1_clkout ;
+
+endmodule
+
+module int_osc_altera_int_osc (
+	clkout,
+	oscena)/* synthesis synthesis_greybox=0 */;
+output 	clkout;
+input 	oscena;
+
+wire gnd;
+wire vcc;
+wire unknown;
+
+assign gnd = 1'b0;
+assign vcc = 1'b1;
+// unknown value (1'bx) is not needed for this tool. Default to 1'b0
+assign unknown = 1'b0;
+
+
+
+cycloneive_oscillator sd1(
+	.oscena(oscena),
+	.clkout(clkout));
+
+endmodule

fpga/ip/int_osc/int_osc.csv

@@ -0,0 +1,18 @@
+# system info int_osc on 2021.12.01.09:19:28
+system_info:
+name,value
+DEVICE,EP4CE15F17C8
+DEVICE_FAMILY,Cyclone IV E
+GENERATION_ID,1638379168
+#
+#
+# Files generated for int_osc on 2021.12.01.09:19:28
+files:
+filepath,kind,attributes,module,is_top
+simulation/int_osc.v,VERILOG,,int_osc,true
+simulation/submodules/altera_int_osc.v,VERILOG,,altera_int_osc,false
+#
+# Map from instance-path to kind of module
+instances:
+instancePath,module
+int_osc.int_osc_0,altera_int_osc

fpga/ip/int_osc/int_osc.html

@@ -0,0 +1,165 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+  <title>datasheet for int_osc</title>
+  <style type="text/css">
+body { font-family:arial ;}
+a { text-decoration:underline ; color:#003000 ;}
+a:hover { text-decoration:underline ; color:0030f0 ;}
+td { padding : 5px ;}
+table.topTitle { width:100% ;}
+table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
+table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
+table.blueBar { width : 100% ; border-spacing : 0px ;}
+table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
+table.blueBar td.l { text-align : left ;}
+table.blueBar td.r { text-align : right ;}
+table.items { width:100% ; border-collapse:collapse ;}
+table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
+table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
+div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
+table.grid { border-collapse:collapse ;}
+table.grid td { border:1px solid #bbb ; font-size:12px ;}
+body { font-family:arial ;}
+table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
+table.x td { border:1px solid #bbb ;}
+td.tableTitle { font-weight:bold ; text-align:center ;}
+table.grid { border-collapse:collapse ;}
+table.grid td { border:1px solid #bbb ;}
+table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
+table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
+table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
+table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
+table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
+table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
+table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
+table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
+table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
+table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
+table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
+table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
+table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
+table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
+table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
+table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
+table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
+table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
+.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
+.flowbox { display:inline-block ;}
+.parametersbox table { font-size:10px ;}
+td.parametername { font-style:italic ;}
+td.parametervalue { font-weight:bold ;}
+div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
+ </head>
+ <body>
+  <table class="topTitle">
+   <tr>
+    <td class="l">int_osc</td>
+    <td class="r">
+     <br/>
+     <br/>
+    </td>
+   </tr>
+  </table>
+  <table class="blueBar">
+   <tr>
+    <td class="l">2021.12.01.09:19:29</td>
+    <td class="r">Datasheet</td>
+   </tr>
+  </table>
+  <div style="width:100% ;  height:10px"> </div>
+  <div class="label">Overview</div>
+  <div class="greydiv">
+   <div style="display:inline-block ; text-align:left">
+    <table class="connectionboxes">
+     <tr style="height:6px">
+      <td></td>
+     </tr>
+    </table>
+   </div><span style="display:inline-block ; width:28px"> </span>
+   <div style="display:inline-block ; text-align:left"><span>
+     <br/></span>
+   </div>
+  </div>
+  <div style="width:100% ;  height:10px"> </div>
+  <div class="label">Memory Map</div>
+  <table class="mmap">
+   <tr>
+    <td class="empty" rowspan="2"></td>
+   </tr>
+  </table>
+  <a name="module_int_osc_0"> </a>
+  <div>
+   <hr/>
+   <h2>int_osc_0</h2>altera_int_osc v20.1
+   <br/>
+   <br/>
+   <br/>
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Parameters</h2>
+      <table>
+       <tr>
+        <td class="parametername">INFORMATION</td>
+        <td class="parametervalue">The maximum output frequency is 80MHz</td>
+       </tr>
+       <tr>
+        <td class="parametername">DEVICE_FAMILY</td>
+        <td class="parametervalue">CYCLONEIVE</td>
+       </tr>
+       <tr>
+        <td class="parametername">PART_NAME</td>
+        <td class="parametervalue">EP4CE15F17C8</td>
+       </tr>
+       <tr>
+        <td class="parametername">DEVICE_ID</td>
+        <td class="parametervalue">UNKNOWN</td>
+       </tr>
+       <tr>
+        <td class="parametername">CLOCK_FREQUENCY_1</td>
+        <td class="parametervalue">116</td>
+       </tr>
+       <tr>
+        <td class="parametername">CLOCK_FREQUENCY_2</td>
+        <td class="parametervalue">77</td>
+       </tr>
+       <tr>
+        <td class="parametername">CLOCK_FREQUENCY</td>
+        <td class="parametervalue">UNKNOWN</td>
+       </tr>
+       <tr>
+        <td class="parametername">CBX_AUTO_BLACKBOX</td>
+        <td class="parametervalue">ALL</td>
+       </tr>
+       <tr>
+        <td class="parametername">deviceFamily</td>
+        <td class="parametervalue">UNKNOWN</td>
+       </tr>
+       <tr>
+        <td class="parametername">generateLegacySim</td>
+        <td class="parametervalue">false</td>
+       </tr>
+      </table>
+     </td>
+    </tr>
+   </table>&#160;&#160;
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Software Assignments</h2>(none)</td>
+    </tr>
+   </table>
+  </div>
+  <table class="blueBar">
+   <tr>
+    <td class="l">generation took 0.00 seconds</td>
+    <td class="r">rendering took 0.00 seconds</td>
+   </tr>
+  </table>
+ </body>
+</html>

fpga/ip/int_osc/int_osc.spd

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file
+   path="simulation/submodules/altera_int_osc.v"
+   type="VERILOG"
+   library="int_osc_0" />
+ <file path="simulation/int_osc.v" type="VERILOG" />
+ <topLevel name="int_osc" />
+ <deviceFamily name="cycloneive" />
+</simPackage>

fpga/ip/int_osc/int_osc.xml

@@ -0,0 +1,134 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2021.12.01.09:19:29"
+ outputDirectory="/home/hpa/abc80/max80/fw/fpga/ip/int_osc/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="Cyclone IV E"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="EP4CE15F17C8"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="8"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="clkout" kind="clock" start="1">
+   <property name="associatedDirectClock" value="" />
+   <property name="clockRate" value="0" />
+   <property name="clockRateKnown" value="false" />
+   <property name="externallyDriven" value="false" />
+   <property name="ptfSchematicName" value="" />
+   <port name="clkout" direction="output" role="clk" width="1" />
+  </interface>
+  <interface name="oscena" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port name="oscena" direction="input" role="oscena" width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="int_osc:1.0:AUTO_DEVICE=EP4CE15F17C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1638379169,AUTO_UNIQUE_ID=(altera_int_osc:20.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=UNKNOWN,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=Cyclone IV E,DEVICE_ID=UNKNOWN,INFORMATION=The maximum output frequency is 80MHz,PART_NAME=EP4CE15F17C8)"
+   instancePathKey="int_osc"
+   kind="int_osc"
+   version="1.0"
+   name="int_osc">
+  <parameter name="AUTO_GENERATION_ID" value="1638379169" />
+  <parameter name="AUTO_DEVICE" value="EP4CE15F17C8" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
+  <generatedFiles>
+   <file
+       path="/home/hpa/abc80/max80/fw/fpga/ip/int_osc/synthesis/int_osc.v"
+       type="VERILOG" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/home/hpa/abc80/max80/fw/fpga/ip/int_osc/synthesis/submodules/altera_int_osc.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file path="/home/hpa/abc80/max80/fw/fpga/ip/int_osc.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/opt/altera/20.1/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="int_osc">queue size: 0 starting:int_osc "int_osc"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="int_osc"><![CDATA["<b>int_osc</b>" reuses <b>altera_int_osc</b> "<b>submodules/altera_int_osc</b>"]]></message>
+   <message level="Debug" culprit="int_osc">queue size: 0 starting:altera_int_osc "submodules/altera_int_osc"</message>
+   <message level="Info" culprit="int_osc_0">Generating top-level entity altera_int_osc.</message>
+   <message level="Info" culprit="int_osc_0"><![CDATA["<b>int_osc</b>" instantiated <b>altera_int_osc</b> "<b>int_osc_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altera_int_osc:20.1:CBX_AUTO_BLACKBOX=ALL,CLOCK_FREQUENCY=UNKNOWN,CLOCK_FREQUENCY_1=116,CLOCK_FREQUENCY_2=77,DEVICE_FAMILY=Cyclone IV E,DEVICE_ID=UNKNOWN,INFORMATION=The maximum output frequency is 80MHz,PART_NAME=EP4CE15F17C8"
+   instancePathKey="int_osc:.:int_osc_0"
+   kind="altera_int_osc"
+   version="20.1"
+   name="altera_int_osc">
+  <parameter name="CLOCK_FREQUENCY_2" value="77" />
+  <parameter name="CLOCK_FREQUENCY_1" value="116" />
+  <parameter name="PART_NAME" value="EP4CE15F17C8" />
+  <parameter name="CLOCK_FREQUENCY" value="UNKNOWN" />
+  <parameter name="INFORMATION" value="The maximum output frequency is 80MHz" />
+  <parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
+  <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+  <parameter name="DEVICE_ID" value="UNKNOWN" />
+  <generatedFiles>
+   <file
+       path="/home/hpa/abc80/max80/fw/fpga/ip/int_osc/synthesis/submodules/altera_int_osc.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/opt/altera/20.1/ip/altera/altera_int_osc/altera_int_osc_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="int_osc" as="int_osc_0" />
+  <messages>
+   <message level="Debug" culprit="int_osc">queue size: 0 starting:altera_int_osc "submodules/altera_int_osc"</message>
+   <message level="Info" culprit="int_osc_0">Generating top-level entity altera_int_osc.</message>
+   <message level="Info" culprit="int_osc_0"><![CDATA["<b>int_osc</b>" instantiated <b>altera_int_osc</b> "<b>int_osc_0</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>

fpga/ip/int_osc/int_osc_inst.vhd

@@ -0,0 +1,13 @@
+	component int_osc is
+		port (
+			oscena : in  std_logic := 'X'; -- oscena
+			clkout : out std_logic         -- clk
+		);
+	end component int_osc;
+
+	u0 : component int_osc
+		port map (
+			oscena => CONNECTED_TO_oscena, -- oscena.oscena
+			clkout => CONNECTED_TO_clkout  -- clkout.clk
+		);
+

fpga/ip/int_osc/simulation/aldec/rivierapro_setup.tcl

@@ -0,0 +1,270 @@
+
+# (C) 2001-2021 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2021.12.01.09:19:29
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     int_osc
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If int_osc is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "int_osc"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/opt/altera/20.1/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+  set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+  scripterconf -tcl
+  createdesign "$TOP_LEVEL_NAME"  "."
+  opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib      ./libraries     
+ensure_lib      ./libraries/work
+vmap       work ./libraries/work
+ensure_lib                  ./libraries/altera_ver      
+vmap       altera_ver       ./libraries/altera_ver      
+ensure_lib                  ./libraries/lpm_ver         
+vmap       lpm_ver          ./libraries/lpm_ver         
+ensure_lib                  ./libraries/sgate_ver       
+vmap       sgate_ver        ./libraries/sgate_ver       
+ensure_lib                  ./libraries/altera_mf_ver   
+vmap       altera_mf_ver    ./libraries/altera_mf_ver   
+ensure_lib                  ./libraries/altera_lnsim_ver
+vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver
+ensure_lib                  ./libraries/cycloneive_ver  
+vmap       cycloneive_ver   ./libraries/cycloneive_ver  
+ensure_lib           ./libraries/int_osc_0
+vmap       int_osc_0 ./libraries/int_osc_0
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver      
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"          -work lpm_ver         
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"             -work sgate_ver       
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"         -work altera_mf_ver   
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"     -work altera_lnsim_ver
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v"  -work cycloneive_ver  
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_int_osc.v" -work int_osc_0
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/int_osc.v"                                  
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L int_osc_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L int_osc_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h

fpga/ip/int_osc/simulation/cadence/cds.lib

@@ -0,0 +1,18 @@
+
+DEFINE std              $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys         $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee             $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit            $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory     $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils          $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal       $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels         $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions   $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work             ./libraries/work/                         
+DEFINE int_osc_0        ./libraries/int_osc_0/                    
+DEFINE altera_ver       ./libraries/altera_ver/                   
+DEFINE lpm_ver          ./libraries/lpm_ver/                      
+DEFINE sgate_ver        ./libraries/sgate_ver/                    
+DEFINE altera_mf_ver    ./libraries/altera_mf_ver/                
+DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/             
+DEFINE cycloneive_ver   ./libraries/cycloneive_ver/               

fpga/ip/int_osc/simulation/cadence/cds_libs/int_osc_0.cds.lib

@@ -0,0 +1,18 @@
+
+DEFINE std              $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys         $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee             $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit            $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory     $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils          $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal       $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels         $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions   $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work             ./../libraries/work/                      
+DEFINE altera_ver       ./../libraries/altera_ver/                
+DEFINE lpm_ver          ./../libraries/lpm_ver/                   
+DEFINE sgate_ver        ./../libraries/sgate_ver/                 
+DEFINE altera_mf_ver    ./../libraries/altera_mf_ver/             
+DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/          
+DEFINE cycloneive_ver   ./../libraries/cycloneive_ver/            
+DEFINE int_osc_0        ./../libraries/int_osc_0/                 

fpga/ip/int_osc/simulation/cadence/hdl.var

@@ -0,0 +1,2 @@
+
+DEFINE WORK work

fpga/ip/int_osc/simulation/cadence/ncsim_setup.sh

@@ -0,0 +1,189 @@
+
+# (C) 2001-2021 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2021.12.01.09:19:29
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     int_osc
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If int_osc is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2021.12.01.09:19:29
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="int_osc"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/opt/altera/20.1/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/int_osc_0/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cycloneive_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver      
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"          -work lpm_ver         
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"             -work sgate_ver       
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"         -work altera_mf_ver   
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"     -work altera_lnsim_ver
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v"  -work cycloneive_ver  
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_int_osc.v" -work int_osc_0 -cdslib ./cds_libs/int_osc_0.cds.lib
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/int_osc.v"                                                                       
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  export GENERIC_PARAM_COMPAT_CHECK=1
+  ncelab -access +w+r+c -namemap_mixgen $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi

fpga/ip/int_osc/simulation/int_osc.sip

@@ -0,0 +1,8 @@
+set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_VERSION "20.1"
+set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "lib_int_osc" -name SPD_FILE [file join $::quartus(sip_path) "../int_osc.spd"]
+set_global_assignment -library "lib_int_osc" -name MISC_FILE [file join $::quartus(sip_path) "../../int_osc.qsys"]
+
+set_global_assignment -library "lib_int_osc" -name MISC_FILE [file join $::quartus(sip_path) "int_osc.v"]
+set_global_assignment -library "lib_int_osc" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_int_osc.v"]

fpga/ip/int_osc/simulation/int_osc.v

@@ -0,0 +1,16 @@
+// int_osc.v
+
+// Generated using ACDS version 20.1 720
+
+`timescale 1 ps / 1 ps
+module int_osc (
+		output wire  clkout, // clkout.clk
+		input  wire  oscena  // oscena.oscena
+	);
+
+	altera_int_osc int_osc_0 (
+		.oscena (oscena), // oscena.oscena
+		.clkout (clkout)  // clkout.clk
+	);
+
+endmodule

fpga/ip/int_osc/simulation/mentor/msim_setup.tcl

@@ -0,0 +1,264 @@
+
+# (C) 2001-2021 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     int_osc
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If int_osc is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2021.12.01.09:19:29
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "int_osc"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/opt/altera/20.1/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib          ./libraries/     
+ensure_lib          ./libraries/work/
+vmap       work     ./libraries/work/
+vmap       work_lib ./libraries/work/
+if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+  ensure_lib                  ./libraries/altera_ver/      
+  vmap       altera_ver       ./libraries/altera_ver/      
+  ensure_lib                  ./libraries/lpm_ver/         
+  vmap       lpm_ver          ./libraries/lpm_ver/         
+  ensure_lib                  ./libraries/sgate_ver/       
+  vmap       sgate_ver        ./libraries/sgate_ver/       
+  ensure_lib                  ./libraries/altera_mf_ver/   
+  vmap       altera_mf_ver    ./libraries/altera_mf_ver/   
+  ensure_lib                  ./libraries/altera_lnsim_ver/
+  vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver/
+  ensure_lib                  ./libraries/cycloneive_ver/  
+  vmap       cycloneive_ver   ./libraries/cycloneive_ver/  
+}
+ensure_lib           ./libraries/int_osc_0/
+vmap       int_osc_0 ./libraries/int_osc_0/
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver      
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"          -work lpm_ver         
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"             -work sgate_ver       
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"         -work altera_mf_ver   
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"     -work altera_lnsim_ver
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v"  -work cycloneive_ver  
+  }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_int_osc.v" -work int_osc_0
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/int_osc.v"                                  
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L int_osc_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -voptargs=+acc option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L int_osc_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -voptargs=+acc
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h

fpga/ip/int_osc/simulation/submodules/altera_int_osc.v

@@ -0,0 +1,45 @@
+//altint_osc CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone IV E" clkout oscena
+//VERSION_BEGIN 20.1 cbx_altint_osc 2020:11:11:17:03:37:SJ cbx_arriav 2020:11:11:17:03:36:SJ cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_compare 2020:11:11:17:03:37:SJ cbx_lpm_counter 2020:11:11:17:03:37:SJ cbx_lpm_decode 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_nightfury 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_stratixiii 2020:11:11:17:03:37:SJ cbx_stratixv 2020:11:11:17:03:37:SJ cbx_tgx 2020:11:11:17:03:37:SJ cbx_zippleback 2020:11:11:17:03:37:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2020  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and any partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details, at
+//  https://fpgasoftware.intel.com/eula.
+
+
+
+//synthesis_resources = cycloneive_oscillator 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  altera_int_osc
+	( 
+	clkout,
+	oscena) /* synthesis synthesis_clearbox=1 */;
+	output   clkout;
+	input   oscena;
+
+	wire  wire_sd1_clkout;
+
+	cycloneive_oscillator   sd1
+	( 
+	.clkout(wire_sd1_clkout),
+	.oscena(oscena));
+	assign
+		clkout = wire_sd1_clkout;
+endmodule //altera_int_osc
+//VALID FILE

fpga/ip/int_osc/simulation/synopsys/vcs/vcs_setup.sh

@@ -0,0 +1,147 @@
+
+# (C) 2001-2021 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2021.12.01.09:19:29
+
+# ----------------------------------------
+# vcs - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     int_osc
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, follow the guidelines below.
+# 
+# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
+# below into a new file, e.g. named "vcs_sim.sh".
+# 
+# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
+# a separate file, e.g. named "filelist.f".
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
+# # set the top-level simulation or testbench module/entity name.
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# # Source the Quartus-generated IP simulation script and do the following:
+# # - Compile the Quartus EDA simulation library and IP simulation files.
+# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
+# # - Compile the design and top-level simulation module/entity using
+# #   information specified in "filelist.f".
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# # - Run the simulation.
+# #
+# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
+# TOP_LEVEL_NAME=<simulation top> \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# ----------------------------------------
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the Quartus-generated IP simulation script)
+# #
+# +systemverilogext+.sv
+# <design and testbench files, compile-time options, elaboration options>
+# #
+# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If int_osc is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2021.12.01.09:19:29
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="int_osc"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/opt/altera/20.1/quartus/"
+SKIP_FILE_COPY=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
+  $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
+  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v \
+  $QSYS_SIMDIR/submodules/altera_int_osc.v \
+  $QSYS_SIMDIR/int_osc.v \
+  -top $TOP_LEVEL_NAME
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

fpga/ip/int_osc/simulation/synopsys/vcsmx/synopsys_sim.setup

@@ -0,0 +1,11 @@
+
+WORK > DEFAULT
+DEFAULT:          ./libraries/work/            
+work:             ./libraries/work/            
+int_osc_0:        ./libraries/int_osc_0/       
+altera_ver:       ./libraries/altera_ver/      
+lpm_ver:          ./libraries/lpm_ver/         
+sgate_ver:        ./libraries/sgate_ver/       
+altera_mf_ver:    ./libraries/altera_mf_ver/   
+altera_lnsim_ver: ./libraries/altera_lnsim_ver/
+cycloneive_ver:   ./libraries/cycloneive_ver/  

fpga/ip/int_osc/simulation/synopsys/vcsmx/vcsmx_setup.sh

@@ -0,0 +1,189 @@
+
+# (C) 2001-2021 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 20.1 720 linux 2021.12.01.09:19:29
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     int_osc
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries 
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If int_osc is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 20.1 720 linux 2021.12.01.09:19:29
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="int_osc"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/opt/altera/20.1/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/int_osc_0/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/cycloneive_ver/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver      
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"          -work lpm_ver         
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"             -work sgate_ver       
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"         -work altera_mf_ver   
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"     -work altera_lnsim_ver
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v"  -work cycloneive_ver  
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_int_osc.v" -work int_osc_0
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/int_osc.v"                                  
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

fpga/ip/int_osc/synthesis/int_osc.debuginfo

@@ -0,0 +1,388 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="int_osc" kind="system" version="20.1" fabric="QSYS">
+ <!-- Format version 20.1 720 (Future versions may contain additional information.) -->
+ <!-- 2021.12.01.09:19:29 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>EP4CE15F17C8</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>CYCLONEIVE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>8</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1638379169</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>true</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="int_osc_0"
+   kind="altera_int_osc"
+   version="20.1"
+   path="int_osc_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="INFORMATION">
+   <type>java.lang.String</type>
+   <value>The maximum output frequency is 80MHz</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>CYCLONEIVE</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="PART_NAME">
+   <type>java.lang.String</type>
+   <value>EP4CE15F17C8</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE</sysinfo_type>
+  </parameter>
+  <parameter name="DEVICE_ID">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLOCK_FREQUENCY_1">
+   <type>java.lang.String</type>
+   <value>116</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLOCK_FREQUENCY_2">
+   <type>java.lang.String</type>
+   <value>77</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CLOCK_FREQUENCY">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>true</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="CBX_AUTO_BLACKBOX">
+   <type>java.lang.String</type>
+   <value>ALL</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="oscena" kind="conduit_end" version="20.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>INPUT</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>oscena</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>oscena</role>
+   </port>
+  </interface>
+  <interface name="clkout" kind="clock_source" version="20.1">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>OUTPUT</value>
+   </assignment>
+   <parameter name="associatedDirectClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRate">
+    <type>long</type>
+    <value>0</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="clockRateKnown">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="externallyDriven">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="ptfSchematicName">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>false</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>clock</type>
+   <isStart>true</isStart>
+   <port>
+    <name>clkout</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>clk</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altera_int_osc</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>Internal Oscillator</displayName>
+  <version>20.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>20.1</version>
+ </plugin>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>clock_source</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Clock Output</displayName>
+  <version>20.1</version>
+ </plugin>
+ <reportVersion>20.1 720</reportVersion>
+ <uniqueIdentifier>5254001B7C8D0000017D7702274A</uniqueIdentifier>
+</EnsembleReport>

fpga/ip/int_osc/synthesis/int_osc.v

@@ -0,0 +1,16 @@
+// int_osc.v
+
+// Generated using ACDS version 20.1 720
+
+`timescale 1 ps / 1 ps
+module int_osc (
+		output wire  clkout, // clkout.clk
+		input  wire  oscena  // oscena.oscena
+	);
+
+	altera_int_osc int_osc_0 (
+		.oscena (oscena), // oscena.oscena
+		.clkout (clkout)  // clkout.clk
+	);
+
+endmodule

fpga/ip/int_osc/synthesis/submodules/altera_int_osc.v

@@ -0,0 +1,45 @@
+//altint_osc CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone IV E" clkout oscena
+//VERSION_BEGIN 20.1 cbx_altint_osc 2020:11:11:17:03:37:SJ cbx_arriav 2020:11:11:17:03:36:SJ cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_compare 2020:11:11:17:03:37:SJ cbx_lpm_counter 2020:11:11:17:03:37:SJ cbx_lpm_decode 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_nightfury 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_stratixiii 2020:11:11:17:03:37:SJ cbx_stratixv 2020:11:11:17:03:37:SJ cbx_tgx 2020:11:11:17:03:37:SJ cbx_zippleback 2020:11:11:17:03:37:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2020  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and any partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details, at
+//  https://fpgasoftware.intel.com/eula.
+
+
+
+//synthesis_resources = cycloneive_oscillator 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  altera_int_osc
+	( 
+	clkout,
+	oscena) /* synthesis synthesis_clearbox=1 */;
+	output   clkout;
+	input   oscena;
+
+	wire  wire_sd1_clkout;
+
+	cycloneive_oscillator   sd1
+	( 
+	.clkout(wire_sd1_clkout),
+	.oscena(oscena));
+	assign
+		clkout = wire_sd1_clkout;
+endmodule //altera_int_osc
+//VALID FILE

fpga/ip/pll2.v

@@ -0,0 +1,321 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll2.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll2 (
+	areset,
+	inclk0,
+	c0,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "LOW",
+		altpll_component.clk0_divide_by = 1,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 1,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20833,
+		altpll_component.intended_device_family = "Cyclone IV E",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll2",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "ON",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON

fpga/ip/pll.v → fpga/ip/pll3.v

@@ -4,7 +4,7 @@
 // MODULE: altpll 
 
 // ============================================================
-// File Name: pll.v
+// File Name: pll3.v
 // Megafunction Name(s):
 // 			altpll
 //
@@ -37,50 +37,33 @@
 // synopsys translate_off
 `timescale 1 ps / 1 ps
 // synopsys translate_on
-module pll (
+module pll3 (
 	areset,
 	inclk0,
-	phasecounterselect,
-	phasestep,
-	phaseupdown,
-	scanclk,
 	c0,
 	c1,
 	c2,
 	c3,
-	c4,
-	locked,
-	phasedone);
+	locked);
 
 	input	  areset;
 	input	  inclk0;
-	input	[2:0]  phasecounterselect;
-	input	  phasestep;
-	input	  phaseupdown;
-	input	  scanclk;
 	output	  c0;
 	output	  c1;
 	output	  c2;
 	output	  c3;
-	output	  c4;
 	output	  locked;
-	output	  phasedone;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_off
 `endif
 	tri0	  areset;
-	tri0	[2:0]  phasecounterselect;
-	tri0	  phasestep;
-	tri0	  phaseupdown;
 `ifndef ALTERA_RESERVED_QIS
 // synopsys translate_on
 `endif
 
 	wire [4:0] sub_wire0;
-	wire  sub_wire6;
-	wire  sub_wire7;
-	wire [0:0] sub_wire10 = 1'h0;
-	wire [4:4] sub_wire5 = sub_wire0[4:4];
+	wire  sub_wire5;
+	wire [0:0] sub_wire8 = 1'h0;
 	wire [3:3] sub_wire4 = sub_wire0[3:3];
 	wire [2:2] sub_wire3 = sub_wire0[2:2];
 	wire [1:1] sub_wire2 = sub_wire0[1:1];
@@ -89,22 +72,15 @@ module pll (
 	wire  c1 = sub_wire2;
 	wire  c2 = sub_wire3;
 	wire  c3 = sub_wire4;
-	wire  c4 = sub_wire5;
-	wire  locked = sub_wire6;
-	wire  phasedone = sub_wire7;
-	wire  sub_wire8 = inclk0;
-	wire [1:0] sub_wire9 = {sub_wire10, sub_wire8};
+	wire  locked = sub_wire5;
+	wire  sub_wire6 = inclk0;
+	wire [1:0] sub_wire7 = {sub_wire8, sub_wire6};
 
 	altpll	altpll_component (
 				.areset (areset),
-				.inclk (sub_wire9),
-				.phasecounterselect (phasecounterselect),
-				.phasestep (phasestep),
-				.phaseupdown (phaseupdown),
-				.scanclk (scanclk),
+				.inclk (sub_wire7),
 				.clk (sub_wire0),
-				.locked (sub_wire6),
-				.phasedone (sub_wire7),
+				.locked (sub_wire5),
 				.activeclock (),
 				.clkbad (),
 				.clkena ({6{1'b1}}),
@@ -121,8 +97,13 @@ module pll (
 				.fref (),
 				.icdrclk (),
 				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
 				.pllena (1'b1),
 				.scanaclr (1'b0),
+				.scanclk (1'b0),
 				.scanclkena (1'b1),
 				.scandata (1'b0),
 				.scandataout (),
@@ -138,12 +119,12 @@ module pll (
 		altpll_component.clk0_divide_by = 2,
 		altpll_component.clk0_duty_cycle = 50,
 		altpll_component.clk0_multiply_by = 7,
-		altpll_component.clk0_phase_shift = "744",
-		altpll_component.clk1_divide_by = 4,
+		altpll_component.clk0_phase_shift = "186",
+		altpll_component.clk1_divide_by = 2,
 		altpll_component.clk1_duty_cycle = 50,
 		altpll_component.clk1_multiply_by = 7,
 		altpll_component.clk1_phase_shift = "0",
-		altpll_component.clk2_divide_by = 6,
+		altpll_component.clk2_divide_by = 4,
 		altpll_component.clk2_duty_cycle = 50,
 		altpll_component.clk2_multiply_by = 7,
 		altpll_component.clk2_phase_shift = "0",
@@ -151,13 +132,9 @@ module pll (
 		altpll_component.clk3_duty_cycle = 50,
 		altpll_component.clk3_multiply_by = 14,
 		altpll_component.clk3_phase_shift = "0",
-		altpll_component.clk4_divide_by = 2,
-		altpll_component.clk4_duty_cycle = 50,
-		altpll_component.clk4_multiply_by = 7,
-		altpll_component.clk4_phase_shift = "0",
 		altpll_component.inclk0_input_frequency = 20833,
 		altpll_component.intended_device_family = "Cyclone IV E",
-		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll3",
 		altpll_component.lpm_type = "altpll",
 		altpll_component.operation_mode = "NO_COMPENSATION",
 		altpll_component.pll_type = "AUTO",
@@ -173,13 +150,13 @@ module pll (
 		altpll_component.port_inclk1 = "PORT_UNUSED",
 		altpll_component.port_locked = "PORT_USED",
 		altpll_component.port_pfdena = "PORT_UNUSED",
-		altpll_component.port_phasecounterselect = "PORT_USED",
-		altpll_component.port_phasedone = "PORT_USED",
-		altpll_component.port_phasestep = "PORT_USED",
-		altpll_component.port_phaseupdown = "PORT_USED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
 		altpll_component.port_pllena = "PORT_UNUSED",
 		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_USED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
 		altpll_component.port_scanclkena = "PORT_UNUSED",
 		altpll_component.port_scandata = "PORT_UNUSED",
 		altpll_component.port_scandataout = "PORT_UNUSED",
@@ -190,7 +167,7 @@ module pll (
 		altpll_component.port_clk1 = "PORT_USED",
 		altpll_component.port_clk2 = "PORT_USED",
 		altpll_component.port_clk3 = "PORT_USED",
-		altpll_component.port_clk4 = "PORT_USED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
 		altpll_component.port_clk5 = "PORT_UNUSED",
 		altpll_component.port_clkena0 = "PORT_UNUSED",
 		altpll_component.port_clkena1 = "PORT_UNUSED",
@@ -203,10 +180,7 @@ module pll (
 		altpll_component.port_extclk2 = "PORT_UNUSED",
 		altpll_component.port_extclk3 = "PORT_UNUSED",
 		altpll_component.self_reset_on_loss_lock = "ON",
-		altpll_component.vco_frequency_control = "MANUAL_PHASE",
-		altpll_component.vco_phase_shift_step = 1,
-		altpll_component.width_clock = 5,
-		altpll_component.width_phasecounterselect = 3;
+		altpll_component.width_clock = 5;
 
 
 endmodule
@@ -218,7 +192,7 @@ endmodule
 // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
 // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
 // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
@@ -231,20 +205,17 @@ endmodule
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "4"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "6"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "4"
 // Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "5"
-// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "2"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "168.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "84.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "56.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "168.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "84.000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "134.399994"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "168.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -266,51 +237,41 @@ endmodule
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
-// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "1.00000000"
-// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 // Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
 // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "7"
 // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "14"
-// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "7"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "168.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "84.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "56.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "168.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "168.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "84.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "134.40000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "45.00000000"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "11.25000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -321,7 +282,7 @@ endmodule
 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll3.mif"
 // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
@@ -336,7 +297,6 @@ endmodule
 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
 // Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
@@ -344,12 +304,10 @@ endmodule
 // Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK2 STRING "1"
 // Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
 // Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -357,12 +315,12 @@ endmodule
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "744"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "186"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "6"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
 // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "7"
 // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
@@ -370,10 +328,6 @@ endmodule
 // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "14"
 // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "7"
-// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
@@ -391,13 +345,13 @@ endmodule
 // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
@@ -408,7 +362,7 @@ endmodule
 // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
@@ -421,44 +375,29 @@ endmodule
 // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
-// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "1"
 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-// Retrieval info: CONSTANT: WIDTH_PHASECOUNTERSELECT NUMERIC "3"
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
 // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 // Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-// Retrieval info: USED_PORT: phasecounterselect 0 0 3 0 INPUT GND "phasecounterselect[2..0]"
-// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
-// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
-// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
-// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
 // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: @phasecounterselect 0 0 3 0 phasecounterselect 0 0 3 0
-// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
-// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
-// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
 // Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll3.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll3.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll3.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll3.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll3.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll3_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll3_bb.v TRUE
 // Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON

fpga/ip/pll4.v

@@ -0,0 +1,349 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll4.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2020  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and any partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details, at
+//https://fpgasoftware.intel.com/eula.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll4 (
+	areset,
+	inclk0,
+	c0,
+	c1,
+	locked);
+
+	input	  areset;
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  locked;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire3;
+	wire [0:0] sub_wire6 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  locked = sub_wire3;
+	wire  sub_wire4 = inclk0;
+	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+	altpll	altpll_component (
+				.areset (areset),
+				.inclk (sub_wire5),
+				.clk (sub_wire0),
+				.locked (sub_wire3),
+				.activeclock (),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "LOW",
+		altpll_component.clk0_divide_by = 6,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 35,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 6,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 7,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20833,
+		altpll_component.intended_device_family = "Cyclone IV E",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll4",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "ON",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "6"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "280.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "56.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "35"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "280.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "56.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll4.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "35"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll4.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll4.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll4.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll4.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll4.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll4_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll4_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON

fpga/max80.pins

@@ -29,8 +29,8 @@ m2	abc_inp_n[1]
 m1	abc_a[13]
 j2	abc_out_n[1]
 j1	abc_a[9]
-# k6	N/C
-# l6	N/C
+# k6	GPIO N/C
+l6	rngio[0]
 l3	abc_out_n[3]
 k1	abc_a[11]
 l2	abc_inp_n[0]
@@ -69,13 +69,13 @@ n5	abc_d[2]
 n6	spi_cs_flash_n
 
 # Bank 4
-# l11	N/C
-# k9	N/C
+# l11	GPIO N/C
+# k9	GPIO N/C
 m11	hdmi_scl
-# l9	N/C
+# l9	GPIO N/C
 t13	led[0]
-# m9	N/C
-# r9	VCC
+# m9	GPIO N/C
+# r9	GPI  VCC
 n9	exth_hb
 t9	exth_hc
 r10	gpio[3]
@@ -84,7 +84,7 @@ r11	exth_hd
 t11	exth_hf
 r12	exth_he
 t12	abc_xinpstb_n
-# k10	N/C
+k10	board_id
 l10	abc_xoutpstb_n
 p9	gpio[1]
 n12	exth_ha
@@ -93,31 +93,31 @@ r13	hdmi_sda
 t14	led[1]
 t15	hdmi_hpd
 m10	sd_dat[1]
-# p11	N/C
+p11	rngio[1]
 p14	tty_dtr
 r14	led[2]
 
 # Bank 5 (2.5 V)
-# n14	N/C
-# p15	N/C
-# p16	hdmi_d[2](n)
+# n14	GPIO N/C
+# p15	GPIO N/C
+p16	hdmi_d[2](n)
 r16	hdmi_d[2]
-# k17	N/C
-# n16	hdmi_d[1](n)
+# k12	GPIO N/C
+n16	hdmi_d[1](n)
 n15	hdmi_d[1]
-# l14	N/C
-# l13	N/C
-# l16	N/C
-# l15	N/C
-# k16	hdmi_d[0](n)
+# l14	GPIO N/C
+# l13	GPIO N/C
+# l16	GPIO N/C
+# l15	GPIO N/C
+k16	hdmi_d[0](n)
 k15	hdmi_d[0]
-# j16	hdmi_clk(n)
+j16	hdmi_clk(n)
 j15	hdmi_clk
-# m16	GND
-# j14	N/C
+# m16	GPI  GND
+# j14	GPIO N/C
 m15	clock_48
-# j12	N/C
-# j13	N/C
+# j12	GPIO N/C
+# j13	GPIO N/C
 
 # Bank 6
 e16	tty_txd		# BOARD REWORK!!!
@@ -135,7 +135,7 @@ b16	rtc_int_n
 f14	sd_dat[2]
 d16	tty_rts
 d15	tty_cts
-# g11	N/C
+g11	rngio[2]
 c16	i2c_scl
 c15	i2c_sda
 
@@ -163,7 +163,7 @@ c9	sr_a[4]
 d9	sr_a[5]
 e9	sr_cas_n
 a9	abc_a[2]
-# a8	abc_a[2]
+# b9	GPI  abc_a[2]
 
 # Bank 8
 d8	sr_dqm[1]
@@ -188,5 +188,5 @@ a2	abc_int800_x
 d5	sr_dq[15]
 a3	abc_nmi_x
 b3	abc_int80_x
-# c3	N/C
+# c3	GPIO N/C
 d3	sr_clk

fpga/max80.qsf

@@ -119,6 +119,7 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_clk
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to flash_cs_n
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_miso
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to flash_mosi
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to board_id
 set_instance_assignment -name IO_STANDARD "2.5 V" -to clock_48
 
 
@@ -221,6 +222,39 @@ set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
 set_global_assignment -name POWER_USE_TA_VALUE 35
 
 
+
+
+set_location_assignment PLL_3 -to "pll3:pll3|altpll:altpll_component|pll3_altpll:auto_generated|pll1"
+set_location_assignment PLL_4 -to "pll4:pll4|altpll:altpll_component|pll4_altpll:auto_generated|pll1"
+set_location_assignment PLL_2 -to "pll2:pll2|altpll:altpll_component|pll2_altpll:auto_generated|pll1"
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[15]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[14]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[13]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[12]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[11]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[10]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[9]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sr_dq[8]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[7]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[4]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sr_dq[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rngio[2]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+set_global_assignment -name SYSTEMVERILOG_FILE rng.sv
+set_global_assignment -name VERILOG_FILE ip/int_osc/synthesis/int_osc.v
+set_global_assignment -name QIP_FILE ip/int_osc/synthesis/int_osc.qip
+set_global_assignment -name VERILOG_FILE ip/int_osc/synthesis/submodules/altera_int_osc.v
+set_global_assignment -name VERILOG_FILE ip/pll4.v
+set_global_assignment -name VERILOG_FILE ip/pll3.v
+set_global_assignment -name VERILOG_FILE ip/pll2.v
 set_global_assignment -name VERILOG_FILE usb/usb_fs_phy/src_v/usb_fs_phy.v
 set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_tx.v
 set_global_assignment -name VERILOG_FILE usb/usb_serial/src_v/usbf_sie_rx.v
@@ -252,7 +286,6 @@ set_global_assignment -name TCL_SCRIPT_FILE scripts/post_quartus_asm.tcl
 set_global_assignment -name TCL_SCRIPT_FILE scripts/postmodule.tcl
 set_global_assignment -name SOURCE_FILE max80jic.cof
 set_global_assignment -name VERILOG_FILE ip/hdmitx.v
-set_global_assignment -name VERILOG_FILE ip/pll.v
 set_global_assignment -name SYSTEMVERILOG_FILE transpose.sv
 set_global_assignment -name SYSTEMVERILOG_FILE synchro.sv
 set_global_assignment -name SYSTEMVERILOG_FILE tmdsenc.sv
@@ -262,6 +295,3 @@ set_global_assignment -name SOURCE_FILE max80.pins
 set_global_assignment -name SOURCE_TCL_SCRIPT_FILE scripts/pins.tcl
 set_global_assignment -name VERILOG_FILE ip/fifo.v
 set_global_assignment -name VERILOG_FILE ip/ddufifo.v
-
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/max80.sdc

@@ -18,17 +18,19 @@ set_false_path -to [get_registers sld_signaltap:*]
 
 # -------- PLL clock mappings --------
 
-set sdram_out_clk [get_clocks {pll|*|clk[0]}]
-set sdram_clk     [get_clocks {pll|*|clk[4]}]
-set sys_clk       [get_clocks {pll|*|clk[1]}]
-set vid_clk       [get_clocks {pll|*|clk[2]}]
-set flash_clk     [get_clocks {pll|*|clk[3]}]
+set sdram_clk     [get_clocks {pll3|*|clk[0]}]
+set sdram_out_clk [get_clocks {pll3|*|clk[1]}]
+set sys_clk       [get_clocks {pll3|*|clk[2]}]
+set flash_clk     [get_clocks {pll3|*|clk[3]}]
+set hdmi_clk      [get_clocks {pll4|*|clk[0]}]
+set vid_clk       [get_clocks {pll4|*|clk[1]}]
+set usb_clk       [get_clocks {pll2|*|clk[0]}]
 
-set main_clocks   [get_clocks {pll|*}]
+set main_clocks   [get_clocks {pll*|*|clk[*]}]
 
 # Reset isn't actually a clock, but Quartus thinks it is
 create_generated_clock -name rst_n \
-    -source [get_nets {pll|*|*clk[1]}] \
+    -source [get_nets {pll3|*|*clk[2]}] \
     [get_registers rst_n]
 
 # Reset is asynchronous  with everything as far as we are concerned.
@@ -49,15 +51,15 @@ set_multicycle_path -from [all_clocks] -to $synchro_inputs \
 
 # -------- SDRAM I/O constraints --------
 
-set sr_data_out [remove_from_collection [get_ports sr_*] sr_clk]
-set sr_data_in  [get_ports sr_dq\[*\]]
-set_max_skew -to $sr_data_out 0.100ns
-set_input_delay  -clock $sdram_clk 0.500ns  $sr_data_in
+#set sr_data_out [remove_from_collection [get_ports sr_*] sr_clk]
+#set sr_data_in  [get_ports sr_dq\[*\]]
+#set_max_skew -to $sr_data_out 0.100ns
+#set_input_delay  -clock $sdram_clk 0.500ns  $sr_data_in
 
-set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
-    -start -setup 2
-set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
-    -start -hold 0
+#set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
+#    -start -setup 2
+#set_multicycle_path -from $sdram_clk -to $sdram_out_clk \
+#    -start -hold 0
 
 # -------- SDRAM multicycle paths (ready is retarded) --------
 

fpga/max80.sv

@@ -11,6 +11,7 @@
 module max80 (
 	      // Clock oscillator
 	      input	    clock_48, // 48 MHz
+	      input	    board_id,
 
 	      // ABC-bus
 	      input	    abc_clk, // ABC-bus 3 MHz clock
@@ -109,40 +110,75 @@ module max80 (
 	      output	    hdmi_clk,
 	      inout	    hdmi_scl,
 	      inout	    hdmi_sda,
-	      inout	    hdmi_hpd
+	      inout	    hdmi_hpd,
+
+	      // Unconnected pins with pullups, used for randomness
+	      inout [2:0]   rngio
 	      );
 
-   // PLL and reset
-   parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles after PLL lock
+   // -----------------------------------------------------------------------
+   //   PLLs and reset
+   // -----------------------------------------------------------------------
+
+   // Assert internal reset for 4096 cycles after PLL lock
+   parameter reset_pow2 = 12;
+
    reg			    rst_n   = 1'b0;	// Internal reset
-   wire [1:0]		    pll_locked;
+   tri1 [4:1]		    pll_locked;
+
+   //
+   // Clocks.
+   //
+   //  All clocks are derived from a common 48 MHz oscillator
+   //  connected to clock_48, which is a dedicated clock pin
+   //  feeding into hardware PLL2 and PLL4. The SDRAM clock output
+   //  is a dedicated clock out pin from PLL3.
+   //
+   //  sys_clk and sdram_clk are very closely tied; the logic
+   //  assumes in a very large number of places that
+   //  sdram_clk = sys_clk x 2 and that they are synchronous. Therefore
+   //  they better come out of the same PLL!
+   //
+   wire	    sdram_clk;		// 168 MHz SDRAM clock
+   wire	    sys_clk;		//  84 MHz System clock
+   wire	    vid_clk;		//  56 MHz Video pixel clock
+   wire	    vid_hdmiclk;	// 280 MHz HDMI serializer clock = vid_clk x 5
+   wire     flash_clk;		// 134 MHz Serial flash ROM clock
+   wire     usb_clk;		//  48 MHz USB clock
 
-   // Clocks
-   wire	    sdram_clk;		// SDRAM clock
-   wire	    sdram_out_clk;	// SDRAM clock, phase shifted
-   wire	    sys_clk;		// System clock
-   wire	    vid_clk;		// Video pixel clock
-   wire	    vid_hdmiclk;	// D:o in the HDMI clock domain
-   wire     flash_clk;		// Serial flash ROM clock
+   wire     pll23_clk;		//  48 MHz PLL2 -> PLL3 clock transfer
+   assign   usb_clk = pll23_clk;
 
    reg	    reset_cmd_q = 1'b0;
    wire     reset_cmd;
 
-   pll pll (
-	    .areset ( reset_cmd_q ),
-	    .inclk0 ( clock_48 ),
-	    .c0 ( sdram_out_clk ),	// SDRAM external clock (168 MHz)
-	    .c1 ( sys_clk ),		// System clock (84 MHz)
-	    .c2 ( vid_clk ),		// Video pixel clock (56 MHz)
-	    .c3 ( flash_clk ),		// Serial flash ROM clock (134 MHz)
-	    .c4 ( sdram_clk ),		// SDRAM internal clock (168 MHz)
-	    .locked ( pll_locked[0] ),
-	    .phasestep ( 1'b0 ),
-	    .phasecounterselect ( 3'b0 ),
-	    .phaseupdown ( 1'b1 ),
-	    .scanclk ( 1'b0 ),
-	    .phasedone ( )
-	    );
+   pll2 pll2 (
+	      .areset ( reset_cmd_q ),
+	      .locked ( pll_locked[2] ),
+
+	      .inclk0 ( clock_48 ),
+	      .c0     ( pll23_clk )
+	      );
+
+   pll3 pll3 (
+	      .areset ( reset_cmd_q | ~pll_locked[2] ),
+	      .locked ( pll_locked[3] ),
+
+	      .inclk0 ( pll23_clk ),
+	      .c0     ( sr_clk ),	// Output to clock pin (phase shift)
+	      .c1     ( sdram_clk ),	// Internal logic/buffer data clock
+	      .c2     ( sys_clk ),
+	      .c3     ( flash_clk )
+	      );
+
+   pll4 pll4 (
+	      .areset ( reset_cmd_q ),
+	      .locked ( pll_locked[4] ),
+
+	      .inclk0 ( clock_48 ),
+	      .c0     ( vid_hdmiclk ),
+	      .c1     ( vid_clk )
+	      );
 
    wire all_plls_locked = &pll_locked;
 
@@ -182,14 +218,14 @@ module max80 (
 
    // HDMI video interface
    video video (
-		.rst_n      ( vid_rst_n ),
-		.vid_clk    ( vid_clk ),
-		.pll_locked ( pll_locked ),
-
-		.hdmi_d   ( hdmi_d ),
-		.hdmi_clk ( hdmi_clk ),
-		.hdmi_scl ( hdmi_scl ),
-		.hdmi_hpd ( hdmi_hpd )
+		.rst_n       ( vid_rst_n ),
+		.vid_clk     ( vid_clk ),
+		.vid_hdmiclk ( vid_hdmiclk ),
+
+		.hdmi_d      ( hdmi_d ),
+		.hdmi_clk    ( hdmi_clk ),
+		.hdmi_scl    ( hdmi_scl ),
+		.hdmi_hpd    ( hdmi_hpd )
 		);
 
    //
@@ -274,9 +310,7 @@ module max80 (
    sdram (
 	  .rst_n    ( rst_n ),
 	  .clk      ( sdram_clk ), // Internal clock
-	  .out_clk  ( sdram_out_clk ), // External clock (phase shifted)
 
-	  .sr_clk   ( sr_clk ),    // Output clock buffer
 	  .sr_cke   ( sr_cke ),
 	  .sr_cs_n  ( sr_cs_n ),
 	  .sr_ras_n ( sr_ras_n ),
@@ -501,7 +535,11 @@ module max80 (
    //
    wire        rtc_32khz_rework = 1'b1;
 
-   wire [ 7:0] max80_major = 8'd1;
+   reg	       board_id_q;
+   always @(posedge sys_clk)
+     board_id_q <= board_id;
+
+   wire [ 7:0] max80_major = ~board_id_q ? 8'd2 : 8'd1;
    wire [ 7:0] max80_minor = 8'd0;
    wire [15:0] max80_fixes = { 14'b0, rtc_32khz_rework }; // Workarounds
 
@@ -526,6 +564,15 @@ module max80 (
    assign led = led_q;
    assign sysreg_rdata[2] = { 29'b0, led_q };
 
+   // Random number generator
+   rng #(.nclocks(1), .width(32)) rng
+     (
+      .sys_clk ( sys_clk ),
+      .q       ( sysreg_rdata[4] ),
+      .clocks  ( { ~rtc_32khz } ),
+      .rngio   ( rngio )
+      );
+
    //
    // Serial ROM (also configuration ROM.) Fast hardwired data download
    // unit to SDRAM.
@@ -590,7 +637,7 @@ module max80 (
 
    max80_usb usb (
 		  .rst_n   ( rst_n ),
-		  .clock48 ( clock_48 ),
+		  .clock48 ( usb_clk ),
 		  .tty_rxd ( ),
 		  .tty_txd ( tty_data_out ),
 		  .usb_dp  ( gpio[3] ),

fpga/output_files/max80.jdi

@@ -1,8 +1,16 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="3d94b4a70488ee842ac5"/>
+    <hash md5_digest_80b="82012839ae94794ce2bd"/>
   </project>
   <file_info>
     <file device="EP4CE15F17C8" path="max80.sof" usercode="0xFFFFFFFF"/>
   </file_info>
+  <sld_infos>
+    <sld_info hpath="rng:rng|int_osc:int_osc" name="int_osc">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME int_osc HAS_SOPCINFO 1 GENERATION_ID 1638379169"/>
+      </assignment_values>
+      <parameters/>
+    </sld_info>
+  </sld_infos>
 </sld_project_info>

fpga/output_files/max80.pin

@@ -175,7 +175,7 @@ VCCINT                       : G7        : power  :                   : 1.2V
 VCCINT                       : G8        : power  :                   : 1.2V    :           :                
 VCCINT                       : G9        : power  :                   : 1.2V    :           :                
 VCCINT                       : G10       : power  :                   : 1.2V    :           :                
-GND*                         : G11       :        :                   :         : 6         :                
+rngio[2]                     : G11       : bidir  : 3.3-V LVTTL       :         : 6         : Y              
 MSEL2                        : G12       :        :                   :         : 6         :                
 GND                          : G13       : gnd    :                   :         :           :                
 VCCIO6                       : G14       : power  :                   : 3.3V    : 6         :                
@@ -212,7 +212,7 @@ GND*                         : J12       :        :                   :
 GND*                         : J13       :        :                   :         : 5         :                
 GND*                         : J14       :        :                   :         : 5         :                
 hdmi_clk                     : J15       : output : LVDS              :         : 5         : Y              
-hdmi_clk(n)                  : J16       : output : LVDS              :         : 5         : N              
+hdmi_clk(n)                  : J16       : output : LVDS              :         : 5         : Y              
 abc_a[11]                    : K1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_out_n[4]                 : K2        : input  : 3.3-V LVTTL       :         : 2         : Y              
 VCCIO2                       : K3        : power  :                   : 3.3V    : 2         :                
@@ -222,19 +222,19 @@ GND*                         : K6        :        :                   :
 VCCINT                       : K7        : power  :                   : 1.2V    :           :                
 GND                          : K8        : gnd    :                   :         :           :                
 GND*                         : K9        :        :                   :         : 4         :                
-GND*                         : K10       :        :                   :         : 4         :                
+board_id                     : K10       : input  : 3.3-V LVTTL       :         : 4         : Y              
 VCCINT                       : K11       : power  :                   : 1.2V    :           :                
 GND*                         : K12       :        :                   :         : 5         :                
 GND                          : K13       : gnd    :                   :         :           :                
 VCCIO5                       : K14       : power  :                   : 2.5V    : 5         :                
 hdmi_d[0]                    : K15       : output : LVDS              :         : 5         : Y              
-hdmi_d[0](n)                 : K16       : output : LVDS              :         : 5         : N              
+hdmi_d[0](n)                 : K16       : output : LVDS              :         : 5         : Y              
 abc_a[12]                    : L1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_inp_n[0]                 : L2        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_out_n[3]                 : L3        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_a[10]                    : L4        : input  : 3.3-V LVTTL       :         : 2         : Y              
 VCCA1                        : L5        : power  :                   : 2.5V    :           :                
-GND*                         : L6        :        :                   :         : 2         :                
+rngio[0]                     : L6        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
 gpio[0]                      : L7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 esp_io0                      : L8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 GND*                         : L9        :        :                   :         : 4         :                
@@ -276,7 +276,7 @@ exth_ha                      : N12       : bidir  : 3.3-V LVTTL       :
 VCCD_PLL4                    : N13       : power  :                   : 1.2V    :           :                
 GND*                         : N14       :        :                   :         : 5         :                
 hdmi_d[1]                    : N15       : output : LVDS              :         : 5         : Y              
-hdmi_d[1](n)                 : N16       : output : LVDS              :         : 5         : N              
+hdmi_d[1](n)                 : N16       : output : LVDS              :         : 5         : Y              
 abc_xmemw800_n               : P1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_rst_n                    : P2        : input  : 3.3-V LVTTL       :         : 2         : Y              
 abc_d[0]                     : P3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
@@ -287,12 +287,12 @@ VCCIO3                       : P7        : power  :                   : 3.3V
 esp_int                      : P8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 gpio[1]                      : P9        : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 VCCIO4                       : P10       : power  :                   : 3.3V    : 4         :                
-GND*                         : P11       :        :                   :         : 4         :                
+rngio[1]                     : P11       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
 GND                          : P12       : gnd    :                   :         :           :                
 VCCIO4                       : P13       : power  :                   : 3.3V    : 4         :                
 tty_dtr                      : P14       : input  : 3.3-V LVTTL       :         : 4         : Y              
 GND*                         : P15       :        :                   :         : 5         :                
-hdmi_d[2](n)                 : P16       : output : LVDS              :         : 5         : N              
+hdmi_d[2](n)                 : P16       : output : LVDS              :         : 5         : Y              
 abc_xmemw80_n                : R1        : input  : 3.3-V LVTTL       :         : 2         : Y              
 GND                          : R2        : gnd    :                   :         :           :                
 abc_d[4]                     : R3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              

fpga/output_files/max80.sld

@@ -1 +1,9 @@
-<sld_project_info/>
+<sld_project_info>
+  <sld_infos>
+    <sld_info hpath="rng:rng|int_osc:int_osc" name="int_osc">
+      <assignment_values>
+        <assignment_value text="QSYS_NAME int_osc HAS_SOPCINFO 1 GENERATION_ID 1638379169"/>
+      </assignment_values>
+    </sld_info>
+  </sld_infos>
+</sld_project_info>

fpga/rng.sv

@@ -0,0 +1,63 @@
+//
+// Simple hardware random number generator
+//
+
+module rng
+#(parameter
+  nclocks = 1,	// Asynchronous clocks
+  width = 32	// Output bus width
+  )
+   (
+    // System clock
+    input	       sys_clk,
+
+     // Output data
+    output [width-1:0] q,
+
+     // Randomness inputs
+    input [nclocks-1:0] clocks, // Asynchronous clocks
+    inout [2:0]        rngio		// Unconnected pins with pullups
+    );
+
+
+   wire		 int_clock;	// Internal oscillator clock
+
+   // Internal on-chip oscillator
+   int_osc int_osc
+     (
+      .clkout ( int_clock ),
+      .oscena ( 1'b1 )
+      );
+
+   // De facto RC oscillator using the rngio pins
+   assign rngio[0] = rngio[2] ? 1'b0 : 1'bz;
+   assign rngio[1] = rngio[0] ? 1'b0 : 1'bz;
+   assign rngio[2] = rngio[1] ? 1'b0 : 1'bz;
+
+   wire [nclocks+1:0] sclocks;
+
+   synchronizer #(.width(nclocks+2)) synchro
+     (
+      .rst_n ( 1'b1 ),
+      .clk ( sys_clk ),
+      .d ( { clocks, rngio[0], int_clk } ),
+      .q ( sclocks )
+      );
+
+   // LFSR randomness accumulator
+
+   // See http://users.ece.cmu.edu/~koopman/crc/crc36.html for
+   // choice of polynomial.
+   localparam poly_width = 33;
+   localparam [poly_width:0] poly = 34'h2_0000_009d;
+
+   localparam lsfr_max = width > poly_width ? width-1 : poly_width-1;
+
+   reg [lsfr_max:0] lsfr;
+
+   always @(posedge sys_clk)
+     lsfr <= {lsfr[lsfr_max-1:0], ^sclocks} ^
+	     (lsfr[lsfr_max-1] ? poly : {poly_width{1'b0}});
+
+   assign q = lsfr[lsfr_max:lsfr_max-width+1];
+endmodule // rng

fpga/sdram.sv

@@ -279,10 +279,8 @@ module sdram
 	      // Reset and clock
 	      input		rst_n,
 	      input		clk,
-	      input		out_clk, // Phase shifted external clock
 
 	      // SDRAM hardware interface
-	      output		sr_clk, // SDRAM clock output buffer
 	      output		sr_cke, // SDRAM clock enable
 	      output		sr_cs_n, // SDRAM CS#
 	      output		sr_ras_n, // SDRAM RAS#
@@ -347,31 +345,6 @@ module sdram
 
    assign       sr_cke   = 1'b1;
 
-`ifdef SD_CLK_USE_DDIO
-   // SDRAM output clock buffer. The SDRAM output clock is
-   // inverted with respect to our internal clock, so that
-   // the SDRAM sees the positive clock edge in the middle of
-   // our clocks.
-   //
-   // Use a DDIO buffer for best performance
-   // For EP4CE15 only could use a secondary PLL here, but it
-   // isn't clear it buys us a whole lot.
-   //
-   // This buffer is driven by a separate PLL output, so that
-   // the phase shift between the clock and the outputs/inputs
-   // can be tuned.
-   ddio_out sr_clk_out (
-			.aclr ( 1'b0 ),
-			.datain_h ( 1'b1 ),
-			.datain_l ( 1'b0 ),
-			.outclock ( out_clk ),
-			.dataout ( sr_clk )
-			);
-`else // !`ifdef SD_CLK_USE_DDIO
-   // Dedicated clock pin
-   assign sr_clk = out_clk;
-`endif
-
    // SDRAM output signal registers
    reg [12:0]		    dram_a;
    assign		    sr_a = dram_a;
@@ -409,14 +382,16 @@ module sdram
 
    // The actual values are unimportant; the compiler will optimize
    // the state machine implementation.
-   typedef enum logic [2:0] {
-	 st_reset,		// Reset until init timer expires
-	 st_init_rfsh,		// Refresh cycles during initialization
-	 st_init_mrd,		// MRD register write during initialization
-	 st_idle,		// Idle state: all banks precharged
-	 st_rfsh,
-	 st_rd_wr,		// Port 0/1 transaction
-	 st_wr2			// Port 2 write (burstable)
+   typedef enum logic [3:0] {
+	st_reset,		// Reset until init timer expires
+	st_init_rfsh,		// Refresh cycles during initialization
+	st_init_mrd,		// MRD register write during initialization
+	st_ready,		// Ready to issue command in the next cycle
+	st_rfsh,		// Refresh cycle
+        st_rd_wr_act,		// Port 1 ACT command
+	st_rd_wr,		// Port 1 transaction
+	st_wr2_act,		// Port 2 write ACT command
+	st_wr2			// Port 2 write (burstable)
    } state_t;
    state_t state = st_reset;
 
@@ -452,11 +427,14 @@ module sdram
 
    reg [31:0] wdata_q;
    reg [ 3:0] be_q;
-   reg [ 9:0] col_addr;
+   reg [24:0] addr;
    reg	      wrq2_more;
 
-   assign p1.start = (state == st_idle);
-   assign p1.addr0 = col_addr[0];
+   wire [13:0] row_addr  = addr[24:12];
+   wire  [1:0] bank_addr = addr[11:10];
+   wire  [8:0] col_addr  = addr[9:1];
+   assign p1.addr0       = addr[0];
+
    assign p1.rd = dram_q;
 
    //
@@ -481,6 +459,7 @@ module sdram
 	  op_ctr        <= 6'h0;
 	  op_zero       <= 1'b0;
 	  state         <= st_reset;
+	  p1.start      <= 1'b0;
 	  p1.wrack      <= 1'bx;
 	  p1.rd         <= 16'hxxxx;
 	  p1.rstrb      <= 2'b00;
@@ -490,37 +469,37 @@ module sdram
 
 	  wdata_q       <= 32'hxxxx_xxxx;
 	  be_q          <= 4'bxxxx;
-	  col_addr      <= 10'hxxx;
+	  addr          <= 25'bx;
        end
      else
        begin
 	  // Default values
-	  // Note: dram_ba are preserved
 	  dram_a        <= 13'b0;
+	  dram_ba       <= bank_addr;
 	  dram_dqm      <= 2'b00;
 	  dram_d        <= 16'haaaa;
 	  dram_cmd      <= cmd_nop;
 
+
 	  dram_d_en     <= 1'b1; // Don't float except during read
 
 	  dram_q        <= sr_dq;
+	  if (~dram_d_en)
+	    dram_d      <= 16'hxxxx; // Allow losing contents when out disabled
 	  p1.rstrb      <= 2'b00;
 	  wacc2         <= 1'b0;
 
-	  if (state == st_reset || state == st_idle)
-	    begin
-	       op_ctr    <= 6'b0;
-	       op_zero   <= 1'b0;
-	    end
-	  else
-	    begin
-	       op_ctr <= op_ctr + 1'b1;
-	       op_zero <= &op_cycle; // About to wrap around
-	    end // else: !if(state == st_reset || state == st_idle)
+	  op_ctr  <= op_ctr + 1'b1;
+	  op_zero <= &op_cycle; // About to wrap around
+
+	  p1.start      <= 1'b0;
 
 	  case (state)
 	    st_reset:
 	      begin
+		 op_ctr  <= 6'b0;
+		 op_zero <= 1'b0;
+
 		 dram_a[10] <= 1'b1; // Precharge all banks
 
 		 dram_cmd  <= cmd_nop;
@@ -549,74 +528,74 @@ module sdram
 
 		 if (op_zero)
 		   if (init_op_ctr[0])
-		     state <= st_idle;
+		     state <= st_ready;
 		   else
 		     dram_cmd <= cmd_mrd;
 	      end
 
-	    st_idle:
+	    st_ready:
 	      begin
+		 op_ctr  <= 6'b0;
+		 op_zero <= 1'b0;
+
+		 dram_cmd <= cmd_desl;
+
 		 p1.wrack <= 1'bx;
 		 be_q     <= 4'bxxxx;
 		 wdata_q  <= 32'hxxxx_xxxx;
+		 addr     <= 25'bx;
 
-		 // A data transaction starts with ACTIVE command;
-		 // a refresh transaction starts with REFRESH.
-		 // Port 0 has the highest priority, then
-		 // refresh, then port 1; a refresh transaction
-		 // is started opportunistically if nothing is
-		 // pending and the refresh counter is no less than
-		 // half expired.
 		 dram_a  <= 13'h1bb;
-		 dram_ba <= 2'bxx;
 		 dram_d  <= 16'hbbbb;
 
+		 // Port 1 and refresh have priority over port 2;
+		 // the various port 1 instances and refresh have
+		 // priorities set by the arbiter block.
 		 if (do_rfsh)
 		   begin
-		      dram_cmd    <= cmd_ref;
-		      state       <= st_rfsh;
+		      state        <= st_rfsh;
 		   end
 		 else if (p1.req)
 		   begin
-		      dram_cmd     <= cmd_act;
-		      dram_a       <= p1.addr[24:12];
-		      dram_ba      <= p1.addr[11:10];
-		      col_addr     <= p1.addr[9:0];
+		      addr         <= p1.addr;
 		      p1.wrack     <= |p1.wstrb;
 		      wdata_q      <= p1.wd;
 		      be_q         <= p1.wstrb;
 		      state        <= st_rd_wr;
+		      p1.start     <= 1'b1;
 		   end // if (p1.req)
 		 else if (wrq2[0])
 		   begin
 		      // Begin port 2 write
-		      dram_cmd    <= cmd_act;
-		      dram_a      <= a2[24:12];
-		      dram_ba     <= a2[11:10];
-		      state       <= st_wr2;
-		   end
-		 else
-		   begin
-		      dram_cmd    <= cmd_desl;
-		      state       <= st_idle;
+		      addr         <= { a2, 1'b0 };
+		      state        <= st_wr2_act;
 		   end
-	      end // case: st_idle
+	      end // case: st_ready
 
-	    st_rfsh:
-	      begin
-		 if (op_cycle == t_rfc-2)
-		   state <= st_idle;
+	    st_rfsh: begin
+		 if (op_cycle == 0)
+		   dram_cmd    <= cmd_ref;
+		 else if (op_cycle == t_rfc-2)
+		   state <= st_ready;
 	      end
 
+	    st_rd_wr_act: begin
+	       op_ctr  <= 6'b0;
+	       op_zero <= 1'b0;
+
+	       dram_cmd <= cmd_act;
+	       dram_a   <= row_addr;
+	       dram_ba  <= bank_addr;
+
+	       state    <= st_rd_wr;
+	    end
+
 	    st_rd_wr:
 	      begin
 		 dram_d_en <= p1.wrack;
 		 dram_dqm  <= {2{p1.wrack}};
 		 dram_d    <= 16'hcccc ^ {16{p1.wrack}};
 
-		 if (op_cycle < 7)
-		   dram_q <= op_cycle * 16'h1111;
-
 		 // Commands
 		 //
 		 // This assumes:
@@ -631,7 +610,7 @@ module sdram
 		 case (op_cycle)
 		   2: begin
 		      dram_a[10]   <= 1'b0; // No auto precharge
-		      dram_a[8:0]  <= col_addr[9:1];
+		      dram_a[8:0]  <= col_addr;
 		      dram_cmd     <= p1.wrack ? cmd_wr : cmd_rd;
 		      dram_d       <= wdata_q[15:0];
 		      dram_dqm     <= {2{p1.wrack}} & ~be_q[1:0];
@@ -654,13 +633,23 @@ module sdram
 		   end
 		   8: begin
 		      p1.rstrb[1] <= ~p1.wrack;
-		   end
-		   9: begin
-		      state <= st_idle;
+		      state <= st_ready;
 		   end
 		 endcase // case (op_cycle)
 	      end // case: st_rd_wr
 
+	    st_wr2_act:
+	      begin
+		 op_ctr   <= 6'b0;
+		 op_zero  <= 1'b0;
+
+		 dram_a   <= row_addr;
+		 dram_ba  <= bank_addr;
+		 dram_cmd <= cmd_act;
+
+		 state    <= st_wr2;
+	      end
+
 	    st_wr2:
 	      begin
 		 // Streamable write from flash ROM
@@ -669,10 +658,7 @@ module sdram
 		 dram_a[8:0] <= a2[9:1];
 
 		 case (op_cycle)
-		   0: begin
-		      wacc2 <= 1'b1;
-		   end
-		   1: begin
+		   0, 1: begin
 		      wacc2 <= 1'b1;
 		   end
 		   2: begin
@@ -701,12 +687,9 @@ module sdram
 		      dram_dqm    <= 2'b11;
 		   end
 		   8: begin
+		      // tRP will be complete before the next ACT
 		      dram_dqm    <= 2'b11;
-		   end
-		   9: begin
-		      // tRP will be complete in the next cycle
-		      dram_dqm    <= 2'b11;
-		      state <= st_idle;
+		      state <= st_ready;
 		   end
 		 endcase // case (op_cycle)
 	      end // case: st_wr2

fpga/video.sv

@@ -1,7 +1,7 @@
 module video (
 	      input	   rst_n,
 	      input	   vid_clk,
-	      inout [1:0]  pll_locked,
+	      input	   vid_hdmiclk,
 
 	      output [2:0] hdmi_d,
 	      output	   hdmi_clk,
@@ -127,7 +127,7 @@ module video (
 	       .reverse_w ( 1'b0 ),
 	       .transpose ( 1'b0 ),
 	       .reg_d ( 1'b0 ),
-	       .reg_q ( 1'b0 )
+	       .reg_q ( 1'b1 )
 	       ) hdmitranspose
      (
       .clk ( vid_clk ),
@@ -136,15 +136,10 @@ module video (
       .q ( hdmi_to_tx )
       );
 
-   wire        vid_hdmiclk;
-
    hdmitx hdmitx (
-		  .pll_areset ( ~pll_locked[0] ),
 		  .tx_in ( hdmi_to_tx ),
-		  .tx_inclock ( vid_clk ),
-		  .tx_coreclock ( vid_hdmiclk ), // Pixel clock in HDMI domain
-		  .tx_locked ( pll_locked[1] ),
-		  .tx_out ( { hdmi_clk, hdmi_d } ),
-		  .tx_outclock ( )
+		  .tx_syncclock ( vid_clk ),
+		  .tx_inclock ( vid_hdmiclk ),
+		  .tx_out ( { hdmi_clk, hdmi_d } )
 		  );
 endmodule // video

fw/ioregs.h

@@ -52,15 +52,16 @@
 #define TIMER_HZ		(1 << TIMER_SHIFT)
 
 /* Basic system registers */
-#define SYS_MAGIC		IODEVL(SYS,0)
-#define SYS_BOARDCFG		IODEVL(SYS,1)
-#define SYS_BOARDFIX		IODEVH0(SYS,1)
+#define SYS_MAGIC		IODEVRL(SYS,0)
+#define SYS_BOARDCFG		IODEVRL(SYS,1)
+#define SYS_BOARDFIX		IODEVRH0(SYS,1)
 #define SYS_BOARDFIX_RTC32	1
-#define SYS_BOARDREV		IODEVH1(SYS,1)
-#define SYS_BOARDMINOR		IODEVB2(SYS,1)
-#define SYS_BOARDMAJOR		IODEVB3(SYS,1)
+#define SYS_BOARDREV		IODEVRH1(SYS,1)
+#define SYS_BOARDMINOR		IODEVRB2(SYS,1)
+#define SYS_BOARDMAJOR		IODEVRB3(SYS,1)
 #define SYS_LED			IODEVL(SYS,2)
 #define SYS_RESET		IODEVL(SYS,3)
+#define SYS_RANDOM		IODEVRL(SYS,4)
 
 #define ROMCOPY_RAMADDR		IODEVL(ROMCOPY,0)
 #define ROMCOPY_ROMADDR		IODEVL(ROMCOPY,1)

fw/system.c

@@ -65,6 +65,12 @@ void init(void)
     wait_romcopy_done();
     set_leds(5);
 
+#if 1
+    con_puts("Waiting 5 s for testing...");
+    udelay(5000000);
+    con_putc('\n');
+#endif
+
     /* This needs to be done as early as possible!!! */
     abc_init_memmap();
 
@@ -78,18 +84,31 @@ void init(void)
 		   (uint16_t)boardcfg);
     }
 
-    con_puts("Quick DRAM test:\n");
-    for (int i = 0; i < 8; i++) {
-	uint32_t v = (i*0x11111111) + 0x44332211;
-	test_dram[i] = v;
-	con_printf("%08x ", v);
+    if ( 1 ) {
+	con_puts("Quick DRAM test:\n");
+	for (int i = 0; i < 8; i++) {
+	    uint32_t v = (i*0x11111111) + 0x44332211;
+	    test_dram[i] = v;
+	    con_printf("%08x ", v);
+	}
+	con_putc('\n');
+	
+	for (int i = 0; i < 8; i++) {
+	    con_printf("%08x ", test_dram[i]);
+	}
+	con_puts("\n\n");
+
+	udelay(1000000);
     }
-    con_putc('\n');
 
-    for (int i = 0; i < 8; i++) {
-	con_printf("%08x ", test_dram[i]);
+    if ( 1 ) {
+	con_puts("Random number generator test:\n");
+	for (int i = 0; i < 8; i++) {
+	    uint32_t a = SYS_RANDOM;
+	    uint32_t b = SYS_RANDOM;
+	    con_printf("%08x %08x delta %08x\n", a, b, a^b);
+	}
     }
-    con_puts("\n\n");
 
     set_leds(4);