max80: better testing of the sdram controller

max80.sv

@@ -326,6 +326,7 @@ module max80 (
    reg	      abc_xmemrd_q;
    reg	      abc_xmemwr_q;
    reg	      abc_xmem_done;
+   reg [9:0]  abc_mempg;
 
    wire       abc_rack;
    wire       abc_wack;
@@ -339,6 +340,7 @@ module max80 (
 	  abc_xmemrd_q  <= 1'b0;
 	  abc_xmemwr_q  <= 1'b0;
 	  abc_xmem_done <= 1'b0;
+	  abc_mempg     <= 0;
        end
      else
        begin
@@ -351,8 +353,12 @@ module max80 (
 	  abc_rrq <= abc_xmemrd_q & ~(abc_xmem_done | abc_rack);
 	  abc_wrq <= abc_xmemwr_q & ~(abc_xmem_done | abc_wack);
 
-	  if (abc_rack)
+	  if (abc_rack & abc_rvalid)
 	    abc_do <= abc_sr_rd;
+
+	  // HACK FOR TESTING ONLY
+	  if (abc_iowr)
+	    abc_mempg <= { abc_a[1:0], abc_di };
        end // else: !if(~rst_n)
 
    sdram sdram (
@@ -370,10 +376,11 @@ module max80 (
 		.sr_a     ( sr_a ),
 		.sr_dq    ( sr_dq ),
 
-		.a0       ( { 9'b0, abc_a } ),
+		.a0       ( { abc_mempg, abc_a } ),
 		.rd0      ( abc_sr_rd ),
 		.rrq0     ( abc_rrq ),
 		.rack0    ( abc_rack ),
+		.rvalid0  ( abc_rvalid ),
 		.wd0      ( abc_d ),
 		.wrq0     ( abc_wrq ),
 		.wack0    ( abc_wack ),
@@ -383,6 +390,7 @@ module max80 (
 		.rd1      ( ),
 		.rrq1     ( 1'b0 ),
 		.rack1    ( ),
+		.rvalid1  ( ),
 		.wd1      ( 32'hxxxx_xxxx ),
 		.wrq1     ( 1'b0 ),
 		.wack1    ( )

output_files/max80.map

@@ -10,7 +10,7 @@ Quad-Serial configuration device dummy clock cycle: 8
 
 Notes:
 
-- Data checksum for this conversion is 0xF760705C
+- Data checksum for this conversion is 0xF76073A6
 
 - All the addresses in this file are byte addresses