Timing improvements: wait state for iodev, fix handling of sr_clk

fpga/ip/pll.v

@@ -155,12 +155,11 @@ module pll (
 		altpll_component.clk4_duty_cycle = 50,
 		altpll_component.clk4_multiply_by = 7,
 		altpll_component.clk4_phase_shift = "0",
-		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 20833,
 		altpll_component.intended_device_family = "Cyclone IV E",
 		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
 		altpll_component.lpm_type = "altpll",
-		altpll_component.operation_mode = "NORMAL",
+		altpll_component.operation_mode = "NO_COMPENSATION",
 		altpll_component.pll_type = "AUTO",
 		altpll_component.port_activeclock = "PORT_UNUSED",
 		altpll_component.port_areset = "PORT_USED",
@@ -225,7 +224,7 @@ endmodule
 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
 // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
 // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
 // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
@@ -283,7 +282,7 @@ endmodule
 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
 // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "14"
 // Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "7"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "168.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "84.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "48.00000000"
@@ -375,11 +374,10 @@ endmodule
 // Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "7"
 // Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
 // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"

fpga/max80.sdc

@@ -33,11 +33,9 @@ set vid_clk       [get_clocks pll|*|clk\[2\]]
 set flash_clk     [get_clocks pll|*|clk\[3\]]
 
 # SDRAM I/O constraints
-# set_max_skew -to [get_ports sr_*] 0.500ns
 set sr_data_out [remove_from_collection [get_ports sr_*] sr_clk]
 set sr_data_in  [get_ports sr_dq\[*\]]
-set_max_skew -to [get_ports sr_*] 0.100ns
-set_output_delay -clock $sdram_clk 1.500ns [get_ports sr_clk]
+set_max_skew -to $sr_data_out 0.100ns
 set_input_delay  -clock $sdram_clk 0.500ns  $sr_data_in
 
 # Anything that feeds into a synchronizer is by definition

fpga/max80.sv

@@ -573,7 +573,11 @@ module max80 (
 	sdram_rdata <= sdram_rd;
      end
 
+   // Add a mandatory wait state to iodevs to reduce the size
+   // of the CPU memory input MUX (it hurts timing on memory
+   // accesses...)
    tri1 [15:0] iodev_wait_n;
+   reg	       iodev_mem_ready;
 
    always @(*)
      case ( cpu_mem_quad )
@@ -581,7 +585,7 @@ module max80 (
        4'b0001: cpu_mem_ready = 1'b1;
        4'b0010: cpu_mem_ready = sdram_mem_ready;
        4'b0100: cpu_mem_ready = 1'b1;
-       4'b1000: cpu_mem_ready = &iodev_wait_n;
+       4'b1000: cpu_mem_ready = iodev_mem_ready;
        default: cpu_mem_ready = 1'bx;
      endcase // case ( mem_quad )
 
@@ -772,16 +776,24 @@ module max80 (
 		      .periodic ( sys_irq[3] )
 		      );
    //
-   // I/O device input data MUX
+   // I/O device input data (registered to reduce MUX overhead for
+   // the critical memory data paths.)
+   // abo
    //
-   always @(*)
+   always @(posedge sys_clk)
      case ( cpu_mem_addr[10:7] )
-       4'd0:    iodev_rdata  = { 29'b0, led_q };
-       4'd2:    iodev_rdata  = { 31'b0, rom_done_q };
-       4'd3:	iodev_rdata  = tty_rdata;
-       4'd4:    iodev_rdata  = sdcard_rdata;
-       4'd5:    iodev_rdata  = sysclock_rdata;
-       default: iodev_rdata  = 32'h0;
+       4'd0:    iodev_rdata  <= { 29'b0, led_q };
+       4'd2:    iodev_rdata  <= { 31'b0, rom_done_q };
+       4'd3:	iodev_rdata  <= tty_rdata;
+       4'd4:    iodev_rdata  <= sdcard_rdata;
+       4'd5:    iodev_rdata  <= sysclock_rdata;
+       default: iodev_rdata  <= 32'h0;
      endcase
 
+   always @(negedge rst_n or posedge sys_clk)
+     if (~rst_n)
+       iodev_mem_ready <= 1'b0;
+     else
+       iodev_mem_ready <= &iodev_wait_n & cpu_mem_valid;
+
 endmodule

fpga/sdram.sv

@@ -161,6 +161,7 @@ module sdram
 
    assign       sr_cke   = 1'b1;
 
+`ifdef SD_CLK_USE_DDIO
    // SDRAM output clock buffer. The SDRAM output clock is
    // inverted with respect to our internal clock, so that
    // the SDRAM sees the positive clock edge in the middle of
@@ -180,6 +181,10 @@ module sdram
 			.outclock ( out_clk ),
 			.dataout ( sr_clk )
 			);
+`else // !`ifdef SD_CLK_USE_DDIO
+   // Dedicated clock pin
+   assign sr_clk = out_clk;
+`endif
 
    // SDRAM output signal registers
    reg [12:0]		    dram_a;