usb: fix logic for draining tx FIFO, fix BREAK reception

The logic for draining the Tx FIFO was slightly off.

A BREAK message takes the interface number, not the endpoint number,
and they are offset by 1 due to endpoint 0 being the configuration
endpoint.

fpga/max80.qpf

@@ -19,12 +19,12 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 19:51:05  December 29, 2021
+# Date created = 20:03:37  January 08, 2022
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "21.1"
-DATE = "19:51:05  December 29, 2021"
+DATE = "20:03:37  January 08, 2022"
 
 # Revisions
 

fpga/usb/usb_serial/src_v/usb_cdc_core.sv

@@ -126,7 +126,9 @@ module usb_cdc_channel
 
 		    .rdclk   ( clk_i ),
 		    .q       ( data_ep.d.tx_data ),
-		    .rdreq   ( ~inport_valid_q | data_ep.u.tx_data_accept ),
+		    .rdreq   ( inport_valid_q
+			       ? data_ep.u.tx_data_accept
+			       : ~inport_empty_w ),
 		    .rdempty ( inport_empty_w ),
 		    .rdfull  ( ),
 		    .rdusedw ( )
@@ -238,13 +240,13 @@ module usb_cdc_channel
 
    tri0 [15:0] status;
    assign status[0]    = txempty;
-   assign status[1]    = (txused_msb <= water_ctl[3:4-water_bits]);
-   assign status[2]    = (txused_msb >= water_ctl[7:8-water_bits]);
+   assign status[1]    = txempty | (txused_msb <= water_ctl[3:4-water_bits]);
+   assign status[2]    = txfull  | (txused_msb >= water_ctl[7:8-water_bits]);
    assign status[3]    = txfull;
 
    assign status[4]    = rxempty;
-   assign status[5]    = (rxused_msb <= water_ctl[11:12-water_bits]);
-   assign status[6]    = (rxused_msb >= water_ctl[15:16-water_bits]);
+   assign status[5]    = rxempty | (rxused_msb <= water_ctl[11:12-water_bits]);
+   assign status[6]    = rxfull  | (rxused_msb >= water_ctl[15:16-water_bits]);
    assign status[7]    = rxfull;
 
    assign status[8]    = had_rxdata[1];
@@ -907,7 +909,10 @@ module usb_cdc_core
 			end
 		      `CDC_SEND_BREAK:
 			begin
-			   rx_break_r[wIndex_w[3:1]] = wIndex_w[0] & |wValue_w;
+			   // The break index is based on interfaces,
+			   // which is 0, 2, 4, ... for the various
+			   // channels, not endpoints.
+			   rx_break_r[wIndex_w[3:1]] = |wValue_w;
 			end
 		      default:
 			begin

rv32/boot.mif

@@ -1301,12 +1301,12 @@ CONTENT BEGIN
 050E : 706D6F63;
 050F : 64656C69;
 0510 : 3A6E6F20;
-0511 : 63654420;
-0512 : 20393220;
-0513 : 31323032;
-0514 : 3A393120;
-0515 : 333A3934;
-0516 : 00000A34;
+0511 : 6E614A20;
+0512 : 20382020;
+0513 : 32323032;
+0514 : 3A303220;
+0515 : 303A3230;
+0516 : 00000A37;
 0517 : 00000101;
 0518 : 00000000;
 0519 : 00000000;